JP3676271B2 - Transport stream processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
In the field of digital broadcasting, program elements such as video, audio, still images, character data, music data, and computer programs are transmitted in a transport packet format. The present invention relates to a transport stream processing apparatus that extracts a necessary transport packet or extracts necessary data when a data format in a payload of the transport packet is a section format.
[0002]
[Prior art]
In FIG. 1 of Japanese Patent Laid-Open No. 2000-23135, the header and entry data of digital data that are sequentially input are compared in a specific unit, and the current comparison result and the past comparison result are calculated by the determination integration unit. A section selection device is disclosed in which the determination holding unit holds the calculation result and continues these processes until the end of the comparison determination.
[0003]
[Problems to be solved by the invention]
In the section selection device described above, the comparison process takes time because the comparison between the digital data and the plurality of entries must be continued until the end of the comparison determination regardless of the necessity of comparison. Further, since one determination holding means must be provided for each entry, the circuit scale increases. In addition, it is difficult to realize a series of comparisons of PID comparison, section index comparison, and section comparison with the same hardware.
[0004]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a transport stream processing apparatus that can shorten the comparison processing time.
[0005]
Another object of the present invention is to provide a transport stream processing apparatus capable of reducing the circuit scale.
[0006]
Still another object of the present invention is to provide a transport stream processing apparatus capable of realizing a plurality of types of comparison with a single hardware.
[0007]
[Means for Solving the Problems]
According to one aspect of the present invention, a transport stream processing device includes a section data buffer, a section buffer control circuit, a section length determination circuit, n pattern memories, a memory control circuit, a comparison circuit, an entry A determination circuit. The section buffer control circuit writes m bytes from the beginning of the section data of the transport packet extracted from the transport stream to the section buffer. The section length determination circuit determines the section data length based on the data written in the section data buffer. The n pattern memories are memories that can be written / read from the host. The memory control circuit changes the access method of the n pattern memories according to the section data length. The comparison circuit changes the comparison method between the data in the section data buffer and the data read from the n pattern memories in accordance with the section data length. The entry determination circuit determines a matching entry based on the comparison result by the comparison circuit and the section data length. The transport stream processing device reads p patterns of data to be compared from n pattern memories in accordance with the section data length, and compares the p patterns from the beginning of the data in the section data buffer.
[0008]
Preferably, the data of the same entry is arranged at the same physical address of the n pattern memories, and the byte order in the same entry is changed according to the address.
[0009]
Preferably, data of a plurality of entries are arranged at the same physical address of the n pattern memories, and the data in the entries are divided and data are arranged at different physical addresses.
[0010]
According to another aspect of the present invention, a transport stream processing device includes a section data buffer, a section buffer control circuit, n pattern memories, a mode memory, a memory control circuit, a comparison circuit, and an entry determination. Circuit. The section buffer control circuit writes m bytes from the beginning of the section data of the transport packet extracted from the transport stream to the section buffer. The n pattern memories are memories that can be written / read from the host. The mode memory is a memory that can be written / read from the host. The memory control circuit writes / reads the pattern memory and mode memory during host access, and reads out the comparison memory when a start signal is input. The comparison circuit changes the comparison method between the data in the section data buffer and the data in the n pattern memories according to the value in the mode memory. The entry determination circuit determines a matching entry from the result from the comparison circuit and the value of the mode memory. In the above transport stream processing device, comparison can be made with a plurality of patterns per access by starting comparison with a start signal and changing the comparison method with the value of the mode memory.
[0011]
According to yet another aspect of the present invention, a transport stream processing device includes a section data buffer, a section buffer control circuit, a pattern memory, a tag memory, a memory control circuit, a comparison circuit, and a match address storage circuit. With. The section buffer control circuit writes m bytes from the beginning of the section data of the transport packet extracted from the transport stream to the section buffer. The pattern memory is a memory that can be written / read from the host. In the tag memory, the address of the pattern memory to be compared is written. The memory control circuit writes / reads the pattern memory or tag memory during host access, and reads the pattern memory and tag memory to read data to be compared when a start signal is input. The comparison circuit compares the data in the section data buffer with the data in the pattern memory and generates a stop signal from the value in the tag memory. The coincidence address storage circuit writes a value corresponding to the address coincident as a result of comparison by the comparison circuit to the tag memory. In the above transport stream processing device, when the start signal is activated, the data read from the pattern memory is compared with the value of the section data buffer by the valid address of the pattern memory written in the tag memory, and the matching address is tagged. Can be controlled to write to memory.
[0012]
According to yet another aspect of the present invention, a transport stream processing device includes a section data buffer, a section buffer control circuit, a pattern memory, a first tag register, a second tag register, and a memory control circuit. A comparison circuit, a priority encoder, a match result storage circuit, and a tag erasure circuit. The section buffer control circuit writes m bytes from the beginning of the section data of the transport packet extracted from the transport stream to the section buffer. The pattern memory is a memory that can be written / read from the host. The first tag register stores the address location of the pattern memory to be compared. The second tag register loads the value of the first tag register every time it compares. The memory control circuit writes / reads the pattern memory or the first tag register during host access, and transfers data from the first tag register to the second tag register when a start signal is input, In order to do this, the pattern memory is read. The comparison circuit compares the data in the section data buffer with the data in the pattern memory, and generates a stop signal from the value in the tag register. The priority encoder outputs the address of the pattern memory from the value of the second tag register. The match result storage circuit reflects the match result in the first tag register by the match signal from the comparison circuit. The tag erase circuit erases the corresponding value from the address of the priority encoder. In the transport stream processing apparatus, when the start signal becomes active, the value of the first tag register is transferred to the second tag register, and then the priority encoder detects the position where the value of the second tag register is 1. Then, for the address generated by the priority encoder, the tag erasure circuit writes the second tag register corresponding to the address to 0, and stores the match result in the first tag register depending on the mode and the address generated by the priority encoder. When the comparison circuit determines that the values match, 1 is written to the tag register and 0 is written if they do not match. The pattern memory is written in one clock until the tag cannot be erased or until a stop signal is input to the memory control circuit. Can be accessed continuously .
[0013]
The tag register can be used in three ways: a PID filter that detects PID matching of transport packets, a section index filter that associates PIDs with sections, and a section filter that detects section matching. It is preferable that the area of the rewritten arbitrary pattern memory can be used.
[0014]
According to yet another aspect of the present invention, a transport stream processing apparatus includes a section data buffer, a section buffer control circuit, a pattern memory, a memory control circuit, a comparison circuit, and a local memory. The section buffer control circuit extracts a transport packet from the transport stream and writes m bytes from the beginning of the section data in the payload of the transport packet to the section buffer. The pattern memory is a memory that can be written / read from the host. The memory control circuit writes / reads the pattern memory when accessing the host, and reads the pattern memory for comparison when a start signal is input. The comparison circuit compares the data in the section data buffer with the data in the pattern memory. The local memory is a memory that can write / read data from the host. In the above transport stream processing device, when the start n bytes of the section data straddle between the packets, the start n bytes of the section data before straddling is stored in the local memory, and when the next section is input, the local memory The start n bytes of this section data are read out, written into the section buffer, connected to the subsequent input section, and the connected section data is compared with the pattern memory.
[0015]
In the transport stream processing apparatus according to the present invention, the length of the digital data, that is, the section length is determined, and unnecessary conditions are not read, but only necessary conditions are read and compared, thereby shortening the comparison processing time.
[0016]
In addition, since the comparison is performed in units of entries after all the digital data to be compared is prepared, the determination holding means is not required if the comparison is completed when the comparison is completed.
[0017]
Also, multiple types of comparisons can be realized with a single hardware.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.
[0019]
(First embodiment)
FIG. 1 is a block diagram showing the overall configuration of a transport stream processing apparatus according to the first embodiment of the present invention. The transport stream processing device shown in FIG. 1 includes a PID filter 100, a section buffer control circuit 102, section data buffers 101a and 101b, a section length determination circuit 103, a memory control circuit 105, and pattern memories 104a and 104b. , A comparison circuit 106, an entry determination circuit 107, and a selector 108.
[0020]
The PID filter 100 extracts a predetermined transport packet from the transport stream, and supplies section data of the transport packet to the section buffer control circuit 102.
[0021]
The section buffer control circuit 102 extracts 16 bytes (0th to 15th bytes) from the head of the section data from the PID filter 100. Then, the 0 to 7th bytes of the extracted section data are written to the section data buffer 101a, and the 8th to 15th bytes are written to the section data buffer 101b.
[0022]
The section length determination circuit 103 obtains a section length SL based on a total of 12 bits including the lower 4 bits of the second byte from the head of the section data stored in the section data buffer 101a and 8 bits of the third byte. The section length SL is the length of the section data from the PID filter 100.
[0023]
A plurality of entries are stored in the pattern memories 104a and 104b. The entry is data for selecting section data from the PID filter 100.
[0024]
The memory control circuit 105 reads 8-byte data from the pattern memories 104a and 104b. When the section length SL is 9 bytes or more, one entry (16 bytes) is constituted by the 8-byte data read from the pattern memory 104a and the 8-byte data read from the pattern memory 104b. On the other hand, when the section length SL is 8 bytes or less, one entry (8 bytes) is constituted by 8 bytes of data read from the pattern memory 104a, and 8 bytes of data read from the pattern memory 104b. Another entry (8 bytes) is constructed.
[0025]
Comparison circuit 106 includes comparators 106a and 106b and selectors 106c to 106e. The selector 106c supplies the data read from the section data buffer 101a or the data read from the section data buffer 101b to the comparator 106b according to the section length SL from the section length determination circuit 103. The selector 106d gives the data read from the pattern memory 104a or the data read from the pattern memory 104b to the comparator 106a in accordance with a control signal from the memory control circuit 105. The comparator 106a gives “1” to the entry determination circuit 107 when the data read from the section data buffer 101a and the data given from the selector 106d match, and “0” when they do not match. The selector 106e supplies the data read from the pattern memory 104a or the data read from the pattern memory 104b to the comparator 106b in accordance with a control signal from the memory control circuit 105. The comparator 106b gives “1” to the entry determination circuit 107 when the data supplied from the selector 106c matches the data supplied from the selector 106e, and “0” when they do not match.
[0026]
The entry determination circuit 107 determines whether or not the section data read from the section data buffers 101a and 101b matches the entry read from the pattern memories 104a and 104b by a method according to the section length SL. This will be specifically described below. When the section length SL is 9 bytes or more, when the logical product of the output of the comparator 106a and the output of the comparator 106b is “1”, the section data read from the section data buffers 101a and 101b and the pattern memory 104a, It is determined that the entry read from 104b matches, and when the logical product is “0”, it is determined that they do not match. On the other hand, when the section length SL is 8 bytes or less, the determination is made based on the output of the comparator 106a and the output of the comparator 106b. When the output of the comparator 106a is “1”, it is determined that the section data read from the section data buffer 101a matches the entry read from the pattern memory 104a, and the output of the comparator 106a is “0”. When it is determined that there is a discrepancy. When the output of the comparator 106b is “1”, it is determined that the section data read from the section data buffer 101a matches the entry read from the pattern memory 104b, and the output of the comparator 106b is “0”. "", It is determined that there is a mismatch.
[0027]
The selector 108 selects the least significant bit AD [0] or “1” of the address AD [*: 0] from the memory control circuit 105 according to the control signal from the memory control circuit 105, and gives the address to the pattern memory 104b. Is output as the least significant bit. An address obtained by combining the least significant bit selected by the selector 307 with the address AD [*: 1] from the memory control circuit 105 is given to the pattern memory 104b.
[0028]
Next, the operation of the transport stream processing apparatus configured as described above will be described.
[0029]
In this transport stream processing apparatus, a plurality of entries to be compared must be written in the pattern memories 104a and 104b in advance. This writing is performed by access from a host (not shown) such as a microcomputer. An address map viewed from the host is shown in FIG. As shown in FIG. 2, 0 to 15 bytes of entry 0 are written in addresses 00h to 0fh. 0 to 15 bytes of entry 1 are written to addresses 10h to 1fh. Similarly, 0 to 15 bytes of entry k are written to addresses k0h to kfh. Although the address map seen from the host is as shown in FIG. 2, it is not physically arranged in this order due to the convenience of reading at the time of comparison. The physical address map is as shown in FIG. Referring to FIG. 3, one address is given here for 16 bytes of entry data. For example, an address 00h is given to 16 bytes of entry 0, and an address 01h is given to 16 bytes of entry 1. At even addresses (00h, 02h,...), 0 to 7 bytes of entry data are written to the pattern memory 104a and 8 to 15 bytes are written to the pattern memory 104b. On the other hand, at odd addresses (01h, 03h,...), 8 to 15 bytes of entry data are written to the pattern memory 104a and 0 to 7 bytes are written to the pattern memory 104b. In this way, a plurality of entries are written in advance in the pattern memories 104a and 104b.
[0030]
Then, the section buffer control circuit 102 extracts 16 bytes from the head of the section data. The 0th to 7th bytes are written to the section data buffer 101a, and the 8th to 15th bytes are written to the section data buffer 101b.
[0031]
When data is written to the section data buffers 101a and 101b, the section length determination circuit 103 obtains the section length SL. The internal operation of the comparison circuit 106 differs depending on whether the section length SL is 9 bytes or more and 8 bytes or less. In the following description, the section length SL is divided into 9 bytes or more and 8 bytes or less.
[0032]
(1) When section length SL is 9 bytes or more
The memory control circuit 105 controls the selector 108 so as to select the least significant bit AD [0] of the address AD [*: 0] from the memory control circuit 105. Therefore, the same address is given to the pattern memory 104a and the pattern memory 104b. According to this address, 8-byte data is read from the pattern memories 104a and 104b.
[0033]
When the address given from the memory control circuit 105 to the pattern memories 104a and 104b is an even number, the memory control circuit 105 controls the selector 106d to select and output the data read from the pattern memory 104a. The selector 106e is controlled to select and output the data read from 104b. On the other hand, when the addresses given from the memory control circuit 105 to the pattern memories 104a and 104b are odd numbers, the memory control circuit 105 controls the selector 106d to select and output the data read from the pattern memory 104b, The selector 106e is controlled so as to select and output data read from the pattern memory 104a.
[0034]
The comparator 106a of the comparison circuit 106 compares the 0th to 7th byte section data read from the section data buffer 101a with the 0th to 7th byte entry data selected by the selector 106d, and determines the result as an entry decision. Output to the circuit 107. The selector 106c selects the section data of the 8th to 15th bytes read from the section data buffer 101b and supplies the selected section data to the comparator 106b. The comparator 106b compares the 8th to 15th byte section data read from the section data buffer 101b with the 8th to 15th byte entry data selected by the selector 106e, and compares the result with the entry determination circuit 107. Output.
[0035]
The entry determination circuit 107 calculates the logical product of the output of the comparator 106a and the output of the comparator 106b and determines whether or not they match.
[0036]
Hereinafter, the above comparison operation will be described in more detail.
[0037]
As shown in FIG. 4A, the address 00h is given to the pattern memories 104a and 104b at the first clock. In response to this, the 0th to 7th bytes of entry 0 are read from the pattern memory 104a, and the 8th to 15th bytes of entry 0 are read from the pattern memory 104b. The 0th to 7th byte data of entry 0 read from the pattern memory 104a is selected by the selector 106d and given to the comparator 106a, and the 8th to 15th byte data of entry 0 read from the pattern memory 104b. Is selected by the selector 106e and supplied to the comparator 106b. The section data of 0 to 7 bytes read from the section data buffer 101a and the entry data of 0 to 7 bytes of entry 0 are compared by the comparator 106a, and 8 to 15 read from the section data buffer 101b. The section data of the byte and the 8th to 15th bytes of entry 0 are compared by the comparator 106b. Then, the entry determination circuit 107 determines whether the 0th to 15th byte section data read from the section data buffers 101a and 101b matches the 0th to 15th bytes of the entry 0. When it is determined that they match, the comparison process ends. When it is determined that they do not match, the comparison process with entry 1 is continued.
[0038]
If it is determined that they do not match, the address 01h is given to the pattern memories 104a and 104b at the second clock, as shown in FIG. 4B. In response to this, the 8th to 15th bytes of data in entry 1 are read from the pattern memory 104a, and the 0th to 7th bytes of entry 1 are read from the pattern memory 104b. The 0th to 7th byte data of entry 1 read from the pattern memory 104b is selected by the selector 106d and applied to the comparator 106a, and the 8th to 15th byte data of entry 1 read from the pattern memory 104a. Is selected by the selector 106e and supplied to the comparator 106b. The section data of 0 to 7 bytes read from the section data buffer 101a and the entry data of 0 to 7 bytes of entry 1 are compared by the comparator 106a, and 8 to 15 read from the section data buffer 101b. The section data of the byte and the 8th to 15th bytes of entry 1 are compared by the comparator 106b. Then, the entry determination circuit 107 determines whether the 0th to 15th byte section data read from the section data buffers 101a and 101b matches the 0th to 15th bytes of the entry 1. When it is determined that they match, the comparison process ends. When it is determined that they do not match, the comparison process with the entry 2 is continued.
[0039]
Thereafter, processing similar to that described above is performed until it is determined by the entry determination circuit 107 that the matching is performed or comparison processing with all entries is completed.
[0040]
As described above, when the section length SL is 9 bytes or more, one entry is compared per clock.
[0041]
(2) When section length SL is 8 bytes or less
The memory control circuit 105 generates only even addresses. The memory control circuit 105 controls the selector 108 so as to select “1”. Therefore, only even addresses are given to the pattern memory 104a and only odd addresses are given to the pattern memory 104b. According to this address, 8-byte data is read from the pattern memories 104a and 104b. The 8-byte data read from the pattern memory 104a and the 8-byte data read from the pattern memory 104b are the 0th to 7th byte data of different entries. The memory control circuit 105 controls the selector 106d to select and output the data read from the pattern memory 104a, and the selector 106e to select and output the data read from the pattern memory 104b. Control.
[0042]
The comparator 106a of the comparison circuit 106 compares the 0th to 7th byte section data read from the section data buffer 101a with the 0th to 7th byte entry data read from the pattern memory 104a, and compares the result. The data is output to the entry determination circuit 107. The selector 106c selects the 0th to 7th byte section data read from the section data buffer 101a and supplies the selected section data to the comparator 106b. The comparator 106b compares the 0th to 7th byte section data read from the section data buffer 101a with the 0th to 7th byte entry data read from the pattern memory 104b, and compares the result with the entry determination circuit. It outputs to 107.
[0043]
The entry determination circuit 107 determines the comparison result by the comparator 106a and the comparison result by the comparator 106b as the comparison result for each entry.
[0044]
Hereinafter, the above comparison operation will be described in more detail.
[0045]
As shown in FIG. 5A, at the first clock, the address 00h is given to the pattern memory 104a and the address 01h is given to the pattern memory 104b. In response to this, the 0th to 7th bytes of entry 0 are read from the pattern memory 104a, and the 0th to 7th bytes of entry 1 are read from the pattern memory 104b. The 0th to 7th byte data of entry 0 read from the pattern memory 104a is selected by the selector 106d and given to the comparator 106a, and the 0th to 7th byte data of entry 1 read from the pattern memory 104b. Is selected by the selector 106e and supplied to the comparator 106b. The 0 to 7 byte section data read from the section data buffer 101a and the 0 to 7 byte entry data of entry 0 are compared by the comparator 106a, and the 0 to 7 bytes read from the section data buffer 101a are compared. The section data of the byte and the 0th to 7th bytes of entry 1 are compared by the comparator 106b. When at least one of the comparison results of the comparators 106a and 106b indicates a match, the comparison process is terminated. When the comparison results of the comparators 106a and 106b indicate a mismatch, the comparison processing with the entry 2 and the entry 3 is continued.
[0046]
When the comparison results of the comparators 106a and 106b indicate a mismatch, as shown in FIG. 5B, the address 02h is given to the pattern memory 104a and the address 03h is given to the pattern memory 104b at the second clock. In response to this, the 0th to 7th bytes of entry 2 are read from the pattern memory 104a, and the 0th to 7th bytes of entry 3 are read from the pattern memory 104b. The 0th to 7th byte data of entry 2 read from the pattern memory 104a is selected by the selector 106d and applied to the comparator 106a, and the 0th to 7th byte data of entry 3 read from the pattern memory 104b. Is selected by the selector 106e and supplied to the comparator 106b. The 0- to 7-byte section data read from the section data buffer 101a and the entry 0 to 7-byte entry data of the entry 2 are compared by the comparator 106a, and the 0-7 bytes read from the section data buffer 101a are compared. The section data of the byte and the 0th to 7th bytes of entry 3 are compared by the comparator 106b. When at least one of the comparison results of the comparators 106a and 106b indicates a match, the comparison process is terminated. When the comparison results of the comparators 106a and 106b indicate a mismatch, the comparison processing with the entry 4 and the entry 5 is continued.
[0047]
Thereafter, processing similar to that described above is performed until at least one of the comparison results of the comparators 106a and 106b indicates a match or comparison processing with all entries is completed.
[0048]
Thus, when the section length SL is 8 bytes or less, a comparison with two entries per clock is executed.
[0049]
As described above, in the transport stream processing device according to the first embodiment, the bits to be compared among the section data are accumulated in the section data buffers 101a and 101b, and the comparison with each of the plurality of entries is performed in units of bits. This is done in units of entries. Therefore, the comparison process can be terminated when it matches a certain entry. As a result, it is not necessary to perform the comparison process for the remaining entries, so that the time required for the comparison process can be made shorter than before.
[0050]
Further, since the comparison is performed in entry units, it is not necessary to provide a means for holding the comparison result. Thereby, a circuit area can be made smaller than before.
[0051]
Usually, the number of section data included in one transport packet is larger when the section length is short than when it is long. That is, as the section length is shorter, the number of section data to be compared increases and the time required for the comparison process becomes longer. However, in the transport stream processing device according to the first embodiment, when the section length SL is 8 bytes or less, since it is compared with two entries at the same time, the time required for the comparison processing when the section length SL is 8 bytes or less and 9 It is possible to reduce the difference from the time required for the comparison process when the number of bytes is longer.
[0052]
(Second Embodiment)
FIG. 6 is a block diagram showing the configuration of the main part of the transport stream processing apparatus according to the second embodiment of the present invention. The transport stream processing apparatus shown in FIG. 6 further includes an inverter 201 in addition to the transport stream processing apparatus shown in FIG. Other configurations are the same as those of the transport stream processing apparatus shown in FIG. The inverter 201 inverts the least significant bit AD [0] of the address AD [*: 0] from the memory control circuit 105. The selector 108 selects the least significant bit AD [0] of the address AD [*: 0] from the memory control circuit 105 or the output / AD [0] of the inverter 201 according to the control signal from the memory control circuit 105, It is output as the least significant bit of the address given to the pattern memory 104b. An address obtained by combining the least significant bit AD [0] selected by the selector 108 with the address AD [*: 1] from the memory control circuit 105 is given to the pattern memory 104b.
[0053]
As in the first embodiment, in this transport stream processing apparatus, a plurality of entries to be compared must be written in advance in the pattern memories 104a and 104b. This writing is performed by access from a host (not shown) such as a microcomputer. The address map seen from the host is the same as that shown in FIG. The physical address map is as shown in FIG. Referring to FIG. 7, at even addresses (00h, 02h,...), 0 to 7 bytes of entry k (k is an even number) are written to pattern memory 104a, and 0 to 7 bytes of entry (k + 1) are pattern. It is written in the memory 104b. On the other hand, at odd addresses (01h, 03h,...), 8 to 15 bytes of entry (k + 1) are written to the pattern memory 104a, and 8 to 15 bytes of entry k are written to the pattern memory 104b.
[0054]
Next, the operation of the transport stream processing apparatus configured as described above will be described.
[0055]
The section buffer control circuit 102 extracts 16 bytes from the head of the section data. The 0th to 7th bytes are written to the section data buffer 101a, and the 8th to 15th bytes are written to the section data buffer 101b. When data is written to the section data buffers 101a and 101b, the section length determination circuit 103 obtains the section length SL. The internal operation of the comparison circuit 106 differs depending on whether the section length SL is 9 bytes or more and 8 bytes or less. In the following description, the section length SL is divided into 9 bytes or more and 8 bytes or less.
[0056]
(1) When section length SL is 9 bytes or more
The memory control circuit 105 controls the selector 108 so as to select the output / A [0] of the inverter 201. Therefore, the address given to the pattern memory 104b is an inversion of the least significant bit of the address given to the pattern memory 104a. According to these addresses, 8-byte data is read from the pattern memories 104a and 104b, respectively.
[0057]
When the address given from the memory control circuit 105 to the pattern memory 104a is an even number, the memory control circuit 105 controls the selector 106d to select and output the data read from the pattern memory 104a, and from the pattern memory 104b. The selector 106e is controlled to select and output the read data. On the other hand, when the address given from the memory control circuit 105 to the pattern memory 104a is an odd number, the memory control circuit 105 controls the selector 106d so as to select and output the data read from the pattern memory 104b. The selector 106e is controlled to select and output the data read from 104a.
[0058]
The comparator 106a of the comparison circuit 106 compares the 0th to 7th byte section data read from the section data buffer 101a with the 0th to 7th byte entry data selected by the selector 106d, and determines the result as an entry decision. Output to the circuit 107. The selector 106c selects the section data of the 8th to 15th bytes read from the section data buffer 101b and supplies the selected section data to the comparator 106b. The comparator 106b compares the 8th to 15th byte section data read from the section data buffer 101b with the 8th to 15th byte entry data selected by the selector 106e, and compares the result with the entry determination circuit 107. Output.
[0059]
The entry determination circuit 107 calculates the logical product of the output of the comparator 106a and the output of the comparator 106b and determines whether or not they match.
[0060]
Hereinafter, the comparison operation described above will be described in detail.
[0061]
As shown in FIG. 8A, the address 00h is given to the pattern memory 104a and the address 01h is given to the pattern memory 104b at the first clock. In response to this, the 0th to 7th bytes of entry 0 are read from the pattern memory 104a, and the 8th to 15th bytes of entry 0 are read from the pattern memory 104b. The 0th to 7th byte data of entry 0 read from the pattern memory 104a is selected by the selector 106d and given to the comparator 106a, and the 8th to 15th byte data of entry 0 read from the pattern memory 104b. Is selected by the selector 106e and supplied to the comparator 106b. The section data of 0 to 7 bytes read from the section data buffer 101a and the entry data of 0 to 7 bytes of entry 0 are compared by the comparator 106a, and 8 to 15 read from the section data buffer 101b. The section data of the byte and the 8th to 15th bytes of entry 0 are compared by the comparator 106b. Then, the entry determination circuit 107 determines whether the 0th to 15th byte section data read from the section data buffers 101a and 101b matches the 0th to 15th bytes of the entry 0. When it is determined that they match, the comparison process ends. When it is determined that they do not match, the comparison process with entry 1 is continued.
[0062]
When it is determined that they do not match, as shown in FIG. 8B, the address 01h is given to the pattern memory 104a and the address 00h is given to the pattern memory 104b at the second clock. In response to this, the 8th to 15th bytes of data in entry 1 are read from the pattern memory 104a, and the 0th to 7th bytes of entry 1 are read from the pattern memory 104b. The 0th to 7th byte data of entry 1 read from the pattern memory 104b is selected by the selector 106d and applied to the comparator 106a, and the 8th to 15th byte data of entry 1 read from the pattern memory 104a. Is selected by the selector 106e and supplied to the comparator 106b. The section data of 0 to 7 bytes read from the section data buffer 101a and the entry data of 0 to 7 bytes of entry 1 are compared by the comparator 106a, and 8 to 15 read from the section data buffer 101b. The section data of the byte and the 8th to 15th bytes of entry 1 are compared by the comparator 106b. Then, the entry determination circuit 107 determines whether or not the 0th to 15th byte section data read from the section data buffers 101a and 101b matches the 0th to 15th bytes of the entry 1. When it is determined that they match, the comparison process ends. When it is determined that they do not match, the comparison process with the entry 2 is continued.
[0063]
Thereafter, processing similar to that described above is performed until it is determined by the entry determination circuit 107 that they match or until the comparison processing with all entries is completed.
[0064]
As described above, when the section length SL is 9 bytes or more, one entry is compared per clock.
[0065]
(2) When section length SL is 8 bytes or less
The memory control circuit 105 generates only even addresses. Further, the memory control circuit 105 controls the selector 108 so as to select the least significant bit AD [0] of the address AD [*: 0] from the memory control circuit 105. Therefore, the same address is given to the pattern memory 104a and the pattern memory 104b. According to this address, 8-byte data is read from the pattern memories 104a and 104b. Therefore, the 8-byte data read from the pattern memory 104a and the 8-byte data read from the pattern memory 104b are the 0th to 7th byte data of different entries. The memory control circuit 105 controls the selector 106d to select and output the data read from the pattern memory 104a, and the selector 106e to select and output the data read from the pattern memory 104b. Control.
[0066]
The comparator 106a of the comparison circuit 106 compares the 0th to 7th byte section data read from the section data buffer 101a with the 0th to 7th byte entry data read from the pattern memory 104a, and compares the result. The data is output to the entry determination circuit 107. The selector 106c selects the 0th to 7th byte section data read from the section data buffer 101a and supplies the selected section data to the comparator 106b. The comparator 106b compares the 0th to 7th byte section data read from the section data buffer 101a with the 0th to 7th byte entry data read from the pattern memory 104b, and compares the result with the entry determination circuit. It outputs to 107.
[0067]
The entry determination circuit 107 determines the comparison result by the comparator 106a and the comparison result by the comparator 106b as the result for each entry.
[0068]
Hereinafter, the comparison operation described above will be described in detail.
[0069]
As shown in FIG. 9A, the address 00h is given to the pattern memories 104a and 104b at the first clock. In response to this, the 0th to 7th bytes of entry 0 are read from the pattern memory 104a, and the 0th to 7th bytes of entry 1 are read from the pattern memory 104b. The 0th to 7th byte data of entry 0 read from the pattern memory 104a is selected by the selector 106d and given to the comparator 106a, and the 0th to 7th byte data of entry 1 read from the pattern memory 104b. Is selected by the selector 106e and supplied to the comparator 106b. The 0 to 7 byte section data read from the section data buffer 101a and the 0 to 7 byte entry data of entry 0 are compared by the comparator 106a, and the 0 to 7 bytes read from the section data buffer 101a are compared. The section data of the byte and the 0th to 7th bytes of entry 1 are compared by the comparator 106b. When at least one of the comparison results of the comparators 106a and 106b indicates a match, the comparison process is terminated. When the comparison results of the comparators 106a and 106b indicate a mismatch, the comparison processing with the entry 2 and the entry 3 is continued.
[0070]
When the comparison results of the comparators 106a and 106b show a mismatch, as shown in FIG. 9B, the address 02h is given to the pattern memories 104a and 104b at the second clock. In response to this, the 0th to 7th bytes of entry 2 are read from the pattern memory 104a, and the 0th to 7th bytes of entry 3 are read from the pattern memory 104b. The 0th to 7th byte data of entry 2 read from the pattern memory 104a is selected by the selector 106d and applied to the comparator 106a, and the 0th to 7th byte data of entry 3 read from the pattern memory 104b. Is selected by the selector 106e and supplied to the comparator 106b. The 0- to 7-byte section data read from the section data buffer 101a and the entry 0 to 7-byte entry data of the entry 2 are compared by the comparator 106a, and the 0-7 bytes read from the section data buffer 101a are compared. The section data of the byte and the 0th to 7th bytes of entry 3 are compared by the comparator 106b. When at least one of the comparison results of the comparators 106a and 106b indicates a match, the comparison process is terminated. When the comparison results of the comparators 106a and 106b indicate a mismatch, the comparison processing with the entry 4 and the entry 5 is continued.
[0071]
Thereafter, processing similar to that described above is performed until at least one of the comparison results of the comparators 106a and 106b indicates a match or comparison processing with all entries is completed.
[0072]
Thus, when the section length SL is 8 bytes or less, a comparison with two entries per clock is executed.
[0073]
As described above, the transport stream processing apparatus according to the second embodiment can achieve the same effects as those described in the first embodiment.
[0074]
(Third embodiment)
FIG. 10 is a block diagram showing an overall configuration of a transport stream processing apparatus according to the third embodiment of the present invention. The transport stream processing device shown in FIG. 10 includes a PID filter 100, a section buffer control circuit 302, section data buffers 301a to 301d, a section length determination circuit 103, a memory control circuit 305, and pattern memories 304a to 304d. The comparison circuit 306 and the entry determination circuit 307 are provided.
[0075]
The PID filter 100 extracts a predetermined transport packet from the transport stream, and provides section data of the transport packet to the section buffer control circuit 302.
[0076]
The section buffer control circuit 302 takes out 16 bytes (0th to 15th bytes) from the head of the section data from the PID filter 100. The extracted section data from the 0th to 3rd bytes are stored in the section data buffer 301a, the 4th to 7th bytes are stored in the section data buffer 301b, and the 8th through 11th bytes are stored in the section data buffer 301c. The data up to the first is written in the section data buffer 301d.
[0077]
The section length determination circuit 103 obtains a section length SL based on a total of 12 bits including the lower 4 bits of the second byte from the head of the section data stored in the section data buffer 301a and 8 bits of the third byte.
[0078]
A plurality of entries are stored in the pattern memories 304a to 304d.
[0079]
The memory control circuit 305 reads 4-byte data from the pattern memories 304a to 304d. When the section length SL is 9 bytes or more, 4-byte data read from the pattern memory 304a, 4-byte data read from the pattern memory 304b, and 4-byte data read from the pattern memory 304c One entry (16 bytes) is composed of 4 bytes of data read from the pattern memory 304d. When the section length SL is 5 bytes or more and 8 bytes or less, one entry (8 bytes) is formed by 4 bytes of data read from the pattern memory 304a and 4 bytes of data read from the pattern memory 304b. Thus, another one entry (8 bytes) is constituted by the 4-byte data read from the pattern memory 304c and the 4-byte data read from the pattern memory 304d. When the section length SL is 4 bytes or less, one entry (4 bytes) is constituted by 4 bytes of data read from the pattern memory 304a, and another 4 bytes of data read from the pattern memory 304b. One entry (4 bytes) is configured, and another one entry (4 bytes) is configured by 4-byte data read from the pattern memory 304c, and 4-byte data is read from the pattern memory 304d. Constitutes another entry (4 bytes).
[0080]
Comparison circuit 306 includes comparators 306a-306d and selectors 306e, 306f. When the section length SL is 9 bytes or more, the selector 306e transfers the data read from the section data buffer 301a to the comparator 306a, the data read from the section data buffer 301b to the comparator 306b, and the section data buffer 301c. The data read from is supplied to the comparator 306c, and the data read from the section data buffer 301d is supplied to the comparator 306d. When the section length SL is 5 bytes or more and 8 bytes or less, the selector 306e supplies the data read from the section data buffer 301a to the comparators 306a and 306c, and the data read from the section data buffer 301b is the comparator. To 306b and 306d. When the section length SL is 4 bytes or less, the selector 306e provides the data read from the section data buffer 301a to the comparators 306a to 306d. The selector 306f gives the data read from the pattern memories 304a to 304d to the comparators 306a to 306d in accordance with the control signal from the memory control circuit 105. The comparators 306a to 306d give “1” to the entry determination circuit 307 when the data supplied from the selector 306e matches the data supplied from the selector 306f, and “0” when they do not match.
[0081]
The entry determination circuit 307 determines whether or not the section data read from the section data buffers 301a to 301d matches the entry read from the pattern memories 304a to 304d by a method according to the section length SL. This will be specifically described below. When the section length SL is 9 bytes or more, when the logical product of the output of the comparator 306a, the output of the comparator 306b, the output of the comparator 306c, and the output of the comparator 306d is "1", the section data buffers 301a to 301d It is determined that the section data read from the pattern data and the entries read from the pattern memories 304a to 304d match, and when the logical product is “0”, it is determined that they do not match. When the section length SL is 5 bytes or more and 8 bytes or less, the determination is made based on the outputs of the comparators 306a and 306b and the outputs of the comparators 306c and 306d. When the logical product of the output of the comparator 306a and the output of the comparator 306b is “1”, the section data read from the section data buffers 301a and 301b matches the entry read from the pattern memories 304a and 304b. Therefore, when the logical product is “0”, it is determined that there is a mismatch. When the logical product of the output of the comparator 306c and the output of the comparator 306d is "1", the section data read from the section data buffers 301a and 301b and the entry read from the pattern memories 304c and 304d Are determined to match, and when the logical product is “0”, it is determined that they do not match. When the section length SL is 4 bytes or less, the determination is made based on the outputs of the comparators 306a to 306d. When the output of the comparator 306a is “1”, it is determined that the section data read from the section data buffer 301a matches the entry read from the pattern memory 304a, and the output of the comparator 306a is “0”. When it is determined that there is a discrepancy. When the output of the comparator 306b is “1”, it is determined that the section data read from the section data buffer 301a matches the entry read from the pattern memory 304b, and the output of the comparator 306b is “0”. "", It is determined that there is a mismatch. When the output of the comparator 306c is “1”, it is determined that the section data read from the section data buffer 301a matches the entry read from the pattern memory 304c, and the output of the comparator 306c is “0”. "", It is determined that there is a mismatch. When the output of the comparator 306d is “1”, it is determined that the section data read from the section data buffer 301a matches the entry read from the pattern memory 304d, and the output of the comparator 306d is “0”. "", It is determined that there is a mismatch.
[0082]
Next, the operation of the transport stream processing apparatus configured as described above will be described.
[0083]
In this transport stream processing apparatus, a plurality of entries to be compared must be written in the pattern memories 304a to 304d in advance. This writing is performed by access from a host (not shown) such as a microcomputer. The physical address map is as shown in FIG. Referring to FIG. 11, here, one address is given for 16 bytes of entry data. Address 00h is given to a total of 16 bytes from 0 to 3 bytes of entry 0 to entry 3. The 0th to 3rd bytes of entry 0 to entry 3 are stored in pattern memories 304a, 304c, 304b, and 304d, respectively. Address 01h is given to a total of 16 bytes of the fourth to seventh bytes of entry 0 to entry 3. The fourth to seventh bytes of entry 0 to entry 3 are stored in pattern memories 304b, 304d, 304a, and 304c, respectively. Address 02h is given to a total of 16 bytes of the 8th to 11th bytes of entry 0 to entry 3. The 8th to 11th bytes of entry 0 to entry 3 are stored in pattern memories 304c, 304a, 304d, and 304b, respectively. Address 03h is given to a total of 16 bytes of the 12th to 15th bytes of entry 0 to entry 3. The 12th to 15th bytes of entry 0 to entry 3 are stored in pattern memories 304d, 304b, 304c, and 304a, respectively. In this way, a plurality of entries are written in advance in the pattern memories 304a to 304d.
[0084]
Then, the section buffer control circuit 302 extracts 16 bytes from the head of the section data. The 0th to 3rd bytes are written to the section data buffer 301a, the 4th to 7th bytes are written to the section data buffer 301b, the 8th to 11th bytes are written to the section data buffer 301c, and the 12th to 15th bytes are section data. It is written in the buffer 301d.
[0085]
When data is written to the section data buffers 301a to 301d, the section length determination circuit 103 obtains the section length SL. The internal operation of the comparison circuit 106 differs according to the section length SL. The following explanation is divided into (1) when the section length SL is 9 bytes or more, (2) when the section length SL is 5 bytes or more and 8 bytes or less, and (3) 4 bytes or less.
[0086]
(1) When section length SL is 9 bytes or more
As shown in FIG. 12A, at the first clock, address 00h is given to the pattern memory 304a, address 01h is given to the pattern memory 304b, address 02h is given to the pattern memory 304c, and address 03h is given to the pattern memory 304d. In response to this, the 0th to 3rd bytes of entry 0 are entered from the pattern memory 304a, the 4th to 7th bytes of entry 0 from the pattern memory 304b, and the 8th to 11th bytes of entry 0 are entered from the pattern memory 304c. Data of 12th to 15th bytes of 0 is read from the pattern memory 304d. The selector 306f stores the 0th to 3rd byte data of the entry 0 read from the pattern memory 304a into the comparator 306a and the 4th to 7th byte data of the entry 0 read from the pattern memory 304b into the comparator 306b. In addition, the 8th to 11th byte data of entry 0 read from the pattern memory 304c is supplied to the comparator 306c, and the 12th to 15th byte data of entry 0 read from the pattern memory 304d is supplied to the comparator 306d. . The selector 306e receives the 0th to 3rd byte section data from the section data buffer 301a to the comparator 306a, the 4th to 7th byte section data from the section data buffer 301b to the comparator 306b, and the section data buffer 301c The 8th to 11th byte section data is supplied to the comparator 306c, and the 12th to 15th byte section data from the section data buffer 301d is supplied to the comparator 306d. The 0 to 3 byte section data read from the section data buffer 301a and the 0 to 3 byte entry data of entry 0 are compared by the comparator 306a, and 4 to 7 read from the section data buffer 301b. The section data of the byte and the fourth to seventh bytes of the entry 0 are compared by the comparator 306b, and the section data of the eighth to eleventh bytes read from the section data buffer 301c and the eighth to eleventh bytes of the entry 0 are compared. The entry data is compared with the comparator 306c, and the 12th to 15th byte section data read from the section data buffer 301d is compared with the 12th to 15th bytes of the entry 0 by the comparator 306d. Then, the entry determination circuit 307 determines whether or not the 0th to 15th byte section data read from the section data buffers 301a to 301d matches the 0th to 15th bytes of the entry 0. When it is determined that they match, the comparison process ends. When it is determined that they do not match, the comparison process with entry 1 is continued.
[0087]
When it is determined that they do not match, as shown in FIG. 12B, at the second clock, the address 02h is in the pattern memory 304a, the address 03h is in the pattern memory 304b, the address 00h is in the pattern memory 304c, and the address 01h is in the pattern. Each is provided to the memory 304d. In response to this, the 8th to 11th byte data of entry 1 is from the pattern memory 304a, the 12th to 15th bytes of entry 1 are from the pattern memory 304b, and the 0th to 3rd bytes of entry 1 are from the pattern memory 304c. 1 to 4th to 7th bytes of data are read from the pattern memory 304d. The selector 306f stores the 8th to 11th byte data of entry 1 read from the pattern memory 304a in the comparator 306c, and the 12th to 15th byte data of entry 1 read from the pattern memory 304b in the comparator 306d. The 0th to 3rd byte data of entry 1 read from the pattern memory 304c is supplied to the comparator 306a, and the 4th to 7th byte data of entry 1 read from the pattern memory 304d is supplied to the comparator 306b. . The selector 306e receives the 0th to 3rd byte section data from the section data buffer 301a to the comparator 306a, the 4th to 7th byte section data from the section data buffer 301b to the comparator 306b, and the section data buffer 301c The 8th to 11th byte section data is supplied to the comparator 306c, and the 12th to 15th byte section data from the section data buffer 301d is supplied to the comparator 306d. The 0 to 3 byte section data read from the section data buffer 101a and the 0 to 3 byte entry data of entry 1 are compared by the comparator 306a, and 4 to 7 read from the section data buffer 301b. The section data of the byte and the fourth to seventh bytes of the entry 1 are compared by the comparator 306b, and the eighth to eleventh byte section data read from the section data buffer 301c and the eighth to eleventh bytes of the entry 1 are compared. The entry data is compared with the comparator 306c, and the 12th to 15th byte section data read from the section data buffer 301d is compared with the 12th to 15th bytes of the entry 1 by the comparator 306d. Then, the entry determination circuit 307 determines whether or not the 0th to 15th byte section data read from the section data buffers 301a to 301d matches the 0th to 15th bytes of the entry 1. When it is determined that they match, the comparison process ends. When it is determined that they do not match, the comparison process with the entry 2 is continued.
[0088]
Thereafter, processing similar to that described above is performed until it is determined by the entry determination circuit 307 that they match or until the comparison processing with all entries is completed.
[0089]
As described above, when the section length SL is 9 bytes or more, one entry is compared per clock.
[0090]
(2) When section length SL is 5 bytes or more and 8 bytes or less
As shown in FIG. 13A, at the first clock, the address 00h is given to the pattern memories 304a and 304c, and the address 01h is given to the pattern memories 304b and 304d. In response to this, the 0th to 3rd bytes of entry 0 are from the pattern memory 304a, the 4th to 7th bytes of entry 0 are from the pattern memory 304b, and the 0th to 3rd bytes of entry 1 are from the pattern memory 304c. The fourth to seventh bytes are read from the pattern memory 304d. The selector 306f stores the 0th to 3rd byte data of entry 0 read from the pattern memory 304a into the comparator 306a, and the 4th to 7th byte data of entry 0 read from the pattern memory 304b into the comparator 304b. The 0th to 3rd byte data of entry 1 read from the pattern memory 304c is stored in the comparator 304c, and the 4th to 7th byte data of entry 1 read from the pattern memory 304d is stored in the comparator 304d. give. The selector 306e supplies the 0-3rd byte section data from the section data buffer 301a to the comparators 306a and 306c, and the 4th-7th byte section data from the section data buffer 301b to the comparators 306b and 306d, respectively. The 0 to 3 byte section data read from the section data buffer 301a and the 0 to 3 byte entry data of entry 0 are compared by the comparator 306a, and 4 to 7 read from the section data buffer 301b. The section data of the byte and the fourth to seventh bytes of entry 0 are compared by the comparator 306b. The 0 to 3 byte section data read from the section data buffer 301a and the 0 to 3 byte entry data of entry 1 are compared by the comparator 306c, and 4 to 7 read from the section data buffer 301b. The section data of the byte and the 4th to 7th bytes of entry 1 are compared by the comparator 306d. When at least one of the logical product of the output of the comparator 306a and the output of the comparator 306b and the logical product of the output of the comparator 306c and the output of the comparator 306d is “1”, the comparison process is terminated. When the logical product of the output of the comparator 306a and the output of the comparator 306b and the logical product of the output of the comparator 306c and the output of the comparator 306d are both “0”, the comparison processing with the entry 2 and the entry 3 is continued. I do.
[0091]
When the logical product of the output of the comparator 306a and the output of the comparator 306b and the logical product of the output of the comparator 306c and the output of the comparator 306d are both “0”, as shown in FIG. At the second clock, the address 01h is given to the pattern memories 304a and 304c, and the address 00h is given to the pattern memories 304b and 304d. In response to this, the 4th to 7th bytes of entry 2 are from pattern memory 304a, the 0th to 3rd bytes of entry 2 are from pattern memory 304b, the 4th to 7th bytes of entry 3 are from pattern memory 304c, The 0th to 3rd bytes are read from the pattern memory 304d. The selector 306f stores the 4th to 7th byte data of the entry 2 read from the pattern memory 304a in the comparator 306b and the 0th to 3rd byte data of the entry 2 read from the pattern memory 304b to the comparator 304a. Further, the 4th to 7th byte data of the entry 3 read from the pattern memory 304c is stored in the comparator 304d, and the 0th to 3rd byte data of the entry 3 read from the pattern memory 304d is stored in the comparator 304c. give. The selector 306e supplies the 0-3rd byte section data from the section data buffer 301a to the comparators 306a and 306c, and the 4th-7th byte section data from the section data buffer 301b to the comparators 306b and 306d, respectively. The 0 to 3 byte section data read from the section data buffer 301a and the 0 to 3 byte entry data of entry 2 are compared by the comparator 306a, and 4 to 7 read from the section data buffer 301b. The section data of the byte and the 4th to 7th bytes of entry 2 are compared by the comparator 306b. The 0-3rd byte section data read from the section data buffer 301a and the 0-3rd byte entry data of entry 3 are compared by the comparator 306c, and 4-7 read from the section data buffer 301b. The section data of the byte and the 4th to 7th bytes of entry 3 are compared by the comparator 306d. When at least one of the logical product of the output of the comparator 306a and the output of the comparator 306b and the logical product of the output of the comparator 306c and the output of the comparator 306d is “1”, the comparison process is terminated. When the logical product of the output of the comparator 306a and the output of the comparator 306b and the logical product of the output of the comparator 306c and the output of the comparator 306d are both “0”, the comparison process with the entry 4 and the entry 5 is continued. I do.
[0092]
Thereafter, at least one of the logical product of the output of the comparator 306a and the output of the comparator 306b and the logical product of the output of the comparator 306c and the output of the comparator 306d indicates “1” or all entries. Until the comparison process is completed, the same process as described above is performed.
[0093]
As described above, when the section length SL is not less than 5 bytes and not more than 8 bytes, comparison with two entries per clock is executed.
[0094]
(3) When section length SL is 4 bytes or less
As shown in FIG. 14, the address 00h is given to the pattern memories 304a to 304d at the first clock. In response to this, the 0th to 3rd bytes of entry 0 are from the pattern memory 304a, the 0th to 3rd bytes of entry 2 are from the pattern memory 304b, and the 0th to 3rd bytes of entry 1 are from the pattern memory 304c. The 0th to 3rd bytes are read from the pattern memory 304d. The selector 306f stores the 0th to 3rd byte data of entry 0 read from the pattern memory 304a into the comparator 306a and the 0th to 3rd byte data of entry 2 read from the pattern memory 304b into the comparator 304c. The 0th to 3rd byte data of entry 1 read from the pattern memory 304c is stored in the comparator 304b, and the 0th to 3rd byte data of entry 3 read from the pattern memory 304d is stored in the comparator 304d. give. The selector 306e gives the 0th to 3rd byte section data from the section data buffer 301a to the comparators 306a to 306d. The 0 to 3 byte section data read from the section data buffer 301a and the 0 to 3 byte entry data of entry 0 are compared by the comparator 306a, and the 0 to 3 bytes read from the section data buffer 301a are compared. The section data of the byte and the 0th to 3rd bytes of the entry 1 are compared by the comparator 306b, and the 0th to 3rd byte of the section data read from the section data buffer 301a and the 0th to 3rd bytes of the entry 2 are compared. The entry data is compared by the comparator 306c, and the 0-3rd byte section data read from the section data buffer 301a and the 0-3rd byte of the entry 3 are compared by the comparator 306d. When at least one of the outputs from the comparators 306a to 306d indicates a match, the comparison process is terminated. When all the outputs of the comparators 306a to 306d indicate mismatch, the comparison processing with the fourth to seventh bytes of entry 0 to entry 3 is continued.
[0095]
Thereafter, processing similar to that described above is performed until at least one of the outputs of the comparators 306a to 306d indicates a match or comparison processing with all entries is completed.
[0096]
Thus, when the section length SL is 4 bytes or less, a comparison with four entries per clock is executed.
[0097]
As described above, the transport stream processing apparatus according to the third embodiment can achieve the same effects as those described in the first embodiment.
[0098]
(Fourth embodiment)
FIG. 15 is a block diagram showing an overall configuration of a transport stream processing apparatus according to the fourth embodiment of the present invention. The transport stream processing apparatus shown in FIG. 15 includes a PID filter 100, a section buffer control circuit 102, section data buffers 101a and 101b, pattern memories 604a and 604b, a memory control circuit 605, a comparison circuit 606, and an entry. A determination circuit 607 and a mode memory 608 are provided.
[0099]
A plurality of entries are written in the pattern memories 604a and 604b. The mode memory 608 is set with mode data indicating whether the mode is the 16-byte mode or the 8-byte mode, and data indicating whether the entry stored in the pattern memories 604a and 604b is valid or invalid. Has been.
[0100]
The data arrangement of the pattern memories 601a and 604b and the mode memory 608 is shown in FIG. 0 to 15 bytes of entry 0 are written from address 00h to 0fh. Similarly, 0 to 15 bytes of entry 1 are written at addresses 10 to 1 fh. However, in the 8-byte mode, one entry and 16 bytes are halved as in addresses 10 to 1fh, and one entry and 8 bytes are used as two sets, such as entry 1 and entry 1α. At this time, the mode memory 608 is set to the 8-byte mode and whether two sets of one entry and 8 bytes are valid or invalid. Similarly, the 16-byte mode and whether this entry is valid or invalid are set.
[0101]
The memory control circuit 605 reads 8-byte data from the pattern memories 604a and 604b. The memory control circuit 605 reads mode data from the mode memory 608. Further, the memory control circuit 605 reads data indicating whether the data read from the pattern memories 604a and 604b is valid or invalid from the mode memory 608.
[0102]
Comparison circuit 606 includes comparators 606a and 606b and a selector 606c. When the mode data from the mode memory 608 indicates the 8-byte mode, the selector 606c gives the data read from the section data buffer 101a to the comparator 606c, and when the mode data from the mode memory 608 indicates the 16-byte mode. Gives the data read from the section data buffer 101b to the comparator 606c. The comparator 606a gives “1” to the entry determination circuit 607 when the data read from the section data buffer 101a and the data read from the pattern memory 604a match, and “0” when they do not match. . The comparator 606b gives “1” to the entry determination circuit 607 when the data supplied from the selector 606c and the data read from the pattern memory 604b match, and “0” when they do not match.
[0103]
The entry determination circuit 607 determines whether or not the section data read from the section data buffers 101a and 101b matches the entry read from the pattern memories 604a and 604b according to the mode data from the mode memory 608. Judge with. When the mode data from the mode memory 608 indicates the 16-byte mode, the section read from the section data buffers 101a and 101b when the logical product of the output of the comparator 606a and the output of the comparator 606b is "1". It is determined that the data and the entries read from the pattern memories 604a and 604b match, and when the logical product is “0”, it is determined that they do not match. When the mode data from the mode memory 608 indicates the 8-byte mode, the determination is made based on the output of the comparator 606a and the output of the comparator 606b. Specifically, when the output of the comparator 606a is “1”, it is determined that the section data read from the section data buffer 101a matches the entry read from the pattern memory 604a, and the output of the comparator 606a. When “0” is “0”, it is determined that there is a mismatch. When the output of the comparator 101b is “1”, it is determined that the section data read from the section data buffer 101a matches the entry read from the pattern memory 604b, and the output of the comparator 604b is “0”. "", It is determined that there is a mismatch.
[0104]
Next, the operation of the transport stream processing apparatus configured as described above will be described. Here, the description will be made on the assumption that there are two types, an 8-byte mode and a 16-byte mode.
[0105]
The section buffer control circuit 102 extracts the first 16 bytes of the section data, writes the 0th to 7th bytes to the section data buffer 101a, and writes the 8th to 15th bytes to the section data buffer 101b. A plurality of 16-byte data for comparison with the section data written in the section data buffers 101a and 101b are written in the pattern memories 604a and 604b.
[0106]
When data is written in the section data buffers 101a and 101b, the comparison is started. The internal operation of the comparison circuit 606 differs depending on the mode data set in the mode memory 608.
[0107]
When the mode data set in the mode memory 608 indicates the 16-byte mode, the memory control circuit 605 reads 8-byte data from the pattern memory 604a and 8-byte data from the pattern memory 604b. When the 8-byte data in the pattern memory 604a and the 8-byte data in the pattern memory 604b are concatenated, 16-byte data of the same entry is obtained.
[0108]
The comparator 606a of the comparison circuit 606 compares the 0th to 7th byte data of the section data buffer 101a with the 0th to 7th byte data read from the pattern memory 604a, and the result is the entry determination circuit 607. Output to. The comparator 606b of the comparison circuit 606 compares the 8th to 15th byte data of the section data buffer 101b with the 8th to 15th byte data read from the pattern memory 604b, and determines the result as an entry determination. Output to the circuit 607. Since the above operation is performed with one clock, one entry can be compared per clock. Since the entry determination circuit 607 is notified from the mode memory 608 that the mode is the 16-byte mode, the logical product of the output of the comparator 606a and the output of the comparator 606b is taken to determine whether or not they match. .
[0109]
When the mode data set in the mode memory 608 indicates the 8-byte mode, the memory control circuit 605 reads 8-byte data from the pattern memory 604a and 8-byte data from the pattern memory 604b. The 8-byte data in the pattern memory 604a and the 8-byte data in the pattern memory 604b divide 16 bytes of 1 entry into half and use them as 8 bytes of 1 entry.
[0110]
The comparator 606a of the comparison circuit 606 compares the 0th to 7th byte data of the section data buffer 101a with the 0th to 7th byte data read from the pattern memory 604a, and the result is sent to the entry determination circuit 607. Output. The comparator 606b of the comparison circuit 606 compares the 0th to 7th byte data of the section data buffer 101a selected by the selector 606c with the 0th to 7th byte data read from the pattern memory 604b. The result is output to the entry determination circuit 607. Since the above operation is performed with one clock, two sets of one entry and eight bytes per clock can be compared. Further, since the entry determination circuit 607 is notified from the mode memory 608 that the mode is the 8-byte mode, the output of the comparator 606a and the output of the comparator 606b are each determined to be a result of 8 bytes per entry.
[0111]
As described above, the transport stream processing apparatus according to the fourth embodiment can achieve the same effects as those in the first embodiment.
[0112]
(Fifth embodiment)
FIG. 17 is a block diagram showing an overall configuration of a transport stream processing apparatus according to the fifth embodiment of the present invention. The transport stream processing device shown in FIG. 17 includes a section data buffer 801, a section buffer control circuit 802, a pattern memory 803, a tag memory 804, a memory control circuit 805, a comparison circuit 806, and a match address storage circuit 807. With.
[0113]
The section buffer control circuit 802 extracts 16 bytes (0th to 15th bytes) from the head of the section data and writes them to the section data buffer 801.
[0114]
In the section data buffer 801, section data of 16 bytes from the head, a necessary PID value, and a necessary index are set according to processing.
[0115]
The pattern memory 803 includes a PID area, an index area, and a section area. In the PID area, a plurality of entries for comparison with the PID value set in the section data buffer 801 are set. In the index area, a plurality of entries for comparison with the index set in the section data buffer 801 are set. In the section area, a plurality of entries (16 bytes) for comparison with the section data set in the section data buffer 801 are set. An entry set in the index area is associated with an entry set in the section area.
[0116]
Tag memory 804 includes regions 804a-804d. A value corresponding to the address of the PID area of the pattern memory 803 is set in the area 804a. A value corresponding to the address of the index area of the pattern memory 803 is set in the area 804b. In the area 804c, a value corresponding to the address of the entry in the section area associated with the entry in the index area determined to match by the comparison circuit 806 is set. In the area 804d, a value corresponding to the address of the entry in the section area determined to be matched by the comparison circuit 806 is set.
[0117]
The memory control circuit 805 controls access to the pattern memory 803 and the tag memory 804.
[0118]
The comparison circuit 806 determines whether or not the value set in the section data buffer 801 matches the value read from the pattern memory 803, and notifies the match address storage circuit 807 of the result.
[0119]
When it is determined that the comparison circuit 806 matches, the match address storage circuit 807 adds a predetermined value to the address generated by the memory control circuit 805 and writes it in the area 804d of the tag memory 804.
[0120]
Next, the operation of the transport stream processing apparatus configured as described above will be described. Here, the description will be divided into PID comparison, index comparison, and section comparison.
[0121]
<PID comparison>
First, a necessary PID value is set in the section data buffer 801, and a start signal is input to the memory control circuit 805. The memory control circuit 805 reads a value from the top of the area 804a of the tag memory 804, generates a read address of the pattern memory 803 based on this value, and reads entry data from the PID area. The comparison circuit 806 compares the value set in the section data buffer 801 with the value read from the pattern memory 803, and notifies the coincidence address storage circuit 807 if they match. When the comparison circuit 806 determines that there is a match, the match address storage circuit 807 holds a value (index) obtained by adding a specific value to the address generated by the memory control circuit 805. When the stop signal of the comparison circuit 806 is generated, the memory control circuit 805 determines that the comparison is completed and ends the comparison. The matched PID can be determined by this process.
[0122]
<Index comparison>
Next, in order to know the index of which section pattern is valid based on the matched PID, the matched address storage circuit 807 sets the held index in the section data buffer 801 and sets the start signal as the memory control circuit 805. To enter. The memory control circuit 805 reads a value from the head of the area 804b of the tag memory 804, generates an address of the pattern memory 803 based on this value, and reads entry data from the index area. The comparison circuit 806 compares the value set in the section data buffer 801 with the value read from the pattern memory 803, and notifies the coincidence address storage circuit 807 if they match. When the matching address storage circuit 807 determines that the comparison circuit 806 matches, the matching address storage circuit 807 adds a predetermined value to the address generated by the memory control circuit 805 and writes it in the area 804c of the tag memory 804. The memory control circuit 805 determines that the comparison is completed when the end of the area 804a of the tag memory 804 is reached, and ends the comparison. A valid index of the section pattern on the pattern memory necessary for this processing can be determined.
[0123]
<Section comparison>
When the section data is input after processing up to this point, the section buffer control circuit 802 extracts the first 16 bytes of the section data and writes the 0th to 15th bytes in the section data buffer 801. The memory control circuit 805 reads the value written from the head of the tag memory area 804c, generates an address of the pattern memory 803 based on this value, and reads entry data from the section area.
[0124]
The comparison circuit 806 compares the section data set in the section data buffer 801 with the entry data read from the pattern memory 803, and notifies the coincidence address storage circuit 807 if they match. When the comparison address storage circuit 807 determines that the comparison circuit 806 matches, the match address storage circuit 807 adds a predetermined value to the address generated by the memory control circuit 805 and writes it in the area 804d of the tag memory 804. The memory control circuit 805 determines that the comparison is completed when the stop signal of the comparison circuit 806 or the end of the area 804c of the tag memory 804 is reached by the mode (PID comparison, index comparison, section comparison), and ends the comparison.
[0125]
As described above, according to the transport stream processing apparatus of the fifth embodiment, it is possible to determine whether or not the matching PID matches the corresponding section pattern. That is, a series of comparisons of PID comparison, section index comparison, and section comparison can be realized with the same hardware.
[0126]
(Sixth embodiment)
FIG. 18 is a block diagram showing an overall configuration of a transport stream processing apparatus according to the sixth embodiment of the present invention. The transport stream processing apparatus shown in FIG. 18 includes a section data buffer 901, a section buffer control circuit 902, a pattern memory 903, tag registers 904a and 904b, a memory control circuit 905, a comparison circuit 906, and a match result storage. A circuit 907, a priority encoder 909, and a tag erasing circuit 910 are provided.
[0127]
As shown in FIG. 19, the pattern memory 903 and the tag register 904a include a PID comparison area, a section index area, and a section comparison area. In the PID comparison area of the pattern memory 903, a plurality of entries (2 bytes / 1 entry) for comparison with the PID value set in the section data buffer 901 are set. In the section index area, a plurality of entries (2 bytes / 1 entry) for comparison with the index set in the section data buffer 901 are set. In the section comparison area, a plurality of entries (16 bytes / 1 entry) for comparison with the section data set in the section data buffer 901 are set. An entry set in the section index area is associated with an entry set in the section comparison area.
[0128]
Next, the operation of this transport stream processing device will be described.
[0129]
First, when performing PID comparison, a necessary PID value is set in the PID comparison area of the pattern memory 903, and 1 is set in the PID comparison area of the tag register 904a. Next, a necessary PID value is set in the section data buffer 901, and a start signal is input to the memory control circuit 905. Then, the memory control circuit 905 copies the value set in the tag register 904a to the tag register 904b. Next, the priority encoder 909 searches for the first “1” in the tag register 904 b and gives this address to the memory control circuit 905 and the tag erasure circuit 910. The comparison circuit 906 compares the value read from the pattern memory 903 by the memory control circuit 905 with the value of the section data buffer 901, and issues a stop signal to the memory control circuit 905 if they match. Further, the tag erasing circuit 910 writes back and erases the first “1” searched by the priority encoder 909 to “0”. That is, the memory control circuit 905 repeats the above operation with one clock until the tag register 904b has “1” and the priority encoder 909 detects “1” or until the comparison circuit 906 determines that they match. . By this operation, PID comparison can be performed.
[0130]
When performing section pattern index comparison, a necessary section pattern index is set in the section index area of the pattern memory 903, and 1 is set in the section pattern index area of the tag register 904a. Next, a necessary PID index value is set in the section data buffer 901, and a start signal is input to the memory control circuit 905. Then, the memory control circuit 905 copies the value set in the tag register 904a to the tag register 904b. Next, the priority encoder 909 searches for the leading “1” in the tag register 904 b and gives this address to the memory control circuit 905 and the tag erasing circuit 910. The comparison circuit 906 compares the value read from the pattern memory 903 by the memory control circuit 905 with the value in the section data buffer 901, and notifies the match result storage circuit 907 if they match. The match result storage circuit 907 writes “1” at the section pattern position corresponding to the section pattern index of the tag register 904a. Further, the tag erasing circuit 910 writes back and erases the first “1” searched by the priority encoder 909 to “0”. That is, the memory control circuit 905 repeats the above operation with one clock as long as the tag register 904b has “1” and the priority encoder 909 detects “1”. By this operation, the section pattern index can be searched.
[0131]
When section comparison is performed, a necessary section pattern is set in the section comparison area of the pattern memory 903, and by searching for the section pattern index, “1” is set in the section pattern area of the tag register 904a. Next, by inputting section data to the section buffer control circuit 902, the section buffer control circuit 902 sets the top value in the section data buffer 901. As a result, a start signal is input to the memory control circuit 905. Then, the memory control circuit 905 copies the value of the tag register 904a to the tag register 904b. Next, the priority encoder 909 searches for the leading “1” in the tag register 904 b and gives this address to the memory control circuit 905 and the tag erasing circuit 910. The comparison circuit 906 compares the value read from the pattern memory 903 by the memory control circuit 905 with the value of the section data buffer 901. Further, the tag erasing circuit 910 writes back and erases the first “1” searched by the priority encoder 909 to “0”. That is, the memory control circuit 905 repeats the above operation with one clock as long as the tag register 904b has “1” and the priority encoder 909 detects “1”. By this operation, a matching section pattern can be searched.
[0132]
As described above, according to the sixth embodiment, a series of comparisons of PID comparison, section index comparison, and section comparison can be realized with the same hardware.
[0133]
(Seventh embodiment)
As shown in FIG. 20, the section data 1201 may be divided into a transport packet 1202 and a transport packet 1204. There may be a transport packet 1203 in between. In this case, when the first 16 bytes or less of the section data 1201 is divided, the divided data 1205 is once stored in the memory, and when the transport packet 1204 containing the next continuous data 1206 arrives, the division is performed. Concatenated data 1205 and continued data 1206 are extracted and compared by extracting 16 bytes from the head. An example of hardware for realizing this is shown in FIG.
[0134]
FIG. 21 is a block diagram showing the overall configuration of the transport stream processing apparatus according to the seventh embodiment of the present invention. The transport stream processing apparatus shown in FIG. 21 includes a section data buffer 1101, a section buffer control circuit 1102, a pattern memory 1103, a memory control circuit 1104, a comparison circuit 1105, and a local memory 1106.
[0135]
Next, the operation of the transport stream processing apparatus shown in FIG. 21 will be described. Here, a case where the last section data of the transport packet is 16 bytes or less will be described.
[0136]
When the packet end signal indicating the end of the transport packet is input to the section buffer control circuit 1102 when the section data is less than 16 bytes, the section buffer control circuit 1102 writes the section data to the section buffer 1101. This is notified to the memory control circuit 1104. The memory control circuit 1104 stores the data in the section data buffer 1101 in the local memory 1106.
[0137]
Next, when the section data stored in the local memory 1106 continues, the memory control unit 1104 first reads the section data from the local memory 1106 and writes it to the section buffer 1101. After that, the section buffer control circuit 1102 writes the section data input from the continuation of the section data read from the local memory 1106 to obtain 16-byte continuous section data. The memory control circuit 1104 reads the pattern memory 1103 and supplies data to the comparison circuit 1105. The comparison circuit 1105 compares the data in the section data buffer 1101 and the value in the pattern memory 1103 to determine whether or not they match.
[0138]
As described above, even if the head data to be compared of the section data is across the transport packet, the section data can be obtained by pattern matching of the head data.
[0139]
【The invention's effect】
In the transport stream processing apparatus according to the present invention, the comparison processing time can be shortened by judging the section length, reading out unnecessary conditions, and comparing only the necessary conditions.
[0140]
In addition, since the comparison is performed in units of entries after all the data to be compared is prepared, the determination holding means is not required if the comparison is completed when the comparison is completed.
[0141]
Also, multiple types of comparisons such as PID comparison, section index comparison, and section comparison can be realized with a single hardware.
[0142]
Also, comparison processing can be performed when a section spans between packets.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a transport stream processing apparatus according to a first embodiment of the present invention.
FIG. 2 is an address map viewed from the host.
FIG. 3 is a physical address map.
FIGS. 4A and 4B are diagrams showing comparison targets when the section length is 9 bytes or more. FIGS.
FIGS. 5A and 5B are diagrams showing comparison targets when the section length is 8 bytes or less. FIGS.
FIG. 6 is a block diagram showing a configuration of a main part of a transport stream processing apparatus according to a second embodiment of the present invention.
FIG. 7 is a physical address map.
FIGS. 8A and 8B are diagrams showing comparison targets when the section length is 9 bytes or more. FIGS.
FIGS. 9A and 9B are diagrams showing comparison targets when the section length is 8 bytes or less. FIGS.
FIG. 10 is a block diagram showing an overall configuration of a transport stream processing apparatus according to a third embodiment of the present invention.
FIG. 11 is a physical address map.
FIGS. 12A and 12B are diagrams showing comparison targets when the section length is 9 bytes or more. FIGS.
FIGS. 13A and 13B are diagrams showing comparison targets when the section length is 5 bytes or more and 8 bytes or less. FIGS.
FIG. 14 is a diagram showing an object to be compared when the section length is 4 bytes or less.
FIG. 15 is a block diagram showing an overall configuration of a transport stream processing apparatus according to a fourth embodiment of the present invention.
FIG. 16 is an address map of a pattern memory and a mode memory.
FIG. 17 is a block diagram showing an overall configuration of a transport stream processing apparatus according to a fifth embodiment of the present invention.
FIG. 18 is a block diagram showing an overall configuration of a transport stream processing apparatus according to a sixth embodiment of the present invention.
FIG. 19 is a diagram showing areas in a pattern memory and a tag register.
FIG. 20 is a diagram illustrating a configuration of a transport packet.
FIG. 21 is a block diagram showing an overall configuration of a transport stream processing apparatus according to a seventh embodiment of the present invention.
[Explanation of symbols]
101a, 101b, 301a-301d, 801, 901, 1101 Section data buffer
102, 302, 802, 902, 1102 Section buffer control circuit
103 Section length judgment circuit
104a, 104b, 304a-304d, 604a, 604b, 803, 903, 1103 pattern memory
105, 305, 605, 805, 905, 1104 Memory control circuit
106,306,606,806,906,1105 comparison circuit
107, 307, 607 entry judgment circuit
608 mode memory
804 Tag memory
807 Match address storage circuit
904a, 904b Tag register
907 Match result storage circuit
909 priority encoder
910 Tag erasure circuit
1106 Local memory

Claims (4)

A section data buffer;
A section buffer control circuit for writing m bytes from the beginning of the section data of the transport packet extracted from the transport stream to the section buffer;
A section length determination circuit for determining a section data length based on data written to the section data buffer;
N pattern memories writable / readable from the host;
A memory control circuit that changes an access method of the n pattern memories in accordance with the section data length;
A comparison circuit that changes a comparison method between the data in the section data buffer and the data read from the n pattern memories according to the section data length;
An entry determination circuit for determining a matching entry based on a comparison result by the comparison circuit and the section data length;
A transport stream processing apparatus, wherein data to be compared is read from the n pattern memories in accordance with the section data length, and the p patterns are respectively compared from the head of the data in the section data buffer. The transport stream processing device according to claim 1,
The transport stream processing apparatus, wherein data of the same entry is arranged at the same physical address of the n pattern memories, and the byte order in the same entry is changed according to the address. The transport stream processing device according to claim 1,
A transport stream processing apparatus, wherein data of a plurality of entries is arranged at the same physical address of the n pattern memories, data in the entry is divided and data is arranged at different physical addresses. A section data buffer;
A section buffer control circuit for writing m bytes from the beginning of the section data of the transport packet extracted from the transport stream to the section buffer;
N pattern memories writable / readable from the host;
A mode memory that can be written to and read from the host;
A memory control circuit for writing / reading the pattern memory and the mode memory at the time of host access, and reading out the comparison memory at the time of inputting a start signal;
A comparison circuit that changes a comparison method between the data in the section data buffer and the data in the n pattern memories according to the value of the mode memory;
An entry determination circuit for determining a matching entry from the result from the comparison circuit and the value of the mode memory;
A transport stream processing apparatus characterized in that comparison can be made with a start signal and comparison can be made with a plurality of patterns per access by changing the comparison method according to the value of the mode memory.

Images