JP3673463B2 - Error correction LSI device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an error correction LSI device that has a buffer in an error correction LSI and performs buffering, error correction, and data transfer to an external device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, an error correction LSI device that has a buffer in an error correction LSI and performs buffering, error correction, and data transfer to an external device has a large-capacity buffer mounted therein. This is because, when the error correction LSI device performs a series of data processing such as buffering, error correction, and data transfer to an external device during high-speed buffering, before the data transfer processing to the external device is completed. In order to prevent the preceding buffering from going round the finite buffer.
[0003]
A conventional error correction LSI device will be described below. FIG. 6 is a diagram showing a configuration of a DVD player device provided with a conventional error correction LSI device.
In FIG. 6, the DVD player device includes a spindle motor 601 that rotates an optical disc 608, an optical pickup unit 602 that reads data by applying a laser to the optical disc 608, and a servo motor unit 603 that performs positioning by the optical pickup unit 602. An error correction LSI device ODC (optical disc controller) 604 that performs signal processing and error correction, a system controller 605 that controls the overall operation of the DVD player device, a back-end processing unit 606 that performs MPEG decoding processing, The conventional error correction LSI device ODC 604 includes a large-capacity buffer 609 and a buffering processing unit for buffering data in the buffer 609. 10, in which the error correction processing unit 611 for performing error correction of the data buffered in the buffer 609, and a data transfer processor 612 transfers the data that has been error-corrected to an external device.
[0004]
The back-end processing unit 606 includes a large-capacity buffer 613 that holds data transferred from the error correction LSI device ODC 604 and an AV decoder 614 that performs MPEG decoding.
[0005]
Next, the data processing operation of the error correction LSI device ODC 604 in the DVD player device configured as described above will be described with reference to FIG.
FIG. 7 is a diagram showing a time chart of a series of data processing in the conventional error correction LSI device ODC.
[0006]
First, the error correction LSI device ODC 604 that has received a buffering command from the system controller 605 causes the buffering processing unit 610 to buffer the data of the optical disk 608 read via the optical pickup unit 602 into the large-capacity buffer 609. When buffering for one ECC block is completed, the error correction processing unit 611 performs error correction of the buffering data.
[0007]
Next, the error correction LSI device ODC 604 receives a data transfer command from the system controller 605, and the data transfer processing unit 612 transfers the error-corrected data to the back-end processing unit 606 at an arbitrary time. Here, the data is transferred after the error correction processing for one ECC block is completed.
[0008]
The data transferred from the error correction LSI device ODC 604 to the back-end processing unit 606 is held in the large-capacity buffer 613, is MPEG-encoded in the AV decoder 614, and is output to the host 607.
[0009]
[Problems to be solved by the invention]
However, the conventional error correction LSI device 604 has a problem that the chip size is large and the chip price is high because the large-capacity buffer 609 is mounted inside for the reason described above.
[0010]
Further, in the conventional error correction LSI device 604, a series of data processing commands such as buffering processing, error correction processing, and data transfer processing to an external device are executed by a plurality of commands by the system controller 605. There was also a problem that the load of the.
[0011]
The present invention solves the above-described conventional problems, and an object thereof is to provide an error correction LSI device that reduces the buffer size of the error correction LSI device and reduces the load on the system controller.
[0012]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, an error correction LSI device according to claim 1 of the present invention has a buffer inside the error correction LSI device, and after recording data is buffered in the buffer for error correction, an external device In the error correction LSI device that transfers the error-corrected recording data, the recording data buffering processing, error correction processing, and data transfer processing to the external device are managed in units of 1 ECC block of the data. 1 management means, a buffering processing time calculated from a buffering speed for buffering the recording data in the buffer, an error correction processing time calculated from a speed unique to the error correction LSI device, and an external device. data transfer processing time in a second managing means for managing the buffer, the buffer In sectors of the record data ring has a third managing means for managing said buffers, said first management means, and the second management means, buffering in 1ECC data block of the buffer It is determined whether or not the error correction processing for one ECC block and the data transfer processing to the external device for one ECC block are completed within the time, and if it is determined that the buffer is set to 2 ECC block buffer size. Ring, error correction, data transfer to an external device, and if it is determined to be impossible, using the third management unit, buffering with 2 ECC block buffer sizes in units of sectors obtained by subdividing 1 ECC block ; Error correction and data transfer to an external device are performed.
[0014]
An error correction LSI device according to claim 2 of the present invention is the error correction device according to claim 1 , wherein a command for buffering, a command for error correction, and a command for data transfer to an external device are provided. Are integrated, and buffering with 2 ECC block buffer size, error correction, and data transfer to an external device are performed with one command.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
Hereinafter, Embodiment 1 of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is a diagram showing a configuration of a DVD player device provided with an error correction LSI device of the present invention.
[0016]
In FIG. 1, a DVD player device includes a spindle motor 101 that rotates an optical disc, an optical pickup unit 102 that reads data by applying a laser to the optical disc, a servo motor unit 103 that positions the optical pickup, and an error that performs signal processing and error correction. A correction LSI device ODC (optical disk controller) 104, a system controller 105 that controls the operation of the entire system, a back-end processing unit 106 that performs MPEG decoding processing, a host 107 that displays video, and an optical disk 108 are included.
[0017]
In addition, the error correction LSI device ODC 104 includes a 2ECC block capacity buffer 109, a buffering processing unit 110 that buffers data in the buffer 109, an error correction processing unit 111 that performs error correction of buffered data, and an error corrected. Data transfer processing unit 112 for transferring the received data to the external device, buffering processing and data transfer processing to the external device, ECC block unit of the recording data, buffering processing, error correction processing, and transfer to the external device The ECC block / time buffer management control unit 113 manages the time required for processing, and the sector unit buffer management control unit 114 manages the buffering processing and the data transfer processing to the external device in units of sectors of the recording data. The
[0018]
The back-end processing unit 106 includes a large-capacity buffer 115 that holds data transferred from the error correction LSI device ODC 104 and an AV decoder 116 that performs MPEG decoding.
[0019]
The data processing operation of the error correction LSI device ODC104 of the first embodiment included in the DVD player device configured as described above will be described with reference to FIGS. FIG. 2 is a timing chart when the buffer is managed by the ECC block / time buffer management control unit, and buffering, error correction, and data transfer processing to an external device are normally performed in buffers for two ECC blocks. FIG.
[0020]
A series of processing operations of the error correction LSI device ODC 104 at this time will be described with reference to FIG. 2. An error received from the system controller 105 is a data processing command for performing a series of processing of buffering, error correction, and data transfer to an external device. In the correction LSI device ODC 104, the buffering processing unit 110 buffers the data of the optical disk 108 read through the optical pickup unit 102 in the 2ECC block capacity buffer 109. When the buffering for one ECC block is completed in the 2ECC block capacity buffer 109, the error correction processing unit 111 corrects the error of the buffering data. When the error correction for one ECC block is completed, the data transfer processing unit 112 is completed. Then, the error-corrected data is transferred to the back-end processing unit 106.
[0021]
In FIG. 2, the buffering processing unit 110 finishes the error correction for one ECC block and the data transfer processing to the external device for one ECC block within the buffering processing time for one ECC block. Buffering is performed, and at the time of this low-speed buffering, the ECC block / time buffer management control unit 113 manages the buffer 109 in units of time and ECC blocks. The management operation of the 2 ECC block capacity buffer 109 includes the time required for buffering one ECC block calculated from the buffering speed by the ECC block / time buffer management control unit 113, and the time required for error correction processing for one ECC block. Based on the time required for the data transfer processing time to the external device, it is determined and managed whether the error correction processing for one ECC block and the data transfer processing to the external device are completed within one ECC block buffering time. is there.
[0022]
The data processed by the error correction LSI device ODC 104 and transferred to the back-end processing unit 106 as described above is held by the large-capacity buffer 115, MPEG encoded by the AV decoder 116, and then sent to the host 107. Is output.
[0023]
Note that the time required for the buffering is calculated from the buffering speed, and the error correction processing time and the data transfer processing time to the external device do not depend on the buffering speed, but are error correction LSIs. This is calculated from the processing speed unique to the device 104.
[0024]
However, as shown in FIG. 2, when the buffering speed of the data is not performed at a low double speed as shown in FIG. 2, but when the buffering speed is high, as shown in FIG. In addition, the error correction processing for one ECC block and the data transfer processing to the external device are not covered. When such a state occurs, the ECC block / time buffer management control unit 113 determines that the buffer 109 is managed by the sector unit buffer management control unit 114 that manages the buffer in units of sectors, and a series of processing is continued.
[0025]
FIG. 4 shows a specific process when it is determined that the error correction process for one ECC block and the data transfer process to the external device are not stopped within one ECC block buffering time. FIG. 4 is a diagram showing a physical buffer image of the 2ECC block capacity buffer controlled by the sector unit buffer management control unit.
[0026]
The 1 ECC block in the first embodiment is divided into 16 sectors, and the buffer 109 shown in FIG. 4 is buffered by the buffering processing unit 110 to the second block of the 2 ECC block capacity buffer 109. Is completed, the error correction processing unit 111 starts the error correction processing of the second block, the data transfer processing unit 112 starts the transfer processing of the error corrected data of the first block to the back end unit 106, and the buffer The ring processing unit 110 is in a state of starting buffering from the beginning of the first ECC block that is the first block. As shown in FIG. 4, since there is still a margin of several sectors between the buffering processing pointer and the data transfer processing pointer, the sector unit buffer management control unit 114 sends the buffering processing pointer and the external device. The data transfer processing pointer is managed in units of sectors, and the processing is continued unless the pointer catches up at the sector level.
[0027]
Hereinafter, a series of data processing operations of the error correction LSI device ODC 104 according to the first embodiment will be described with reference to the flowchart of FIG. FIG. 5 is a flowchart showing a series of data processing of the error correction LSI device ODC104 in the first embodiment.
First, in step 501, the system controller 105 issues a data processing start command to the error correction LSI device ODC 104.
[0028]
Next, in step S502, the error correction LSI device ODC 104 that has received the data processing start command starts buffering of the first ECC block by the buffering processing unit 110.
[0029]
In step S503, when buffering of the first ECC block is completed, the process proceeds to step S504, where error correction processing unit 111 starts error correction processing of the first ECC block, and buffering processing unit 110 performs buffering of the second ECC block. Start the ring process.
[0030]
In step S505, when error correction for the first ECC block is completed, the process proceeds to step S506, where the data transfer processing unit 112 starts data transfer processing to the back-end processing unit 106 for the first ECC block, and the error correction processing unit 111. Thus, error correction for the second ECC block is started.
[0031]
If the ECC block / time buffer management control unit 113 determines in step S507 that the error correction for one ECC block and the data transfer processing to the external device are within the buffering time for one ECC block, the buffering process and the error are performed as they are. Correction processing and data transfer processing to an external device are continued, and determination processing by the ECC block / time buffer management control unit 113 is continued. If it is determined in step S507 that the error correction for one ECC block and the data transfer processing to the external device do not stop within the buffering time for one ECC block, the process proceeds to step S508.
[0032]
In step S508, the sector unit buffer management control unit 114 determines whether or not the buffering processing pointer has caught up with the data transfer processing pointer at the sector level. If not, the buffering processing and error correction processing are performed as they are. Then, the data transfer process to the external device is continued, and the determination process by the sector unit buffer management control unit 114 is continued. When it is determined that the buffering process pointer has caught up with the data transfer process pointer at the sector level, the buffering process is stopped in step S509.
[0033]
In the first embodiment, the data transfer destination from the error correction LSI device ODC 104 is the back end processing unit 106, but the back end processing unit 106 is externally attached to the outside of the error correction LSI device ODC 104. A mass storage device may be used.
[0034]
As described above, according to the error correction LSI device in the first embodiment , the error correction processing and the external device are performed within the buffering time of one ECC block by the first buffer management unit and the second management unit . If it is determined to be possible, a series of processes such as buffering with 2 ECC block size, error correction, and data transfer to an external device are performed. The third buffer management means manages the buffering processing pointer and the data transfer processing pointer to the external device at the sector level, and the buffering processing pointer, the error correction processing pointer, and the data transfer processing pointer catch up at the sector level. The process is executed until the buffering speed is reduced. Buffering in buffer of ECC blocks, error correction, can enable the data transfer processing to an external device, it is possible to realize a reduction in buffer size.
[0035]
In addition, according to the error correction LSI device of the present invention, it is inevitable and manageable to transfer data to an external device immediately after error correction of one ECC block by the above configuration. And a command for performing error correction and a command for performing data transfer to an external device can be integrated into a data transfer command, and the load on the system controller can be reduced.
[0036]
【The invention's effect】
As described above, according to the error correction LSI device according to the first aspect of the present invention has a buffer to internal error correcting LSI device, the recording data buffered in the buffer, after error correction, external In an error correction LSI device that transfers the error-corrected recording data to the device, the recording data buffering processing, error correction processing, and data transfer processing to an external device are managed in units of one ECC block of the data. A first management means, a buffering processing time calculated from a buffering speed for buffering the recording data in the buffer, and an error correction processing time and an external device calculated from a speed unique to the error correction LSI device. in a data transfer processing time to, and second management means for managing the buffer, the buffering In sectors of grayed recorded data, a third managing means for managing said buffers, said first management means, and the second management means, buffering in 1ECC data block of the buffer It is determined whether or not the error correction processing for one ECC block and the data transfer processing to the external device for one ECC block are completed within the time, and if it is determined that the buffer is set to 2 ECC block buffer size. Ring, error correction, data transfer to an external device, and if it is determined to be impossible, using the third management unit, buffering with 2 ECC block buffer sizes in units of sectors obtained by subdividing 1 ECC block ; Since error correction and data transfer to an external device are performed, 2EC is maintained without losing the conventional buffering double speed performance. Buffering in buffer block, error correction, to allow the data transfer processing to an external device, it is possible to realize a reduction in buffer size. In addition, more precise buffer management and effective buffer utilization are possible, and the processing capacity of buffering, error correction, and data transfer processing to an external device with a buffer size of 2 ECC blocks can be improved.
[0038]
According to an error correction LSI device of claim 2 of the present invention, in the error correction device of claim 1 , a command for buffering, a command for error correction, and data transfer to an external device are performed. Since commands are integrated and buffering with 2 ECC block buffer size, error correction, and data transfer to an external device are performed with one command, a command for performing conventional buffering, a command for performing error correction, A command for transferring data to an external device can be integrated into a data transfer command, and the load on the system controller can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a DVD player device using an error correction LSI device according to a first embodiment of the present invention;
FIG. 2 shows a timing chart when the buffering, error correction, and data transfer processing to the external device in the error correction LSI device according to the first embodiment of the present invention are operating normally. FIG.
FIG. 3 is a timing chart when error correction and data transfer processing to an external device are stopped within one ECC block buffering time in the error correction LSI device according to the first embodiment of the present invention;
FIG. 4 is a diagram for explaining buffer management in units of sectors in the error correction LSI device according to the first embodiment of the present invention;
FIG. 5 is a flowchart showing a processing operation of the error correction LSI device according to the first embodiment of the present invention.
FIG. 6 is a block diagram for explaining a DVD player device using a conventional error correction LSI device.
FIG. 7 is a diagram showing a time chart of data processing in a conventional error correction LSI device.
[Explanation of symbols]
101, 601 Spindle motor 102, 602 Optical pickup unit 103, 603 Servo motor unit 104, 604 Error correction LSI device ODC (optical disk controller)
105, 605 System controller 106, 606 Back-end processing unit 107, 607 Host 108, 608 Optical disk 109 2 ECC block capacity buffer 110, 610 Buffering processing unit 111, 611 Error correction processing unit 112, 612 Data transfer processing unit 113 ECC block Time buffer management control unit 114 Sector unit buffer management control unit 115, 613 Large capacity buffer 116, 614 AV decoder 609 Large capacity buffer

Claims (2)

In the error correction LSI device having a buffer inside the error correction LSI device, buffering the recording data in the buffer, correcting the error, and then transferring the recording data corrected by the error to the external device,
A first management means for managing the buffering process of the recording data, the error correction process, and the data transfer process to an external device in units of one ECC block;
A buffering processing time calculated from a buffering speed for buffering the recording data in the buffer; an error correction processing time calculated from a speed unique to the error correction LSI device; and a data transfer processing time to an external device; A second management means for managing the buffer ;
A third management means for managing the buffer in units of sectors of the buffered recording data;
By the first management means and the second management means, error correction processing for one ECC block and data transfer processing to an external device for one ECC block within the buffering processing time for one ECC data block of the buffer If it is determined to be possible, buffering with 2 ECC block buffer size, error correction, and data transfer to an external device are performed. Using the management means 3, buffering with 2 ECC block buffer size, error correction, and data transfer to an external device are performed in units of sectors obtained by subdividing 1 ECC block .
An error correction LSI device characterized by that. The error correction device according to claim 1 ,
A command to perform buffering, a command to perform error correction, and a command to perform data transfer to an external device are integrated, and buffering, error correction, and data transfer to an external device are performed with a single ECC command. I do,
An error correction LSI device characterized by that.

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