JP3666607B2 - Plasma panel driving method, driving apparatus, and plasma panel - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a high-voltage circuit technology for driving a display panel constituted by a display element having a memory function, and in particular, a current path between drive circuits in a display device including an AC (alternating current) type plasma panel. It is related with the technology which simplifies.
[0002]
Currently, there are two types of AC plasma panels: a two-electrode type that performs selective discharge (address discharge) and sustain discharge using two electrodes, and a three-electrode type that performs address discharge using a third electrode.
[0003]
In a two-electrode type color plasma panel that performs gradation display, a phosphor formed in a discharge cell is excited by ultraviolet rays generated by discharge. Since positively charged ions generated simultaneously with ultraviolet rays by the discharge collide with the phosphor, the phosphor is greatly damaged by this impact. The two-electrode type has a configuration in which ions generated by discharge directly collide with the phosphor, and thus the lifetime of the phosphor is reduced. In order to avoid this, a three-electrode structure using surface discharge is generally used as a color plasma panel.
[0004]
In the three-electrode type plasma panel, first and second electrodes for performing sustain discharge and a third electrode for selecting a cell are arranged. Among the three-electrode type plasma panels, there are a type in which the third electrode is formed on the same substrate as the first and second electrodes in which the sustain discharge is performed, and a type in which the third electrode is disposed on the opposite substrate. Further, even when the third electrode is formed on the same substrate, a mold in which the third electrode is disposed on the first and second electrodes for performing the sustain discharge, and the third electrode under the first electrode is disposed. There is a type to place.
[0005]
On the other hand, when the three-electrode type plasma panel is divided from the display method, there are a transmission type in which visible light emitted from the phosphor is transmitted and a reflection type in which light reflected from the phosphor is viewed. When divided according to how the barriers (ribs, barriers) are used, a type in which the barriers are provided in four directions so as to surround the cells to be discharged (hereinafter referred to as “discharge cells”) and completely sealed, and the barriers are provided only on one substrate, There is a type in which spatial coupling is cut by optimizing the gap (distance) between the electrodes with respect to the other substrate. The barrier is used to break a spatial coupling between a cell that is a unit for discharging and an adjacent cell.
[0006]
The plasma panel in which many types are developed as described above is suitable for a large panel because of manufacturing advantages. However, as the panel becomes larger, the scale of wiring increases because it handles a larger current (electric power).
[0007]
Therefore, in response to the increase in the size of the plasma panel, a contrivance has been made to prevent adverse effects such as an increase in current consumption accompanying the increase in size while maintaining the performance of the panel itself.
[0008]
The present invention takes an example of a display device using an AC plasma panel that performs surface discharge with a three-electrode type as a display device, simplifies power supply wiring between drive circuit blocks for each electrode, and increases the size and integration of the device. Is what you do.
[0009]
[Prior art]
A conventional three-electrode type / surface discharge type / AC type plasma panel will be described with reference to the drawings. FIG. 13 is a plan view of a conventional plasma panel, and FIG. 14 is a cross-sectional view of the plasma panel. (A) is a cross-sectional view in a direction horizontal to the address electrodes, and (B) is a cross-sectional view in a direction perpendicular to the address electrodes.
[0010]
As shown in FIG. 13, a three-electrode AC plasma panel applies sustain pulses (sustain pulses) alternately to two sustain electrodes (X electrode and Yn electrode (1 <n <N)), and addresses A cell is selected by the electrode An (1 <n <M).
[0011]
As a cross-sectional structure of the panel P, as shown in FIG. 14, the panel P is constituted by two glass substrates 40 and 49. The first substrate (front glass substrate) 49 includes a first (X electrode) 50 and a second electrode (Y electrode) 51 which are parallel sustain electrodes, and these electrodes are transparent to the bus electrode 47. An electrode 48 is used. Since the transparent electrode 48 has a role of transmitting the reflected light from the phosphor 42, the transparent electrode 48 is formed of ITO (transparent conductive film mainly composed of oxide oxide) or the like. In addition, the bus electrode 47 is made of chromium (Cr) or copper (Cu) because it needs to be made of a low resistance material in order to prevent voltage drop due to electrode resistance. These are covered with a dielectric layer (glass) 46, and an MgO (magnesium oxide) film is formed as a protective film 45 on the discharge surface. The second substrate 40 facing the first substrate 49 is provided with a third electrode (address electrode) 54 in a direction orthogonal to the sustain electrodes 50 and 51. A barrier 53 is formed between the address electrodes 54, and a phosphor 42 having red, green, and blue emission characteristics is formed between the barriers 53 so as to cover the address electrode 54. Two glass substrates 49 and 40 are assembled so that the ridge of the barrier 53 and the MgO film 45 are in close contact with each other.
[0012]
The plasma panel P sustains discharge by applying a sustain voltage to the sustain electrodes, and emits phosphors.
First, wall charges are generated by discharging with a high voltage (write voltage) pulse (write pulse). Ions that are positive charges generated by the discharge are accumulated on the surface of the insulating layer on the electrode to which a negative voltage is applied. Similarly, negatively charged electrons are accumulated on the surface of the insulating layer on the electrode to which a positive voltage is applied. Next, when a pulse (sustain pulse) having a voltage (sustain voltage) lower than the previous one having a different polarity is applied to the address electrode An (1 <n <M), the voltage due to the wall charges accumulated before is added. As a result, the voltage with respect to the discharge space becomes large, and discharge is started beyond the threshold value of the discharge voltage. One discharge ends in a period of 1 μs to several μs immediately after the pulse application. In other words, a cell that has once written discharge and generated wall charges has a feature that it continues discharge by alternately applying sustain pulses with opposite polarity. This phenomenon is called a memory effect or a memory function. In general, an AC plasma panel performs display using this memory effect.
[0013]
FIG. 15 shows a peripheral circuit for driving the plasma panel shown in FIGS.
Each of the address electrodes A1 to AM is connected to an address driver 66, and an address pulse at the time of address discharge is applied by the address driver 66. The Y electrodes Y1 to Yn are individually connected to the scan driver 68. The scan driver 68 is connected to the Y-side common driver 63, and a pulse at the time of address discharge is applied to the Y electrodes Y1 to Yn via the scan driver 63. The X side common driver 61 generates a write pulse, a sustain pulse, and the like.
[0014]
These driver circuits are controlled by the control circuit 64. The control circuit 64 operates based on a synchronization signal and a display data signal from the outside.
FIG. 16 shows driving waveforms according to the conventional driving method when the plasma panel shown in FIGS. 13 and 14 is driven by the circuit shown in FIG. FIG. 16 shows an outline of the operation in one subfield period in the so-called “address / sustain discharge period separated type / write address system”.
[0015]
As can be seen from FIG. 16, one subfield is divided into a reset period, an address period, and a sustain discharge period. In the reset period, an erase discharge is performed by applying a narrow erase pulse in order to erase the cells that have been lit in the previous subfield. Due to the erase discharge accompanying this narrow erase pulse, the state of all cells in the panel becomes uniform with no wall charges.
[0016]
Next, in the address period, address discharge is performed line-sequentially in order to turn on / off the cells according to the display data. First, a scan pulse of −VY level (about −150 V) is applied to the Y electrode. At the same time, an address pulse of voltage Va (about 50 V) is selectively applied to the address electrode corresponding to the cell in the address electrode where sustain discharge occurs, that is, the cell to be lit. Discharge occurs between the address electrode and the Y electrode of the cell to be lit. This is used as priming, and the process immediately shifts to discharge between the X electrode (voltage VX = 50 V) and the Y electrode. As a result, in the selected cell of the selected line, wall charges of an amount capable of sustain discharge accumulate on the X electrode and the MgO surface on the Y electrode.
[0017]
Thereafter, the same operation is sequentially performed on the other display lines, and new display data is written on all the display lines.
Thereafter, during the sustain discharge period, a sustain pulse having a voltage of Vs (about 180 V) is alternately applied to the Y electrode and the X electrode to perform a sustain discharge, and an image display of one subfield is performed. In the “address / sustain discharge period separation type / write address system”, the luminance is determined by the length of the sustain discharge period, that is, the number of sustain pulses.
[0018]
Specifically, as shown in FIG. 16, multi-gradation display (256 gradation display) is performed. For example, in this example, one frame is divided into eight subfields: SF1, SF2, SF3, SF4, SF5, SF6, SF7, and SF8. In these subfields SF1 to SF8, the reset period and the address period have the same length. The length of the sustain discharge period is a ratio of 1: 2: 4: 8: 16: 32: 64: 128. Accordingly, by selecting a subfield to be lit, a difference in luminance of 256 gradations from 0 to 255 can be displayed.
[0019]
[Problems to be solved by the invention]
However, if the panel is to be enlarged using the above conventional plasma panel driving method, the first problem is that there is a high risk of causing a malfunction of the logic, and a circuit necessary for driving the panel is provided due to an increase in wiring patterns. The second problem that it becomes difficult, and the third problem that the margin of the operating voltage is narrowed arise.
[0020]
The problem in this conventional example is demonstrated based on FIG.
FIG. 17A is a diagram schematically showing a driving means for applying a sustain pulse to the X electrode and the Y electrode, a power source between the driving means, and a GND wiring pattern. (B) is a diagram schematically showing the circuit function of the driving means and the current circuit during sustain discharge, and (C) is a diagram showing the timing of current flow when a sustain pulse is applied.
[0021]
In the AC type plasma panel, a sustain voltage is alternately applied between two sustain electrodes to perform a sustain discharge, thereby causing the phosphor to emit light. Considering the current in this case (see FIG. 17B), first, when a sustain pulse composed of the voltage Vs is applied to the X electrode, the power source → the X side driving means 71 (upside SW 78) → the X electrode of the panel P → Discharge current in each cell → Y electrode of panel P → Y side driving means 72 (downside SW 77) → Current flows to GND. The direction of the current that flows when the pulse is removed is the opposite.
[0022]
On the other hand, when a sustain pulse consisting of the voltage Vs is applied to the Y electrode, the power source → the Y side driving means 72 (upside SW 76) → the Y electrode of the panel P → the discharge current of each cell → the X electrode of the panel P → the X side. Current flows from the drive means 71 (downside SW 79) to GND. Similarly, when removing pulses, current flows in the opposite direction.
[0023]
A current waveform in the above operation is shown in FIG.
When the sustain pulse is applied to the X electrodes, the charge current (T1) for the capacity for charging the capacity between the electrodes, the discharge current (T2) due to gas discharge, and the discharge current (T3) for the capacity that flows when the sustain pulse is removed. ) Flows. Further, when the sustain pulse is applied to the Y electrode, the charge current (T4) for the capacity for charging the capacity between the electrodes, the discharge current (T5) due to gas discharge, and the discharge current (T6) for the capacity that flows when the sustain pulse is removed. ) Flows.
[0024]
The point to be noted here is that the large current path is composed of two systems of the power supply line and the GND line between the driving means on the X side and the Y side. In particular, as the size of the plasma panel increases, the X-side drive means 71 is arranged closer to the X electrode lead-out terminal and the Y-side drive means 72 is placed closer to the Y-electrode lead-out terminal. It will be longer. Furthermore, when the panel is enlarged, the amount of current handled by the driving means increases.
[0025]
For this reason, unless the impedance of the path is sufficiently low, the GND potential that is the reference potential of the logic system varies depending on the location, which may cause a malfunction of the logic (first problem).
[0026]
Further, on the back surface of the panel, it is necessary to mount a control circuit (logic circuit), an interface circuit (which converts a video signal into a digital signal), and a circuit for generating a DC power source necessary for driving the panel from an AC power source. . Therefore, wiring two power supply patterns that require a large area in this portion is a big problem in securing a mounting area for various circuits (second problem).
[0027]
Furthermore, the wall charge accumulation state between the address electrode and the Y electrode for performing address discharge needs to be uniform in any cell at the timing immediately before the address period starts. However, when the sustain discharge is performed, some wall charges are accumulated on the address electrode side. This wall charge cannot be completely erased even by the narrow pulse used in the reset period. This is because the narrow erase pulse erases the electric charge between the X electrode and the Y electrode. Therefore, it is difficult to completely erase the wall charges accumulated on the address electrode side, so that the operating voltage margin is narrowed (third problem).
[0028]
In view of the above problems, it is an object of the present invention to provide a plasma panel driving method, a driving apparatus, and an image display apparatus that are free from malfunction, have a small wiring area, and have a wide margin of operating voltage.
[0033]
[Means for Solving the Problems]
  FIG. 1 shows the configuration of the invention according to the first principle.
  FIG. 2 shows a claim according to the second principle.1The structure of the invention described in 1 is shown.
  Claim1The plasma panel driving apparatus 101 described in 1) includes at least a pair of electrodes arranged in parallel to perform a sustain discharge, and an address electrode arranged to cross the pair of electrodes to supply display data. A first signal line for supplying a positive sustain pulse signal having a positive polarity with respect to a reference potential to one of the pair of electrodes, and the reference A second signal line that supplies a negative sustain pulse signal having a negative polarity with respect to the potential to one of the pair of electrodes, and when supplying the positive sustain pulse signal, When grounding the second signal line and supplying the positive sustain pulse signal to one of the pair of electrodes from the first signal line and supplying the negative sustain pulse signal, With grounding the serial first signal line, and a second signal line so as to supply the negative sustain pulse signal to one of said pair of electrodes.
[0034]
  FIG. 3 shows a claim according to the third principle.2The structure of the invention described in 1 is shown.
  Claim2The plasma panel driving apparatus according to claim 2, wherein the plasma panel driving apparatus according to claim 2 includes a first signal line that supplies the positive sustain pulse signal to one of the pair of electrodes, and the negative electrode. A first signal line including a second signal line for supplying a side sustain pulse signal to one of the pair of electrodes, and a capacitor provided between the first and second signal lines. When the positive side sustain pulse signal is supplied during the sustain discharge period, the second signal line is grounded prior to the supply, and the second signal line is grounded. When accumulating electric charge in the capacitor from the signal line side and supplying the negative sustain pulse signal in the sustain discharge period, the first signal line is grounded prior to the supply, Capacitor with the charges accumulated in, the positive sustain pulse signal or the negative sustain pulse signal, configured to provide the one of the pair of electrodes.
[0035]
  Claim3The plasma panel described in 1 is provided with a first substrate in which first and second electrodes that perform sustain discharge are arranged in parallel to each other, and a third electrode that is disposed to face the first substrate and selects a discharge cell. And a second substrate disposed perpendicular to the first electrode and the second electrode, and the plasma panel corresponding to a portion where the first electrode and the third electrode intersect The insulating layer covering the third electrode is thicker than the insulating layer covering the third electrode corresponding to the intersecting portion of the second electrode and the third electrode, A positive sustain pulse signal having a positive polarity with respect to a reference potential and a negative sustain pulse signal having a negative amplitude with respect to the reference potential with respect to one of the first and second electrodes. It is configured to be supplied alternately.
[0045]
[Action]
  Claim1The first signal line for supplying the positive sustain pulse signal to one of the pair of electrodes and the second signal line for supplying the negative sustain pulse signal to one of the pair of electrodes. When supplying the positive sustain pulse signal during the sustain discharge period, the second signal line is grounded, and the positive sustain pulse signal is sent from the first signal line to the pair of electrodes. When the negative sustain pulse signal is supplied to one side, the first signal line is grounded and the negative sustain pulse signal is supplied to one of the pair of electrodes from the second signal line.
[0046]
  Claim2According to the invention described inIn the sustain discharge period, a positive sustain pulse signal having a positive polarity with respect to the reference potential and a negative sustain pulse signal having a negative amplitude are alternately supplied to one of the pair of electrodes. Control as follows. At this time,A first signal line for supplying a positive sustain pulse signal to one of the pair of electrodes; a second signal line for supplying a negative sustain pulse signal to one of the pair of electrodes; A capacitor provided between the two signal lines, and when charge is accumulated in the capacitor from the first signal line side and the positive sustain pulse signal is supplied during the sustain discharge period, When the second signal line is grounded in advance and electric charge is accumulated in the capacitor from the second signal line side and the negative sustain pulse signal is supplied in the sustain discharge period, the second signal line is supplied prior to the supply. One signal line is grounded, and a positive sustain pulse signal or a negative sustain pulse signal is supplied to one of the pair of electrodes using the charge accumulated in the capacitor.
[0047]
  Claim3According to the invention described in (2), the thickness of the insulating layer covering the third electrode corresponding to the intersecting portion of the first electrode and the third electrode intersects the second electrode and the third electrode. And a positive sustain pulse signal and a negative sustain pulse for one of the first and second electrodes, in addition to the thickness of the insulating layer covering the third electrode corresponding to the portion. Signals are supplied alternately.
[0059]
【Example】
  A preferred embodiment of the apparatus of the present invention will be described with reference to the drawings.
  (I) First embodiment
FirstOne embodiment is the first sourceReason ((See FIG. 1).
[0060]
FIG. 4 shows the plasma panel driving apparatus of the first embodiment. (A) is a layout diagram of drive circuits in the entire display device, and (B) is a block diagram thereof.
As shown in FIG. 4A, the driving circuit 200 of this embodiment is roughly divided into an address side driving circuit 9, an X side driving circuit 7a, and a Y side driving circuit 8. The drive timing of each drive circuit is controlled by the control circuit 10. In this embodiment, a strong ground pattern is provided. In the sustain period, a large current can be passed between the power source, the drive system, and both electrodes through this strong ground pattern.
[0061]
As shown in FIG. 4B, the address side drive circuit 9 includes an address power supply 17 that supplies a potential Va for selecting an address, an address driver 16 that supplies an address signal to an address electrode of the plasma panel P, And a VaX circuit 18 that generates the potential VaX of the X electrode in the address period.
[0062]
The X-side drive circuit 7a is a power supply V that outputs a predetermined voltage._OAnd the power supply V_OAnd an X-side sustainer 11 that generates and outputs an X-side sustain pulse (sustain pulse) signal for driving the X electrode of the plasma panel P based on the power supply voltage.
[0063]
The Y side drive circuit 8 is a non-selected power source (−V) applied when the address period is not selected._SC), A selection potential power supply 14 for supplying a selection potential (−VY) applied at the time of selection, a switch 15 for grounding the Y electrode in the sustain period, and a selection signal (in the address period). And a scan driver 12 for supplying a scan pulse signal) to the panel P.
FIG. 5 shows a detailed configuration of the X-side drive circuit 7a in the first embodiment. This circuit corresponds to the X-side driving means 1a of the first principle diagram (see FIG. 1) of the present invention.
[0064]
The X-side drive circuit 7a of the present embodiment is configured by a transistor (such as a MOS-FET) that operates as a switching element. The transistor T12 corresponds to the VaX circuit 18 of FIG. 4 and supplies a potential Va to be applied to the X electrode in the address period. The transistors T10 and T11 temporarily return the sustain pulse signal supplied to the X electrode to the ground potential during the sustain period. The diodes D1 to D3 prevent reverse current flow. The transistor T8 corresponds to the upper switch 3 in FIG. 1 and is conductive during a sustain period while a positive potential (+ Vs) is supplied to the X electrode. The transistor T9 corresponds to the lower switch 4 in FIG. 1 and is conductive during a sustain period while a negative potential (−Vs) is supplied to the X electrode. The gate of each transistor is supplied from the control circuit 10 (see FIG. 4A). The power supply circuit VO supplies + Vs as a positive potential and −Vs as a negative potential to the X-side sustainer 11 around the ground potential.
[0065]
FIG. 6A shows a detailed configuration of the Y-side drive circuit 8. This circuit corresponds to the Y-side driving means 2 in the first principle diagram (FIG. 1) of the present invention.
The scan driver 12 includes a push-pull circuit by transistors T1 and T2. The number of scanning lines of the plasma panel P (N) is provided for each line. The transistor T3 corresponds to the non-selection potential power supply 13 (FIG. 4B). The transistor T4 corresponds to the selection potential power supply 14 (FIG. 4B). The transistor T5 corresponds to the switch 15. The diode D5 is provided to be reverse-biased with respect to the ground potential, and prevents current from flowing into the non-selection potential power supply when the Y electrode is grounded to 0V. With this configuration, the non-selection potential (−V) is applied to the high potential side input terminal of the scan driver 20 in the address period._SC), A selection potential (−VY) is applied to the low potential side input terminal. When the Y electrode of a predetermined scanning line is selected, the transistor T2 is turned on, and when not selected, the transistor T1 is turned on. In the sustain period, when the transistor T5 is opened, a current is supplied from the ground potential to the Y electrode via a diode connected in parallel to the transistor T2 in the scan driver 20. In addition, a current can be supplied to the ground potential through a diode connected in parallel to the transistor T1. That is, since all the current flowing through the Y electrode flows to the ground potential and flows from the ground potential, if the forward voltage drop of the diode is ignored, it can be said that the Y electrode is in the ground state during the sustain period.
[0066]
FIG. 6B shows a detailed configuration of the address drive circuit 9.
The power source required for the address drive circuit 9 is a power source that supplies a potential of + Va with respect to the ground potential.
[0067]
The address driver 16 includes a push-pull circuit including transistors T6 and T7. The address drivers 16 are provided by the number of address electrodes (M). In the address period, the transistor T6 is turned on, and the address potential is applied to the address electrode of the panel P. In a period other than the address period, the transistor T7 is turned on and the address electrode is grounded.
[0068]
Next, the operation of the first embodiment will be described with reference to the drive waveform diagram of FIG.
A narrow erase pulse is used in the reset period in the subfield in this embodiment. In the reset period, the cells that have been lit (discharged) in the previous subfield are erased and discharged by the narrow erase pulse (time t₀). Address period (time t₁~ T₂), A scan pulse signal of −VY is selectively applied to the Y electrode as in the conventional example, and address discharge is performed. At this time, since the potential of the X electrode is Va, the process immediately shifts to the discharge between the X electrode and the Y electrode, accumulates wall charges necessary for performing the sustain discharge, and ends the discharge. In this way, address selection is sequentially performed.
[0069]
Next maintenance period (time t_Three~ T_Four), Sustain pulses having different polarities are alternately applied to all X electrodes of the panel in a step, and a sustain discharge is executed. At this time, the potential of the Y electrode is fixed at 0V.
[0070]
Here, the relationship between the voltage characteristics of the pulse and the applied voltage will be described.
The absolute value Vs of the sustain pulse signal applied during the sustain discharge is the maximum value among the minimum sustain voltages of the n cells between the X electrode and the Y electrode (Vsmn: n is intended for n cells). (Shows the case) and is less than the minimum discharge start voltage (Vf1). Further, Vs is a minimum discharge start voltage (Vf between the address electrode and the X electrode)._AX1: 1 is a value that does not exceed the Y electrode number). The voltage value is limited so as not to start the discharge between the address discharge and the X electrode.
[0071]
The potential difference (Va + VY) between the address pulse voltage (Va) and the scan pulse (−VY) is the maximum discharge start voltage (Vf) between the address electrode and the Y electrode._AYn: n indicates a value exceeding n cells). Further, Va + Vsc and VY are the minimum discharge start voltage (Vf) between the address electrode and the Y electrode so that the discharge is not started in a state where only the scan pulse or only the address pulse is applied (half-selected)._AYIt is necessary not to exceed 1).
[0072]
Specific examples of applied voltages include voltage values of Vs = 170V, Va = 50V, −VY = −150V, and −Vsc = −50V. The voltage indicating the panel characteristics is Vsmn = 150V, Vf1 = 220V, Vf_AY1 = Vf_AY1 = 180V, Vf_AYn = 190V.
[0073]
As described above, according to the first embodiment, the drive circuit of the present invention is configured only by combining a MOS transistor and a diode, which is preferable when the circuit is configured by an integrated circuit.
(II) Second embodiment
The second embodiment of the present inventionThe secondRegarding the principle of 2The present invention(See FIG. 2).
[0074]
Since the configuration of the second embodiment is the same as that of the first embodiment (FIGS. 4 and 6) except for the configuration of the X-side drive circuit, the description thereof is omitted.
FIG. 8 shows the configuration of the X-side drive circuit 7b of the second embodiment.
[0075]
Power supply V_OUnlike the first embodiment, ′ supplies one potential Vs. The capacitor C is inserted to prevent noise. The transistors T10 'and T11' are configured to determine an absolute potential with respect to the ground potential of the power supply, and correspond to the power supply potential fixing means 5a in the second principle diagram shown in FIG. The transistors T8 and T9 are configured to supply a sustain voltage to the X electrode of the panel P, and correspond to the X-side drive unit 1b in the second principle diagram shown in FIG. The transistor T12 is a VaX circuit 18 that applies the potential of the X electrode during the address period.
[0076]
In the above configuration, when a sustain pulse signal having a positive potential is applied in the sustain period, the transistor T11 'is turned on when a control signal is applied to the gate from the control circuit 10, and the power supply V_OThe low potential side terminal (minus terminal) of ′ is grounded. Next, the transistor T8 is turned on, and a positive sustain pulse signal having an amplitude of + Vs with respect to the ground potential is applied to the X electrode of the panel P.
[0077]
Further, when applying the sustain pulse signal having a negative potential, the transistor T10 'is turned on by the control signal, and the power supply V_OThe high potential side terminal (plus terminal) of ′ is grounded. Next, the transistor Q9 is turned on, and a sustain pulse signal having a negative potential having an amplitude of −Vs with respect to the ground potential is applied to the X electrode.
[0078]
As long as the sustain period continues, each time the sustain pulse signal is applied, the transistors T10 'and T11' are alternately turned on and off, and the power supply V_OThe operation of grounding either the positive potential side terminal or the negative potential side terminal of 'is repeated. Therefore, the X electrode is substantially equivalent to a voltage supplied from the + Vs power source and the −Vs power source.
[0079]
The signal supplied to the panel P by the above operation is the same as the drive waveform described with reference to FIG. 7 in the first embodiment.
As described above, according to the second embodiment, positive and negative sustain pulse signals can be generated from a single power source, which is economical. Further, the circuit of this embodiment is also suitable for being constituted by an integrated circuit.
(III) Third embodiment
The third embodiment of the present inventionThe second3 principlesThe present invention ((See FIG. 3).
[0080]
Since the configuration of the third embodiment is the same as that of the first embodiment (FIGS. 4 and 6) except for the configuration of the X-side drive circuit, the description thereof is omitted.
FIG. 9 shows the configuration of the X-side drive circuit 7c of the third embodiment.
[0081]
Book number3The characteristic of the embodiment is that instead of grounding the power source of ± Vs as in the second embodiment every time the sustain pulse signal is supplied, charges are accumulated in the capacitors C1 and C2, and an apparently + Vs power source and − The configuration is such that a power source of Vs exists. When the sustain pulse signals having different polarities are alternately supplied, the transistors T10 and T11 once ground the X potential at the change point of the polarities.
[0082]
In the above configuration, in the address period, the transistors T13 and T14 are turned on with a somewhat long period, and charges are accumulated in the capacitors C1 and C2. For example, in the first half of the address period, the transistor T13 is turned on to charge the capacitor C2 with the voltage Vs. At this time, the diode D11 prevents current leakage from the capacitor C2. Therefore, the cathode of the diode D11 maintains the potential of + Vs.
[0083]
On the other hand, in the second half of the address period, the transistor T14 is turned on to charge the capacitor C1 with the voltage Vs. At this time, the diode D12 prevents current leakage from the capacitor C2. Therefore, the anode of the diode D12 maintains the potential of −Vs.
[0084]
As described above, the transistors T13 and T14 are charged by dividing the address period into the first half and the second half, or the sustain period may be performed in a cycle that is one to several times the cycle of the sustain pulse signal. Good. Further, it is desirable that the capacitors C1 and C2 have sufficient charge storage capability with respect to the amount of charge consumed by one sustain pulse signal. The higher the charge storage capability, the shorter the charging time for the capacitors C1 and C2 by turning on and off the transistors 13 and 14 in the sustain period.
[0085]
As described above, according to the third embodiment, since the capacitor accumulates the charge necessary for the sustain period, it is not necessary to switch the terminal of the power source every time the polarity of the sustain pulse is inverted. In addition, the switching timing of the transistor for charging the capacitor is simple and does not require strict time management.
(IV) Fourth embodiment
Fourth embodiment of the present inventionIsThe present invention relates to a structure of a plasma panel suitable for use in each of the above embodiments.
[0086]
In the plasma panel 300 of the fourth embodiment, as shown in FIG. 10, a dielectric layer (IF layer) 23 is provided on the address electrode 21 close to the X electrode 30 to be thicker than the Y electrode side. With this structure, the discharge start voltage between the X electrode and the address electrode is higher than in the prior art.
[0087]
For example, if the thick dielectric layer 23 on the X electrode 30 is made about 10 microns thicker than the upper part of the Y electrode, the minimum discharge start voltage (VfAX1) between the address electrode 21 and the Y electrode 31 is about 200 [V]. . This is a voltage about 20 [V] higher than the conventional voltage.
[0088]
Therefore, the sustain voltage Vs can be applied up to nearly 200 [V].
(V) Fifth embodiment
Fifth embodiment of the present inventionIsSimilar to the fourth embodiment, the present invention relates to a structure of a plasma panel suitable for use in the first to third embodiments.
[0089]
In the plasma panel 301 of the fifth embodiment, as shown in FIG. 11, the width of the address electrode 35 close to the X electrode 33 is made narrower than the Y electrode 34 side. For this reason, the discharge start voltage between the X electrode 33 and the address electrode 35 becomes higher than before.
[0090]
For example, when the address electrode 35 in the X electrode portion is made thinner by about 30 microns than the Y electrode 34 portion, the minimum discharge start voltage (Vf) between the address electrode 35 and the X electrode 33 is obtained._AX1) can be increased to 190 [V], which is about 10 [V] higher than the conventional one. Therefore, the sustain voltage Vs can be applied up to about 190 [V].
[0091]
【The invention's effect】
  Claim 1as well asClaim2According to the invention described in (1), since the signal supply wiring pattern can be omitted, malfunctions caused by long-distance wiring are less likely to occur. Further, the wiring area is reduced by omitting the wiring pattern.
[0092]
  In particular, the claims1According to the invention described in (1), since a positive and negative sustain pulse signal can be generated with a single power supply, the power supply configuration can be simplified.
  And claims2According to the invention described in (2), in addition to the above effect, it is not necessary to link the operation of grounding the power input terminal and the operation of supplying the sustain pulse signal, and time management may be performed only for the operation of supplying the sustain pulse signal. Therefore, processing can be simplified.
[0093]
  Claim3According to the invention described in claim 1, since the margin until the start of discharge is wide,3A plasma panel suitable for the invention described in 1) can be provided.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a first principle of the present invention.
FIG. 2 is an explanatory diagram showing a second principle of the present invention.
FIG. 3 is an explanatory diagram showing a third principle of the present invention.
FIG. 4 is a configuration diagram of the plasma panel driving apparatus of the first embodiment.
FIG. 5 is a configuration diagram of an X-side drive circuit according to the first embodiment.
FIG. 6 is a configuration diagram of a Y-side drive circuit and an address drive circuit.
FIG. 7 is a drive waveform diagram of the example.
FIG. 8 is a configuration diagram of an X-side drive circuit according to a second embodiment.
FIG. 9 is a configuration diagram of an X-side drive circuit according to a third embodiment.
FIG. 10 is a sectional view of a plasma panel according to a fourth embodiment.
FIG. 11 is a plan view of a plasma panel according to a fifth embodiment.
FIG. 12 is a plan view of a three-electrode / surface discharge / AC type plasma panel.
FIG. 13 is a cross-sectional view of a three-electrode, surface discharge, AC type plasma panel.
FIG. 14 is a configuration diagram of a peripheral circuit of a plasma circuit.
FIG. 15 is a conventional driving waveform diagram.
FIG. 16 is an address / sustain discharge type time chart;
FIG. 17 is an explanatory diagram of a problem in a conventional example.
[Explanation of symbols]
1a, 1b, 1c, 7a, 7b, 7c ... X side drive circuit (means)
2 ... Y side drive circuit (means)
3 ... Upper switch
4 ... Lower switch
5a, 5b ... Power supply potential fixing means
8 ... Y side drive circuit
9 ... Address drive circuit
10 ... Control circuit
11 ... X side sustainer
12 ... Scan driver
13 ... Non-selection potential power supply
14 ... Selection potential power supply
15 ... Switch
16 ... Address driver
17 ... Address power supply
18 ... VaX circuit

Claims (3)

A plasma panel drive device comprising at least a pair of electrodes arranged in parallel to perform a sustain discharge and an address electrode arranged to cross the pair of electrodes to supply display data. And
A first signal line that supplies a positive sustain pulse signal having a positive polarity with respect to a reference potential to one of the pair of electrodes, and a negative sustain having a negative amplitude with respect to the reference potential A second signal line for supplying a pulse signal to one of the pair of electrodes,
When supplying the positive sustain pulse signal, the second signal line is grounded, and the positive sustain pulse signal is supplied to one of the pair of electrodes from the first signal line,
When supplying the negative sustain pulse signal, the first signal line is grounded, and the negative sustain pulse signal is supplied from one of the second signal lines to one of the pair of electrodes. A plasma panel drive device. At least a pair of electrodes arranged in parallel with each other to perform a sustain discharge, an address electrode arranged to cross the pair of electrodes to supply display data, and an on state of a display cell corresponding to the display data An address period for performing the off-off operation, and a sustain discharge period for performing image display by performing a sustain discharge between the pair of electrodes. In the sustain discharge period, a reference is made with respect to one of the pair of electrodes. A plasma panel driving device that controls a positive sustain pulse signal having a positive polarity with respect to a potential and a negative sustain pulse signal having a negative amplitude to be supplied alternately,
A first signal line for supplying the positive sustain pulse signal to one of the pair of electrodes; a second signal line for supplying the negative sustain pulse signal to one of the pair of electrodes; A capacitor provided between the first and second signal lines,
When accumulating electric charge in the capacitor from the first signal line side and supplying the positive sustain pulse signal in the sustain discharge period, the second signal line is grounded prior to the supply, In addition, when charge is accumulated in the capacitor from the second signal line side and the negative sustain pulse signal is supplied during the sustain discharge period, the first signal line is grounded prior to the supply. And
With the charge accumulated in the capacitor, the positive sustain pulse signal or the negative sustain pulse signal, the drive characteristics and to pulp Razumapaneru to be supplied to one of the pair of electrodes. A first substrate in which first and second electrodes for performing a sustain discharge are arranged in parallel to each other, and a third electrode that is placed opposite to the first substrate and selects a discharge cell are the first electrode and A second substrate disposed perpendicular to the second electrode, and a plasma panel comprising:
The thickness of the insulating layer covering the third electrode corresponding to the intersecting portion of the first electrode and the third electrode corresponds to the intersecting portion of the second electrode and the third electrode. Thicker than the insulating layer covering the third electrode,
A positive sustain pulse signal having a positive polarity with respect to a reference potential and a negative sustain pulse signal having a negative amplitude with respect to the reference potential with respect to one of the first and second electrodes. A plasma panel characterized by being supplied alternately.

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