JP3655088B2 - Wavelet transform device and encoding / decoding device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to the field of data compression and decompression, and more particularly to an encoding / decoding device and a wavelet transformation device that use wavelet transformation.
[0002]
[Prior art]
Data compression is a very useful tool for storing and transmitting large amounts of data. For example, the time required for facsimile transmission of a document and transmission of an image such as the World Wide Web can be drastically shortened by reducing the number of bits required for image reproduction using compression.
[0003]
Conventionally, various data compression methods exist. A compression method of JPEG (Joint Photographics Experts Group) is the most widely used compression method. In the JPEG compression method, input symbols or luminance data are quantized and then converted into output codewords. The purpose of quantization is to remove unimportant feature quantities while preserving important feature quantities of data. Prior to quantization, transformation is used to concentrate energy, but JPEG employs DCT (Discrete Cosine Transform). However, various drawbacks have been pointed out with respect to the JPEG method using DCT. For example, block noise and mosquito noise (called this because mosquitoes appear to fly). In image signal processing, there is an interest in pursuing an efficient and highly accurate data compression encoding method that eliminates these drawbacks. Among these methods, there is a wavelet pyramid processing method.
[0004]
When wavelet transform is applied to a two-dimensional signal such as an image signal, a horizontal low-pass filter HL (Horizontal Low) and a horizontal high-pass filter HH (Holizontal High) are used for the input signal. Are separated into a horizontal low-frequency signal (S (smooth) coefficient) and a horizontal high-frequency signal (D (detail) coefficient), and further, a vertical low-pass filter VL (Vertical) with respect to the S coefficient and D coefficient. Low) and vertical high-pass filter VH (Vertical High), horizontal low-vertical low-frequency signal (SS coefficient), horizontal low-vertical high-frequency signal (SD coefficient), horizontal The direction high band-vertical low band signal (DS coefficient) and the horizontal high band-vertical high band signal (DD coefficient) are separated. The series of processes described above is called a level, and an output obtained by performing one horizontal process and vertical process is called a level 1 output. Furthermore, the above four types of signals are called frequency band signals. This process is recursively performed on the SS coefficient when an output of level 2 or higher is desired. In the level 2 output, seven frequency band signals of SS coefficient, 1SD coefficient and 2SD coefficient, 1DS coefficient and 2DS coefficient, 1DD coefficient and 2DD coefficient are obtained. In the above description, the filter is first applied in the horizontal direction and then the filter is applied in the vertical direction, but the order may be reversed.
[0005]
FIG. 28 shows a conventional configuration when processing up to level 4 is performed. In the figure, 1000 is a wavelet transform unit, and 1100 is an encoding unit. The encoding unit 1100 has a function of encoding the output data of the wavelet transform unit 1000 and outputting a compressed code, or decoding a similarly compressed code input from the outside and expanding it to a frequency band signal of each level. Have.
[0006]
In FIG. 28, reference numerals 1001 to 1012 denote filters, and filters 1001, 1004, 1007, and 1010 (hereinafter referred to as filter1H, filter2H, filter3H, and filter4H) are horizontal low-pass filters HL. And a horizontal filter including a horizontal high-pass filter HH. Numbers 1 to 4 in these filter names represent level numbers, and H means a horizontal filter. Similarly, the filters 1002 (filter1V1) and 1003 (filter1V2), the same 1005 (filter2V1) and the same 1006 (filter2V2), the same 1008 (filter3V1), the same 1009 (filter3V2), and the same 1011
(Filter4V1) and 1012 (filter4V2) are vertical filters including a vertical low-pass filter VL and a vertical high-pass filter VH. V in these filter names means a vertical filter, numbers 1 to 4 before V represent level numbers, and number 1 after V inputs a horizontal low-frequency signal (S coefficient). The numeral 2 after V indicates that the filter receives a horizontal high-frequency signal (D coefficient). The above filter may have any configuration, but in the following description, the horizontal low-pass filter HL and the vertical low-pass filter VL are 2-tap that performs calculations using two sets of data. This filter shall be used. Further, as the horizontal high-pass filter HH and the vertical high-pass filter VH, among the S coefficients that are the outputs of the low-pass filter HL or VL, the current position, one before and one after. It is assumed that a 6-tap filter that calculates using a total of three sets of data is used.
[0007]
An example of calculation when such a filter is used is shown in FIG. However, it should be noted that the data mapping in this figure is for explaining the calculation method, and the actual mapping to the memory is as shown in FIGS. 32 to 35, for example. (A) of FIG. 30 explains the process of the horizontal filter, [00] means the 0th pixel data of the 0th line, and [12] means the 2nd pixel data of the 1st line. (In this way, both lines and pixels are counted from 0). The output [S00] of the 0th pixel of the horizontal low-pass filter HL is obtained from [00] data and [01] data, and the output [S01] of the first pixel is [02] data and [03]. It is obtained from the data. On the other hand, the output [D00] of the 0th pixel of the horizontal high-pass filter HH includes data (not existing) two and one before (00) data, [00] data, [ 01] data, [02] data, and [03] data. Here, in order to obtain data that is two and one before the [00] data that does not exist, a process called a mirror is performed. Specifically, a process of turning back the data in a mirror image relationship is performed. As a result, the previous data and the previous data become [01] data and [00] data. In this way, [D00] is calculated from the data of 6 pixels.
[0008]
FIG. 30B illustrates the vertical filter processing. This process is performed in the vertical direction using the S coefficient and the D coefficient by the vertical filter process. The non-existent coefficient is subjected to mirror processing as in the case of the horizontal filter processing.
[0009]
FIG. 31 to FIG. 35 illustrate a method for storing the results of the wavelet processing. FIG. 31 shows image data stored in the frame memory in raster order. Data is read from the frame memory, horizontal processing is performed, and the result is written to the frame memory again. In order to avoid overwriting unprocessed data at the time of writing, for example, the S coefficient and the D coefficient are written by mapping as shown in FIG. In FIG. 32, [1S00] means the S coefficient of address 00 of level 1. FIG. 33 shows an example of mapping when writing each coefficient after performing vertical processing. This is the method of storing each level 1 coefficient. FIG. 34 shows an example of a method for storing level 2 horizontal coefficients. Note that the shaded portion of data is not used because level 2 processing is only performed on 1SS coefficients. Next, each level 2 coefficient is stored by mapping as shown in FIG. 35, and the level 2 processing is completed. The above processing is repeated up to level 4.
[0010]
FIG. 29 is a timing chart of the wavelet transform unit 1000 configured as shown in FIG. However, it should be noted that this timing chart is used for explaining the processing procedure, the time required for memory access or the like is not considered, and the horizontal axis (time axis) scale is not linear. In the following description, the number of pixels or the number of lines is counted from 0, such as 0th pixel or 0th line. Image data (raster data) input from data is 32 pixels × 32 lines (0 to 31), and one data segment (× = ×) corresponds to one line.
[0011]
From time t0, the 0th line data is sequentially input from the 0th pixel, and when the 1st pixel is input, the [1S00] data of the 0th pixel is output from the filter 1H. Next, when [1S01] data is output, three sets of S coefficients ([1S00], [1S00], [1S01]) necessary for calculating the D coefficient are prepared (the previous data is obtained by mirror processing). D coefficient [1D00] is output. This is repeated for one line. In the timing chart, it is shown in units of time of one line, but it should be noted that if it is enlarged, a deviation in units of pixels occurs.
[0012]
Input of data on the first line starts from time t1, and [1S10], [1D10], and S and D coefficients are sequentially output from filter 1H. 2H processing (level 2 horizontal processing) starts. When [1S10] is output, 1V processing (level 1 vertical processing) starts, and [1SS00] is output from filter1V1, and [1DS00] is output from filter1V2. When [1S11] is output, three sets of data necessary for calculating the D coefficient are prepared in filter1V1 and filter1V2. That is, [1S10], [1S10], [1S11] in filter1V1, and [1D10], [1D10], [1D11] are aligned in filter1V2 (the previous data is obtained by mirror processing), and level 1 Output data [1SS00], [1SD00], [1DS00], and [1DD00] are obtained. This is repeated for one line.
[0013]
At time t2, input of the first line for 2V processing (level 2 vertical processing) begins, and 2V processing begins. Thereafter, the processing is repeated until time t9 with the same timing relationship, and each frequency band signal up to level 4 is output.
[0014]
The frequency band signals of the respective levels obtained as described above are encoded and compressed by the encoding unit 1100. However, since the encoding is usually bit processing, the frequency band signals are temporarily stored in the storage. It is necessary to write it down. A commonly used storage is a semiconductor memory. The encoding unit 1100 performs bit processing with reference to each frequency band signal written in the storage and encodes the generated code.
Output as code. The decompression from the compressed code to the image data is performed in the reverse order of the operations described above.
[0015]
More detailed information about the encoding / decoding device, wavelet transform unit, or filter related to the present invention can be found in JP-A-8-116265, JP-A-8-139935, and JP-A-9-27752. Refer to Japanese Patent Laid-Open No. 9-27912 and the like. For similar prior art, refer to JP-A-3-27687, JP-A-5-167997, and JP-A-5-183386.
[0016]
Next, the processing time for wavelet transform will be described. Here, as a storage for each frequency band signal generated by the wavelet transform unit 1000, a general semiconductor memory that can only be read or written at a time is used. This will be described as a case.
[0017]
As described with reference to the timing chart of FIG. 29, since each frequency band signal is output in parallel at the same time, writing to the memory must also be performed in parallel. Only one data can be read or written. 29, the lower left range corresponds to 1H, 1V,. . . , 4V represents the range of processing time occupied by ← →. The r / w cycles under range is the number of memory accesses required for each range (← →) of the range, and is the sum of the number of writes and the number of reads within that range, but different levels are processed simultaneously. The number of times in the range is shown as the total number of times for each level. The numerical value shown on the right side of FIG. 29 is the number of memory accesses (total number of writing and reading) required for horizontal processing or vertical processing at each level. As for the number of memory accesses, at each level, all horizontal data and vertical data are always read once, and all data is rewritten with filter output data, so writing twice the total number of pixels. / Write count is required.
[0018]
[Problems to be solved by the invention]
As described above, encoding is performed using each frequency band signal of each level, but since encoding is normally performed bit processing, it is necessary to temporarily store the output data after wavelet transform in the storage, There is a problem that the processing time is several times longer than the time required to simply input data. As is apparent from the above description, for example, when the size of the input image data is 32 pixels × 32 lines and the number of levels is 4, the number of cycles required to input the image data is 1024 = 32 × 32. On the other hand, the required processing time is 5440 cycles, which is five times or more. Obviously, if the size of the input data increases, the processing time will increase significantly. For example, in the case of 64 pixels × 64 lines, as shown by the dotted line in FIG. 29, as a result of the 1H processing being performed until time t10, the number of sections output in parallel increases, so the processing time increases significantly. Similarly, when the number of levels increases, the processing time increases significantly.
[0019]
Moreover, since each frequency band signal of each level is output at the same time, pipeline processing is necessary. That is, since the data input timings of all filters are different, it is necessary to individually design each filter by incorporating a controller according to the place where the filter is used. In addition, these controllers can deal with only a combination of the number of pixels and the level of one condition, and there is a problem that it is difficult to deal with when one or both of the number of pixels or the level is changed. . Furthermore, the sequence of encoding processing (processing to convert image data into each frequency band signal, wavelet order conversion) and decoding processing (processing to convert each frequency band signal into image data, wavelet inverse conversion) are different, but this Careful design was necessary so that the entire pipeline operation would not fail in consideration of the difference.
[0020]
An object of the present invention is to improve the above-mentioned problems in a wavelet transform apparatus and an encoding / decoding apparatus using the wavelet transform, and more specifically, enabling higher-speed operation. Pipeline processing is unnecessary, design or design change is facilitated, an increase in circuit scale is avoided, and so on.
[0021]
[Means for Solving the Problems]
In order to achieve the above object, a wavelet transform apparatus according to the invention of claim 1 includes a plurality of independent memories associated with each level of the wavelet transform, and a filter common to all levels of the wavelet transform. And a control unit that controls data transfer inside the device, data transfer outside the device, and operations of the plurality of memories. According to the second aspect of the present invention, each of the plurality of memories associated with each level on a one-to-one basis has a read address and a write address that are independent and can be read and written at the same time.
[0022]
In order to achieve the above object, the invention according to claim 3 is the wavelet transform device according to claim 1 or 2, wherein the control unit is provided for at least the plurality of memories. Address and enable signal A part for selectively supplying the control signal, a part for controlling the data transfer inside the apparatus and the data transfer with the outside of the apparatus, and a part for controlling these two parts and for transmitting / receiving control information to / from the outside of the apparatus; It is characterized by dividing into two. According to the invention of claim 4, at least three parts constituting the control unit are divided into a part dedicated for encoding and a part dedicated for decoding.
[0023]
In order to achieve the above object, a wavelet transform apparatus according to the invention of claim 5 includes a plurality of mutually independent memories associated with each level of the wavelet transform one by one, and a maximum memory among the plurality of memories. A buffer memory common to all levels of the wavelet transform having at least the same number of words, a filter unit common to all levels of the wavelet transform, data transfer inside the apparatus, data transfer outside the apparatus, and the plurality of memories And a control unit for controlling the operation of the buffer memory. According to the invention of claim 6, the filter unit according to claim 5 is composed of two independent filter units, and one of the two filter units is assigned to horizontal processing and the other is assigned to vertical processing.
[0024]
In order to achieve the above object, a wavelet transform device according to the invention of claim 7 includes a plurality of independent memories that are associated with each level of the wavelet transform in a one-to-one manner, and a line that is common to all levels of the wavelet transform. A configuration including a memory, a filter unit common to all levels of wavelet transform, a data transfer inside the device, a data transfer outside the device, and a control unit that controls operations of the plurality of memories and the line memory It is said. According to an eighth aspect of the present invention, a horizontal processing filter unit and a vertical processing filter unit are provided as the filter unit according to the seventh aspect.
[0025]
In order to achieve the above object, according to a ninth aspect of the present invention, in the wavelet transform device according to the first or second aspect, each of the plurality of memories is an independent memory having a number equal to the number of types of wavelet transform coefficients, and the filter unit. It comprises two independent filter units used for both horizontal processing and vertical processing.
[0026]
In order to achieve the above object, according to a tenth aspect of the present invention, there is provided the wavelet transform device according to the fifth aspect, wherein each of the memories and the buffer memory has the same number of independent memories as the number of types of wavelet transform coefficients. In addition, the filter unit includes two independent filter units used for both horizontal processing and vertical processing.
[0027]
In order to achieve the above object, the invention of claim 11 is the wavelet transform device according to claim 1 or 2, wherein each of the plurality of memories has a bit depth equal to a sum of all kinds of bit depths of wavelet transform coefficients. It is characterized by having at least a memory.
[0028]
In order to achieve the above object, according to a twelfth aspect of the present invention, in the wavelet transform device according to the fifth aspect, each memory of the plurality of memories and the buffer memory are summed up to the bit depth of all kinds of wavelet transform coefficients. The memory is characterized by having an equal bit depth.
[0032]
In order to achieve the above purpose, Claim 13 An encoding / decoding device according to the invention of claim 1 is provided. 12 The wavelet transform device according to claim 1 is connected to the wavelet transform device, the output data of the wavelet transform device is encoded, or the encoded data input from the outside is decoded and input to the wavelet transform device It is set as the structure which comprises the encoding part which performs.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in order to avoid complication of description, the same or similar reference numerals are used for corresponding parts in a plurality of drawings. Moreover, about the same or similar structure in several Example, it abbreviate | omits or simplifies suitably from related drawing, or uses drawing of another Example.
[0034]
<First embodiment>
FIG. 1 is a block diagram of an encoding / decoding apparatus according to a first embodiment of the present invention. This encoding / decoding device includes a wavelet transform unit 100 and an encoding unit 200. The wavelet transform unit 100 can process up to level 4. Of course, any number of levels may be set, and the present invention exhibits its effect as the number of levels increases. Furthermore, the present invention exhibits its effect as the number of input data (number of pixels) increases.
[0035]
The wavelet transform unit 100 includes memories 102_1 to 102_4 (hereinafter referred to as mem1, mem2, mem3, and mem4) for storing level 1, 2, 3, and 4 frequency band signal data, and a control signal selection unit (s_mux). ) 111, a data selection unit (d_mux) 114, and a control unit (cnotroller) 110 including a main control unit (main) 118 that controls them, and a filter unit including a low-pass filter and a high-pass filter (filter) 130).
[0036]
The wavelet transform unit 100 has input / output of frequency band signal data between the input / output data of image data with the outside and the encoding unit 200. At the time of encoding, image data equal to or less than the maximum number (number of pixels) that can be processed at a time is input to the wavelet transform unit 100 from the input / output data. The maximum number of data is equal to the word number W1 of mem1. The word number W2 of mem2 is set to W2 = W1 × (1/4). The word number W3 of mem3 is set to W3 = W2 × (1/4), and the word number W4 of mem4 is set to W4 = W3 × (1/4). Therefore, the total number of words in the memories mem1 to mem4 is relative to the total number of input data.
1+ (1/4) + (1/4) ^ 2 + (1/4) ^ 3 = 1 + 21/64
That is an increase of about 33%.
[0037]
The main control unit 118 of the control unit 110 is a part that exchanges control signals with the outside and controls the control signal selection unit 111 and the data selection unit 114. The control signal selection unit 111 controls access to the memories mem1 to mem4. It is a part to do. The data selection unit 114 is a part that performs control of internal data transfer of the wavelet transform unit 100, control of transfer of image data to / from the outside, and control of transfer of frequency band signal data to / from the encoding unit 200. The main control unit 118 notifies the outside of the external input start for starting the wavelet transformation, the external input dir for selecting the operation of encoding (wavelet order transformation) or decoding (inverse wavelet transformation), and the end of the wavelet transformation. Output end, control signal output cnt1 for the control signal selector 111, and control signal output cnt2 for the data selector 114. Outputs mem_cnt1 to mem_cnt4 of the control signal selection unit 111 are control signals for the memory, and include an address and a series of enable signals. The data selection unit 114 has outputs mem_out1 to mem_out4 to the memory and inputs mem_in1 to mem_in4 from the memory, and further has an output fil_out to the filter unit 130 and an input fil_in from the filter unit 130.
[0038]
Hereinafter, the operation of this embodiment will be described with reference to the memory map shown in FIGS. 2 and 3 and the timing charts shown in FIGS.
[0039]
First, the encoding operation will be described. It is assumed that a start signal is input to the main control unit 118 of the control unit 110, and image data is input from data with a delay of about several pixel hours. FIG. 4 is a timing chart at the time of encoding. The encoding operation is notified by the dir signal.
[0040]
When the start signal is input at time t0 in FIG. 4, the register in the main control unit 118 is reset, and the control signal selection unit through cnt1 and cnt2 indicates that it is level 1 encoding processing and horizontal processing. 111 and the data selection unit 114 are notified. In response to these signals, the input image data is first input to the filter unit 130 through the fil_out by the data selection unit 114, and the S coefficient from the horizontal low-pass filter and the high-pass filter from the filter unit 130. The D coefficient from is output to the data selection unit 114 through fil_in. Data input to the data selection unit 114 is written to the memory mem1 through mem_out1. At this time, a write address and various enable signals are given to the memory mem1 from the control signal selector 111 through mem_cnt1. The timing of these controls is scheduled by the main control unit 118. These operations are performed in raster order until time t1, and the horizontal processing ends.
[0041]
When image data of 32 pixels × 32 lines is input, the total number of read / write cycles necessary for level 1 horizontal processing (1H) is 1024 cycles. For example, as shown in FIG. 2, the S and D coefficient data are written in the left half of the memory mem1 and in the right half, respectively.
[0042]
Subsequently, the main control unit 118 notifies the control signal selection unit 111 and the data selection unit 114 that the vertical processing is performed through cnt1 and cnt2. In response to these signals, the read address and various enable signals are output from the control signal selection unit 111 to the memory mem1 through mem_cnt1. However, it should be noted that the addressing performed at this time is not the raster direction (horizontal direction) but the line direction (vertical direction). First, the S coefficient obtained by the processing of 1H is output from the memory mem1 to mem_in1, and this is input to the filter unit 130 by the data selection unit 114 through fil_out. Then, the SS coefficient from the low-pass filter in the vertical direction and the SD coefficient from the high-pass filter are output from the filter unit 130 to the data selection unit 114 through fil_in. Next, the D coefficient that is the processing result of 1H is similarly output from the memory mem1 to mem_in1, and this is input from the data selection unit 114 to the filter unit 130 through fil_out. Then, the DS coefficient from the vertical low-pass filter and the DD coefficient from the high-pass filter are output from the filter unit 130 to the data selection unit 114 through fil_in. However, although the S coefficient is processed first and then the D coefficient is processed next, the order may be reversed. The SS, SD, DS, and DD coefficient data input from the filter unit 130 to the data selection unit 114 is written to the memory mem1 through mem_out1. At this time, the write address and various enable signals for the memory mem1 are given from the control signal selector 111 through mem_cnt1. The above operation is repeated until time t2, and the level 1 vertical processing (1V) is completed.
[0043]
When image data of 32 pixels × 32 lines is input, the total number of read / write cycles necessary for 1V processing is 2048 cycles because there are two types of input to the filter unit 130, S coefficient and D coefficient. .
[0044]
As a result of the 1V processing, for example, as shown in FIG. 3, the SS coefficient is in the upper left quadrant of the memory mem1, the SD coefficient is in the lower left quadrant, the DS coefficient is in the upper right quadrant, and the DD coefficient is in the lower right quadrant. Are written respectively.
[0045]
Next, level 2 processing is performed from time t2 to time t4. The data to be subjected to horizontal processing is the level 1 SS coefficient. Therefore, in level 2 horizontal processing (2H) from time t2 to time t3, the control signal selection unit 111 and the data selection unit 114 read the input data from the area in which the SS coefficient of the memory mem1 is stored, and filter The output data of the unit 130 is written into the memory mem2 for level 2, and the data can be read and written at the same time as in the case of the 1H processing. In level 2 vertical processing (2 V), data is read from and written to the memory mem2. Therefore, the total number of read / write cycles required for 2H processing and 2V processing is 256 cycles and 512 cycles, respectively.
[0046]
Subsequently, processing from time t4 to t6 is level 3 processing. In the horizontal processing (3H), reading of the SS coefficient of the memory mem2 and writing of data to the memory mem3 are simultaneously performed, and in the vertical processing (3V), the memory mem3 is read. Reading from and writing to are performed. Therefore, the total number of read / write cycles required for 3H processing and 3V processing is 64 cycles and 128 cycles, respectively. Subsequently, level 4 processing is performed from time t6 to t8, and the total number of read / write cycles required for the horizontal processing (4H) and vertical processing (4V) is 16 cycles and 32 cycles, respectively. Therefore, the total number of read / write cycles from level 1 to level 4 is 4080.
[0047]
Next, the operation during decoding will be described. FIG. 5 is a timing chart at the time of decoding. At the time of decoding, frequency band signal data is input from the encoding unit 200 to the wavelet transform unit 100. The wavelet transform unit 100 operates in the reverse order to that at the time of encoding and performs wavelet inverse transform, and the restored image data is externally output from data. Output to. The decoding operation is notified by the dir signal.
[0048]
In FIG. 5, when a start signal is input at time t0, level 4 vertical processing is started on the input level 4 coefficient data. The input coefficient is sent from the data selection unit 114 to the filter unit 130 through filter_out, and the output data from the filter unit 130 is input to the data selection unit 114 through filter_in, which is written to the memory mem4 under the control of the control signal selection unit 111. It is. This ends at time t1, and then level 4 horizontal processing is started. Data in the memory mem4 is read out, sent to the filter unit 130 via the data selection unit 114, and output from the filter unit 130. That is, the SS coefficient of level 3 is written into the corresponding area of the memory mem3 via the data selection unit 114. This vertical processing ends at time t2. From time t2, it is level 3 processing, vertical processing is performed on the inputted level 3 SD, DS, DD coefficients and SS coefficient read from the memory mem3, and the result is written in the corresponding area of the memory mem3. Level 3 vertical processing ends at time t3, and then level 3 horizontal processing is performed. As a result, level 2 SS coefficient data is written in a corresponding area of the memory mem2. Level 3 processing ends at time t4, level 2 vertical processing is performed, and level 2 horizontal processing is performed from time t5. Level 1 vertical processing is performed from time t6 to time t7, then level 1 horizontal processing is performed from time t8 to time t8, and the restored image data is output to the outside through data.
[0049]
At each level, the number of output pixels is double the number of input pixels in both the horizontal and vertical directions. Therefore, for example, the time from time t0 to t1 is four times the time from time t2 to t3 or the time from time t2 to t3 with respect to the time from time t1 to t2. Therefore, the number of cycles necessary for the decoding operation is 4080 cycles as in the encoding.
[0050]
Note that the memory maps shown in FIGS. 2 and 3 are merely examples shown to make it easy to grasp the processing image, and take any form in consideration of ease of addressing or design. Try to be free. This is because the memories mem1 to mem4 are independent in each level of computation, and are storages for finally storing frequency band signals, and also function as buffer memories for temporarily storing the results of horizontal processing. This is because.
[0051]
<Second embodiment>
FIG. 6 is a block diagram showing a second embodiment of the present invention. However, the encoding unit is omitted, and only the wavelet transform unit is shown.
[0052]
The configuration of this embodiment is suitable for an IC. That is, in the first embodiment, the case where the most general memory (one type of address, that is, one having a common read address and write address) is used as the memories mem1 to mem4. A memory such as a memory that is relatively frequently used in an IC, in which a read address and a write address are independent and can be read and written simultaneously, is used. Accordingly, the memories mem1 to mem4 have two types of address inputs ra (dedicated address input at the time of reading) and wa (dedicated address input at the time of writing), and two types of enable inputs reb (dedicated enable bar at the time of reading) and web (write). And a data input i and a data output o.
[0053]
The control signal selection unit (s_mux) 111 outputs signals of ra1 to ra4, wa1 to wa4, reb1 to reb4, and web1 to web4 to the memories mem1 to mem4. The signals ra, wa, reb, and web that are the basis of these signals are input from the main control unit (main) 118 to the control signal selection unit 111. Further, the control signal selection unit 111 receives the signals hb_s_mux (holizontal bar, s_mux) and level_s_mux (level, s_mux) from the main control unit in order to select the signal output according to the level. The encoding / decoding state is given from the outside by a dir (direction) signal. Similarly, the start signal is given from the outside.
[0054]
The data selection unit (d_mux) 114 receives the output signals o1 to o4 of the memories mem1 to mem4 and the output signals sin, din, xin1, and xin2 of the filter unit (filter) 130, and the input signals to the memories mem1 to mem4. Input signals so, do, xo1, and xo2 to i1 to i4 and the filter unit (filter) 130 are output.
[0055]
Hereinafter, the operation at the time of encoding of this embodiment will be described based on the timing chart of FIG. The time scale is defined such that all image data (here, 32 pixels × 32 lines, total 1024 pixels) is input from data between times t0 and t1, for example. Some of the signals in the figure change in units of pixels, but since they cannot be drawn in units of pixels, they are simplified as follows. That is, X is a don't care signal, x = x is a signal having a bit depth, and a web or start signal is a signal with a cadence such as ￣ | _ | ￣ (other than x = x), A signal in which two high / low signals are drawn at the same time is a 1-bit signal.
[0056]
A start signal is input at time t0, and image data is input from data in synchronization therewith. The main control unit (main) 118 outputs wa, web, hb_mux, level_s_mux, hb_d_mux, and level_d_mux signals. The control signal selection unit (s_mux) 111 and the data selection unit (d_mux) 114 select input / output signals for the memory to be accessed based on the level_s_mux, hb_d_mux, and level_d_mux signals. In FIG. 36, level_s_mux, level_d_mux, hb_d_mux, and hb_d_mux are depicted as the same signal, but it should be noted that there may be a time lag in units of pixels. From time t0 to t1, level 1 horizontal processing is performed on the input image data, and the result is written in the memory mem1. The selection of the memory to be accessed is notified when the signals level_s_mux and level_d_mux are 1, and the horizontal processing is notified when the signals hb_d_mux and hb_d_mux are at the low level. From time t1 to t2, level 1 vertical processing is performed on the S coefficient and D coefficient stored in the memory mem1, and the result is written in the memory mem1. The selection of the memory to be accessed is notified when the signals level_s_mux and level_d_mux are 1, as in the horizontal processing, and the vertical processing is notified when the signals hb_s_mux and hb_d_mux are at the high level. In this embodiment, a memory in which the read address and the write address are independent is used, and the read / write can be performed at the same time, so that the operation shown in the timing chart of FIG. 36 is possible.
[0057]
Level 2 processing is started from time t2. This time, the level 1 SS coefficient data (1SS) obtained in the memory 1 is processed. However, since the address signals of the memories mem1 and mem2 are independent, the level 1 processing sequence is almost unchanged. It can be applied to a sequence (the input changes from image data to 1SS coefficient data, and the size is only ¼). Therefore, the level 2 processing continued until time t4 can be easily understood by referring to the operation described in level 1.
[0058]
Next, level 3 processing is performed in the section from time t4 to t6, and level 4 processing is performed in the section from time t6 to t8. In the same manner as obtained in the first embodiment, when calculating the total number of memory accesses for this embodiment,
32x32x2 (H, V) + 16x16x2 + 8x8x2 + 4x4x2 = 2720 cycles
It becomes. However, even when multiple accesses were made, if it was possible at the same time, it was counted as one time. This number of times is ½ that of the prior art, and the number of accesses is 2/3 of that of the first embodiment.
[0059]
The operation at the time of decoding is in the reverse order to the operation described above, but this will be easily understood from the above description and the description related to the first embodiment, and the description will be omitted.
[0060]
<Third embodiment>
FIG. 7 is a block diagram showing a third embodiment of the present invention. The overall block configuration of the present embodiment is basically the same as that shown in FIG. 6, but the memories mem1 to mem4 and the filter unit 130 of the wavelet transform unit are omitted, and only the control unit 110 is illustrated.
[0061]
In the present embodiment, the control unit 110 has a configuration in which an encoding block and a decoding block are allocated exclusively. That is, the main control unit 118, the control signal selection unit 111, and the data selection unit 114 are divided into an encoding-only emin block 118e, an es_mux block 118d, and an ed_mux block 114e, and a decoding-only dmain block 118d, ds_mux block 111d, and a dd_mux block 114d. In addition, a main selection unit (m_mux) 120 and a start / end control unit (se) 122 are added. Input / output to and from the control unit is the same as in FIG.
[0062]
If attention is paid to each block of encoding main, es_mux and ed_mux, it will be understood that the configuration is the same as the configuration of FIG. Similarly, it will be understood that the configurations of the decoding dmain, ds_mux and dd_mux blocks are the same as those in FIG. The added main selection unit (m_mux) 120 simply switches the input or output of each block of es_mux and ed_mux and the input or output of each block of ds_mux and dd_mux in accordance with an external input signal dir. The added start / end control unit (se) 122 merely selects whether to operate the encoding block or the decoding block in accordance with external input signals start and dir. That is, the design of these two blocks is very easy and the circuit scale is very small. Therefore, the designer only needs to focus on the design of the three blocks 118e, 111e, and 114e for encoding, which are the main blocks, and the three blocks 118d, 111d, and 114d for decoding. In addition, since the blocks for encoding and decoding can be designed separately or independently, the design period and efficiency can be dramatically improved.
[0063]
<Fourth embodiment>
FIG. 8 is a block diagram showing a fourth embodiment of the present invention, and shows only the wavelet transform unit. The block configuration of the wavelet transform unit of this embodiment is basically the same as that of the first or second embodiment, but in this embodiment, the buffer memory 106 (hereinafter bmem) is independent of the memories mem1 to mem4. Is different). The buffer memory bmem has the same number of words as the memory mem1, and the write address and the read address are independent. Needless to say, wiring between the buffer memory bmem is added to the control signal selection unit 111 and the data selection unit 114.
[0064]
The operation in this embodiment can be easily understood with reference to the timing charts of FIGS. That is, as shown in FIG. 4, in the first embodiment or the second embodiment, the writing of the S coefficient and the D coefficient as the result of the horizontal processing is performed recursively in the memories mem1 to mem4. Then, as shown in FIG. 9, the writing of the result of the horizontal processing is performed in the buffer memory bmem. Accordingly, the total number of cycles in the present embodiment is 2720 cycles in the case of image data of 32 pixels × 32 lines, as in the first and second embodiments, and a processing time that is ½ that of the prior art is sufficient. It will be understood.
[0065]
The buffer memory bmem is used for storing the S coefficient and the D coefficient as a result of the horizontal processing during the wavelet processing. However, there is no problem even if the buffer memory bmem is used in another block after the wavelet processing is completed. In other words, if a work memory is required in the encoding unit, this buffer memory bmem can be used as the work memory. Since the work memory is usually prepared in most cases, the configuration of this embodiment is suitable.
[0066]
Furthermore, this embodiment exhibits its effect when the most general memory described in the first embodiment is used for the memories mem1 to mem4. That is, it is not necessary to use a memory that is relatively frequently used in an IC and that has an independent read address and write address. A memory having an independent read address and write address has a disadvantage that its area is larger than that of the most common memory in which both addresses are independent because of its multi-function. According to the present embodiment, high-speed processing equivalent to that of the third embodiment can be realized with a minimum memory area.
[0067]
<Fifth embodiment>
According to the fifth embodiment of the present invention, in the same configuration as the fourth embodiment, as shown in FIG. 10, two filter units (filterH) 130h and a filter unit (filterV) 130v are prepared. Assigned exclusively for horizontal processing and the latter for dedicated vertical processing. Although omitted in FIG. 10, it should be noted that in this embodiment, the memories mem1 to mem4 and the buffer memory bmem all use memories having independent read addresses and write addresses.
[0068]
The operation of this embodiment will be described based on the timing chart of FIG. When the input of image data (data) is started at time t0, this is sequentially input to the filter unit 130h, and the obtained S coefficient and D coefficient are written in the buffer memory bmem. Horizontal processing of the first line (note that the lines and pixels are counted from 0th) is started from time t1, and horizontal processing of the second line is started from time t2. When the S or D coefficient of the first pixel in the second line is output, data for calculating the D coefficient in the vertical processing is prepared, and vertical processing using the filter 130v unit is also started. Here, the data for calculating the SS coefficient and the DS coefficient in the vertical processing is already aligned and output at the time when the S or D coefficient of the first pixel of the first line is output. Note that it describes the processing. Now, the image data is sequentially input in the raster order, and the S and D coefficients subjected to the horizontal processing are sequentially written in the buffer memory bmem, and simultaneously read in the vertical direction, and further subjected to the vertical processing at the same time SS, SD. , DS and DD coefficients are written. Such an operation is possible because the configuration includes two sets of filter units 130h and 130v. Level 1 processing ends at time t4 and level 2 processing begins. At time t7, level 2 processing ends and level 3 processing starts. At level t10, level 3 processing ends and level 4 processing ends. Start, and the entire process ends at time t13.
[0069]
When processing image data of 32 pixels × 32 lines by simultaneous execution of the horizontal processing and vertical processing as described above, the total number of cycles in this embodiment is 1480 cycles, which is about 1 of the total number of cycles of the prior art. Because of / 4, a very high speed operation is possible.
[0070]
<Sixth embodiment>
FIG. 12 is a block diagram showing a sixth embodiment of the present invention. The block configuration of this embodiment is basically the same as that of the second embodiment, but in this embodiment, as shown in FIG. 12, three line memories 107s (line mem) for storing S coefficients are used. (S0), line mem (S1), line mem (S2)) and three line memories 107d (line mem (D0), line mem (D1), line mem (D2)) for storing D coefficients, Further, the data selection unit (d_mux) 114 includes signal lines for these line memories.
[0071]
The operation of the present invention will be described based on the timing chart of FIG. Input of image data (data) is started at time t0, and is input to the filter unit 130 and subjected to horizontal processing. The obtained S coefficient is stored in line mem (S0) in the line memory 107s, and the D coefficient is stored in the line memory 107d. Written to the line mem (D0). When the horizontal processing of the first line is started from time t1, the S coefficient written in lime mem (S0) is sequentially shifted to line mem (S1). The same applies to the D coefficient of line mem (D0). When the horizontal processing of the first line is completed at time t2, data for calculating each frequency band signal in the vertical processing is prepared. Here, once the input of the image data is stopped, vertical processing is performed on the S coefficient written in the line memory 107s and the D coefficient written in the line memory 107v, and SS, SD, DS and The DD coefficient is written into the memory mem1. At time t3, the input of image data is resumed, and the S coefficient of the third line is written in line mem (S0) and the D coefficient is written in line mem (D0). The S coefficient and D coefficient one line before are shifted to line mem (S1) and line mem (D1). This process is sequentially performed. The vertical processing for the last two lines (from time t4 to t5, from time t5 to t6) has all the necessary S coefficients and D coefficients (mirror processing is applied to the last line), so continues. Processed. Level 1 processing ends at time t6. In the following, time t6 to t9 are level 2 processing, time t9 to t10 are level 3 processing, and time t10 to t11 are level 4 processing.
[0072]
As long as the six line memories used in this embodiment can perform reading in parallel, any one such as a general register or a shift register may be used. When processing image data of 32 pixels × 32 lines, the total number of cycles in this embodiment is
(32x32x2) + (16x16x2) + (8x8x2) + (4x4x2) = 2720 cycles
It turns out that it becomes. The number of processing cycles is about half that of the prior art, and high-speed operation can be realized with a small circuit scale.
[0073]
<Seventh embodiment>
FIG. 14 is a block diagram showing a seventh embodiment of the present invention. The block configuration of this embodiment is basically the same as that of the sixth embodiment (FIG. 12), but this embodiment includes two filter units 130h and 130v as shown in FIG. And dedicated to vertical processing.
[0074]
The operation of this embodiment will be described based on the timing chart of FIG. When input of image data (data) is started at time t0, the S coefficient is written in line mem (S0) and the d coefficient is written in line mem (D0). When horizontal processing of the first line is started from time t1, the S coefficient written in line mem (S0) is sequentially shifted to line mem (S1). The same applies to the D coefficient of line mem (D0). When the horizontal processing of the first line is completed at time t2, data for calculating each frequency band signal in the vertical processing is prepared. After time t2, the horizontal processing is performed by the horizontal processing filter unit 130h, and the results are sequentially written in the line memories 107s and 107d. Reading is performed simultaneously with this writing, vertical processing is performed by the filter unit 130v dedicated to vertical processing, and the result is written to the memory mem1. This process is sequentially executed, and the level 1 process ends at time t3. Level 2 processing is performed from time t3, but level 2 processing is subject to level 1 SS coefficients. In the following, processing from level t3 to t6 is level 2, processing from time t6 to t8 is processing at level 3, and processing from time t8 to t10 is processing at level 4.
[0075]
As long as the six line memories used in this embodiment can perform reading in parallel, any one such as a general register or a shift register may be used. The above operation can be realized because two filter units are used. When processing image data of 32 pixels × 32 lines, since the total number of cycles in this embodiment is increased by 2 lines at each level, it will be apparent from FIG. 15 that it is 1480 cycles. This number of processing cycles is about ¼ of the processing time of the prior art, and a very high speed operation can be realized with a small circuit scale.
[0076]
<Eighth embodiment>
According to the eighth embodiment of the present invention, the basic block configuration is the same as that of the first embodiment or the second embodiment. However, as shown in FIG. , DS and DD are divided into four independent memories dedicated to coefficient data, and further, as shown in FIGS. 18 and 19, two filter units 130_1, which can be used for both horizontal processing and vertical processing, 130_2, and the difference is that each is used by switching input / output between horizontal processing and vertical processing.
[0077]
The operation of this embodiment will be described based on the memory map of FIG. 17, the connection diagrams of FIGS. 18 and 19, and the timing chart of FIG. FIG. 17 is a diagram showing a memory map. As preprocessing, raster data (external input image data or previous level SS coefficient data) as shown on the left side is dedicated to each of the four coefficients as shown on the right side in advance. It must be relocated on the memory. This rearrangement is performed according to the following rules. For example, in the case of level 1 processing, the 0th pixel data of the 0th line of raster data (data) is stored in the 0th pixel of the 0th line of the SS memory in the memory mem1, and the 0th line of the SD memory is stored. The first pixel data of the 0th line of the raster data is stored in the 0th pixel. The 0th pixel of the first line of the raster data is stored in the 0th pixel of the 0th line of the DS memory, and the 1st pixel of the first line of the raster data is stored in the 0th pixel of the 0th line of the DD. Eye data is stored. That is, the even-numbered pixels (the 0th line is also counted as even) are stored in the SS memory, the even-numbered odd-numbered pixels are stored in the SD memory, and the odd-numbered lines. The even-numbered pixels of the eye are stored in the DS memory, and the odd-numbered pixels of the odd-numbered lines are stored in the DD memory.
[0078]
The data rearranged in the four memories in the memory mem1 in this way is first connected as shown in FIG. 18 by the data selection unit 114, and the horizontal processing is performed using the two filter units 130_1 and 130_2 simultaneously. Done. Since each of the memories SS to DD in the memory mem1 is independent, reading / writing can be performed at the same time. The even lines are processed by the filter unit (filter1) 130_1, the odd lines are processed by the filter unit (filter2) 130_2, and the results are simultaneously written in the respective memories. Next, the connection is changed as shown in FIG. 19, and vertical processing is performed. That is, even-numbered pixels are processed by the filter unit (filter1) 130_1, odd-numbered pixels are processed by the filter unit (filter2) 130_2, and the result is simultaneously written in each memory.
[0079]
The above is the case of level 1 processing, but in the case of processing after level 2 as well, the processing target data is the SS coefficient data of the previous level, which is processed after being rearranged, and the memories mem2 to mem4 Is the same except using.
[0080]
Next, the operation of this embodiment will be described based on the timing chart of FIG. When input of image data (data) is started at time t0, first, image data (raster data) is distributed and stored in four memories in the memory mem1 as shown in FIG. 17 (tr in the figure). Input of image data is completed at time t1, horizontal processing is performed by the connection shown in FIG. 18 until time t2, and then vertical processing is performed by the connection shown in FIG. 19 until time t3. Level 1 processing ends at time t3. Between time t3 and t4, the level 1 SS coefficient data stored in the SS memory in the memory mem1 is sorted and stored in the four memories in the memory mem2 according to the rules shown in FIG. At time t4, the input of the SS coefficient of level 1 is completed, horizontal processing is performed on the SS coefficient data until time t5, and then vertical processing is performed until time t6. Thereafter, the same processing is performed until time t12, and the processing ends.
[0081]
The total number of cycles in the present embodiment is as follows when processing image data of 32 pixels × 32 lines.
32x32 + (16x16x3) + (8x8x3) + (4x4x3) + (2x2x2) = 1843 cycles
It becomes. This processing cycle number is about 1/3 of the processing time of the prior art, and a very high speed operation can be realized. The number of cycles excluding the time for data distribution performed prior to processing at each level is only 824 cycles.
[0082]
<Ninth embodiment>
According to the ninth embodiment of the present invention, the buffer memory bmem is provided in the same basic block configuration as in the eighth embodiment, as in the fourth embodiment, and the buffer memory bmem is also stored in the memories mem1 to mem4. As shown in FIG. 21, it is divided into four independent memories dedicated to SS, SD, DS, and DD coefficients as shown in FIG. However, each of the four memories constituting the buffer memory bmem has the same number of words as the memory mem1.
[0083]
The operation of this embodiment will be described based on the timing chart of FIG. When input of image data (data) is started at time t0, this data (raster data) is distributed and stored in four memories in the memory mem1 as in the case of the eighth embodiment (in the figure). tr). Input of image data (data) is completed at time t1, horizontal processing is performed until time t2, and the result is written in the buffer memory bmem. The operation at this time is the same as that in the eighth embodiment except that the horizontal processing result is written in the buffer memory bmem (see FIG. 18).
[0084]
Subsequently, data is read from the buffer memory bmem from time t2 to t3, and vertical processing is performed. For each coefficient, only the SS coefficient is written in the corresponding memory in the memory mem2, and the other three coefficients SD, DS, and DD are written in the corresponding memory in the memory mem1. Level 1 processing ends at time t3. In the present embodiment, since reading of the SS coefficient of level 1 from the buffer memory bmem can be performed in parallel with the processing of level 2, the level 2 processing is immediately started from time t3. Thereafter, level 2 processing is performed from time t3 to time t5, level 3 processing is performed from time t5 to time t7, and level 4 processing is performed from time t7 to time t9.
[0085]
The total number of cycles in this embodiment is when processing image data of 32 pixels × 32 lines.
32x2 + (16x16x2) + (8x8x2) + (4x4x2) + (2x2x2) = 1704 cycles
It can be seen from FIG. The number of processing cycles is less than 1/3 that of the prior art, and high-speed operation can be realized. The number of cycles excluding the time for first distributing data is only 680 cycles.
[0086]
<Tenth embodiment>
According to the tenth embodiment of the present invention, the basic block configuration is the same as the first embodiment, the second embodiment, the third embodiment, the sixth embodiment or the seventh embodiment, but at each level. As shown schematically in FIG. 23, each of the memories mem1 to mem4 corresponding to the number of words is ¼, and the bit depth is a bit depth required for each coefficient of SS, SD, DS, and DD. Equal to the sum. For example, when each coefficient of SS, SD, DS, and DD is 8 bits, the bit depth of each memory is 32 bits. Of course, even if the number of bits of each coefficient of SS, SD, DS, and DD is different, there is no problem as long as the sum of necessary bit depths is secured. The operation of the present embodiment can be represented by the same timing chart as in FIG. 20 when applied to the configuration of the eighth embodiment (FIG. 16), for example.
[0087]
According to the present embodiment, it is possible to reduce the memory size by collecting the memory locations separated for each frequency band signal into one memory location. This is because, in general, in the memory in the IC, when the number of words × bit depth is the same, the smaller the number of words, the smaller the area. Further, since the number of control signals such as addresses can be reduced to 1/4, there is an advantage that wiring is reduced, delay time is reduced, and noise is reduced.
[0088]
<Eleventh embodiment>
According to the eleventh embodiment of the present invention, in the same configuration as the fourth and ninth embodiments using the buffer memory bmem, not only the memories mem1 to mem4 but also the buffer memory bmem is the tenth embodiment. As described in the example, the word number is 1/4 and the bit depth is the sum of the required bit depths for the SS, SD, DS, and DD coefficients. FIG. 24 schematically shows such a state. Even if the number of bits of the SS, SD, DS, and DD coefficients is different, there is no problem as long as the sum of the necessary bit depths is secured.
[0089]
The operation of the present embodiment can be represented by the same timing chart as in FIG. 22 when applied to the configuration of the ninth embodiment (FIG. 21), for example. According to the present embodiment, the memory locations divided for each frequency band signal are combined into one memory location, so that the memory size including the buffer memory bmem can be reduced as described in the tenth embodiment. Further, there are advantages such as a reduction in delay time and noise due to a decrease in the number of control signals such as addresses.
[0090]
<Twelfth embodiment>
FIG. 25 is a block diagram showing a twelfth embodiment of the present invention. The wavelet transform unit 100 includes a level 1 wavelet transform unit module 100_level1, a level 2 wavelet transform unit module 100_level2, a level 3 wavelet transform unit module 100_level3, and a level 4 wavelet transform unit module 100_level4. Each wavelet transform unit module has basically the same configuration as that of each of the above embodiments except that it is related to only one level of processing corresponding to each of the wavelet transform unit modules. , Control of data transfer within the module, control of data transfer with an external or adjacent level module, and control unit for exchanging control signals with the external or adjacent level module.
[0091]
That is, the wavelet transform unit module 100_level1 for level 1 includes a memory mem1, a control unit 110_level1, and a filter unit 130_level1. The memory mem1 has the same number of words as image data (data) input from the outside. The wavelet transform unit module 100_level2 for level 2 includes a memory mem2, a control unit 110_level2, and a filter unit 130_level2, and the memory mem2 has a ¼ word number of the memory mem1. The wavelet transform unit module 100_level3 for level 3 includes a memory mem3, a control unit 110_level3, and a filter unit 130_level3. The memory mem3 has a word number that is 1/4 that of the memory mem2. The wavelet transform unit module 100_level4 for level 4 includes a memory mem4, a control unit 110_level4, and a filter unit 130_level41, and the memory mem4 has a ¼ word number of the memory mem3.
[0092]
The level 1 control unit 110_level1 has an external start signal as an input signal and a decode end signal dend1 from the level 2, and has an external decode end signal dend and an encode end signal eend1 to the level 2 as output signals. As input / output signals, there are a data input / output signal data1 for level 2, an input / output signal for memory mem1, and an input / output signal for filter unit 130_level1. The input signal of the control unit 110_level2 of the level 2 is the encoding start signal eend1 from the level 1 and the decoding end signal dend2 from the level 3, and the output signal is the decoding end signal dend1 to the level 1 and the encoding end to the level 3 The input / output signal is a data input / output signal data2 for level 3, an input / output signal for the memory mem2, and an input / output signal for the filter unit 130_level2. The input signal of the control unit 110_level3 of level 3 is the encoding start signal eend2 from level 2 and the decoding end signal dend3 from level 4, and the output signal is the decoding end signal dend2 to level 2 and the encoding end to level 4 The input / output signal is a data input / output signal data3 for level 4, an input / output signal for memory mem3, and an input / output signal for filter 130_level3. An input signal of the control unit 110_level4 of level 4 is an encode start signal eend3 from level 3 and an external decode start signal dstart, and an output signal is a decode end signal dend3 to level 3 and an external encode end signal eend. The input / output signals are an input / output signal for the memory mem4 and an input / output signal for the filter unit 130_level4.
[0093]
The timing chart of the operation of this embodiment is almost the same as that shown in FIG. 4 (for encoding) or FIG. 5 (for decoding). The operation during encoding will be described. When the start signal is input, the wavelet transform unit module 100_level1 performs horizontal processing on image data (data) input from the outside, and then executes vertical processing. When the level 1 processing is completed, this is notified to the control unit 110_level2 by the end1 signal, and the level 2 processing is started in the wavelet transform unit module 200_level2. Thereafter, when the processing up to level 4 is completed, an eend signal is output to the outside.
[0094]
Next, the operation during decoding will be described. When the dstart signal is input, the vertical processing is executed by the wavelet transform unit module 200_level4 on the level 4 coefficient data input from the encoding unit 200, and then the horizontal processing is executed. When the level 4 processing is completed and the level 3 SS coefficient data is reproduced, this is notified to the control unit 110_level3 by the dend3 signal, and the level 3 processing by the wavelet transform unit module 100_level3 is started. When the reproduction of the image data is completed by such wavelet inverse transform processing, a dend signal is output to the outside.
[0095]
According to this embodiment, it is not necessary to design while considering the entire operation over all levels, and only one basic module needs to be designed. By applying this design result to each level, it is possible to design the desired number of wavelet transform units, improving reliability and requesting design changes such as changing the data size or adding levels. Even in cases, it is possible to respond promptly.
[0096]
<Thirteenth embodiment>
FIG. 26 is a block diagram showing a thirteenth embodiment of the present invention. The wavelet transform unit 100 of this embodiment is basically composed of four wavelet transform unit modules as in the twelfth embodiment, but the internal configuration of each wavelet transform unit module is partially different. That is, each of the wavelet transform unit modules 100_level1 to 100_level4 is provided with a buffer memory (bmemi) 106_leveli (i = 1 to 4), for example, as in the fourth embodiment and the fifth embodiment, and further similar to the fourth embodiment. Are provided with two filter units 130h_leveli and 130v_leveli for horizontal processing and vertical processing. The buffer memories bmem1 to bmem4 have the same number of words as the memories mem1 to mem4, respectively. In FIG. 13, the internal configurations of the wavelet transform unit modules 100_level3 and 100_level4 are omitted.
[0097]
The operation of the present embodiment can be represented by a timing chart almost similar to that shown in FIG. The operation during encoding will be described. When the start signal is input, in the wavelet transform unit module 100_level1, horizontal processing and vertical processing for image data input from the outside are executed substantially in parallel. When the level 1 processing is completed, the control unit 110_level2 is notified by the eend1 signal, and the level 2 processing is started in the wavelet transform unit module 100_level2. Thereafter, when the processing up to level 4 is completed, an eend signal is output to the outside and the encoding process is terminated.
[0098]
Next, the operation during decoding will be described. When the dstart signal is input, the wavelet transform unit module 100_level4 executes the wavelet inverse transform vertical processing and then the horizontal processing. When the level 4 processing is completed and the level 3 SS coefficient is reproduced, the control unit 110_level3 is notified by the dend3 signal, and the level 3 processing is started in the wavelet transform unit module 100_level3. When the reproduction process of the image data (data) is completed in this way, a dend signal is output to the outside.
[0099]
In the present embodiment, the processing speed can be made faster than in the twelfth embodiment, and in the same way as in the twelfth embodiment, the design is simplified, the reliability is improved, and the response to the design change request is accelerated. There are advantages.
[0100]
<14th embodiment>
FIG. 27 is a block diagram showing a fourteenth embodiment of the present invention. According to this embodiment, instead of the buffer memory bmemi in each wavelet transform unit module 100_leveli in the thirteenth embodiment, the three line memories 107s_leveli for temporarily holding the S coefficient and the D coefficient are temporarily held. Three line memories 107d_leveli are provided. Naturally, the control unit 100_leveli has input / output signals for these line memories. In FIG. 27, the internal configuration of the wavelet transform unit modules 100_level3 and 100_level4 is the same as that of the wavelet transform unit module 100_level1 or 100_level2, and is omitted, and only input / output signals for other modules or the outside are shown.
[0101]
The encoding timing chart of this embodiment is almost the same as FIG. When the start signal is input, level 1 processing is executed in the wavelet transform unit module 100_level1. When the level 1 processing is completed, the level 2 processing is started in the wavelet transform unit module 100_level2 by the end1 signal. When the processing up to level 4 ends, an eend signal is output to the outside, and the entire processing ends. At the time of decoding, when a dstart signal is input, vertical processing and horizontal processing are performed by the wavelet transform unit module 100_level4. When the level 4 processing is completed and the level 3 SS coefficient is reproduced, the wavelet transform unit module 100_level3 is notified by the dend3 signal, and the level 3 processing is started. When the image data reproduction process is completed, a dend signal is output to the outside.
[0102]
The present embodiment has the same advantages as the seventh embodiment in addition to the same advantages as the twelfth embodiment.
[0103]
【The invention's effect】
As is clear from the above detailed description, the following effects can be obtained.
[0104]
According to the invention of claim 1, by providing a memory for each wavelet transform level, it is possible to shorten the time of horizontal processing (or vertical processing when vertical processing is performed first) and to speed up the processing. it can. The level-corresponding memory is independent for each level operation, and is a storage for finally storing frequency band signals, and as a buffer memory for temporarily storing the result of horizontal processing (or vertical processing). Therefore, address mapping can be freely performed in consideration of ease of addressing or design. Previously, three filters were prepared for each level, and a control mechanism had to be prepared for each. However, the control mechanism was separated from the filter and consolidated into the control unit, and a common filter unit was prepared for all levels. By doing so, it is only necessary to provide the filter unit only with the original calculation function of the filter, and it is possible to perform loop processing, simplifying the circuit configuration and reducing the scale, and facilitating the design.
[0105]
According to the second aspect of the present invention, it is possible to simultaneously read and write the corresponding memory in each level of processing, thereby further speeding up the processing.
[0106]
According to the third aspect of the present invention, since the part constituting the control unit is functionally simple and the circuit scale is reduced, the design or design change of the control unit is further facilitated and the reliability can be enhanced.
[0107]
According to the invention of claim 4, the encoding part and the decoding part of the control unit can be handled independently, and each part becomes functionally simpler and the circuit scale becomes smaller. The design of the part becomes easier and the reliability can be improved.
[0108]
According to the invention of claim 5, in addition to the level-corresponding memory, a buffer memory having at least the same number of words as the maximum memory is provided, and this buffer memory can be shared with buffer memories of other blocks. By using each level of processing, a memory with a small memory area compared to a memory with independent read and write addresses and a memory with independent addresses is used as a level-corresponding memory. High-speed processing comparable to the case becomes possible.
[0109]
According to the invention of claim 6 or 8, further high speed processing is possible by simultaneously executing the horizontal processing and the vertical processing.
[0110]
According to the invention of claim 7, high-speed processing can be realized without increasing the circuit scale by using a line memory that can be configured by a general register or shift register.
[0111]
According to the invention of claim 9 or 10, horizontal processing and vertical processing can be parallelized to further increase the speed, and a general memory whose read address and write address are not independent can be used as a level-corresponding memory, Since it can be used as a buffer memory, an increase in memory area can be avoided.
[0112]
According to the invention of claim 11 or 12, the memory size of the level-corresponding memory or the level-corresponding memory and the buffer memory can be reduced, and the signal delay and noise caused by the wiring related to the memory or buffer can be reduced. .
[0114]
Claim 13 According to this, it is possible to realize an encoding / decoding device having the advantages as described above.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a memory map for an S coefficient and a D coefficient in the first embodiment.
FIG. 3 is a diagram showing an example of a memory map for SS, SD, DS, and DD coefficients in the first embodiment.
FIG. 4 is a timing chart at the time of encoding in the first embodiment.
FIG. 5 is a timing chart at the time of decoding in the first embodiment.
FIG. 6 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.
FIG. 7 is a block diagram showing a configuration of a third exemplary embodiment of the present invention.
FIG. 8 is a block diagram showing a configuration of a fourth exemplary embodiment of the present invention.
FIG. 9 is a timing chart at the time of encoding in the fourth embodiment.
FIG. 10 is a block diagram showing a configuration of a fifth exemplary embodiment of the present invention.
FIG. 11 is a timing chart at the time of encoding in the fifth embodiment.
FIG. 12 is a block diagram showing a configuration of a sixth embodiment of the present invention.
FIG. 13 is a timing chart at the time of encoding in the sixth embodiment.
FIG. 14 is a block diagram showing a configuration of a seventh exemplary embodiment of the present invention.
FIG. 15 is a timing chart at the time of encoding in the seventh embodiment.
FIG. 16 is a diagram showing a configuration of a memory in an eighth embodiment of the present invention.
FIG. 17 is an explanatory diagram of data rearrangement in the eighth embodiment.
FIG. 18 is a diagram showing connections during horizontal processing in the eighth embodiment.
FIG. 19 is a diagram showing connections during vertical processing in the eighth embodiment.
FIG. 20 is a timing chart at the time of encoding in the eighth embodiment.
FIG. 21 is a diagram showing a configuration of a buffer memory in a ninth embodiment of the present invention.
FIG. 22 is a timing chart at the time of encoding in the ninth embodiment.
FIG. 23 is a diagram showing a memory configuration in a tenth embodiment of the present invention.
FIG. 24 is a diagram showing a configuration of a memory and a buffer memory in an eleventh embodiment of the present invention.
FIG. 25 is a block diagram showing a configuration of a twelfth embodiment of the present invention.
FIG. 26 is a block diagram showing a configuration of a thirteenth embodiment of the present invention.
FIG. 27 is a block diagram showing a configuration of a fourteenth embodiment of the present invention.
FIG. 28 is a block diagram showing a conventional technique.
FIG. 29 is a timing chart at the time of encoding in the prior art.
FIG. 30 is an explanatory diagram of a calculation method of horizontal processing and vertical processing of wavelet transform.
FIG. 31 is a diagram illustrating an example of a memory map of image data.
FIG. 32 shows an example of a memory map for level 1 S and D coefficients.
FIG. 33 is a diagram illustrating an example of a memory map for level 1 SS coefficients, SD coefficients, DS coefficients, and DD coefficients;
FIG. 34 shows an example of a memory map for level 2 S and D coefficients.
FIG. 35 is a diagram illustrating an example of a memory map for level 2 SS coefficients, SD coefficients, DS coefficients, and DD coefficients;
FIG. 36 is a timing chart at the time of encoding in the second embodiment of the present invention.
[Explanation of symbols]
100 Wavelet transform unit
100_level1 ~ 100_level4 wavelet transform unit module
102_1 to 102_4 memory (mem1 to mem4)
106 Buffer memory (bmem)
107s, 107s_level1, 107s_level2 S coefficient line memory
107d, 107d_level1, 107d_level2 D coefficient line memory
110, 110_level1 to 110_level4 control unit
111 Control signal selector (s_mux)
111e Encoding dedicated control signal selection unit (es_mux block)
111d Dedicated decoding control signal selection unit (ds_mux block)
114 Data selection part
114e Encoding dedicated data selection part (ed_mux block)
114d Dedicated decoding data selection unit (dd_mux block)
118 Main control unit
118e Encoding main control unit (emain block)
118d Decode-dedicated main control unit (dmain block)
122 Start / end control unit (se block)
130, 130_1, 130_2 filter section
130h, 130h_level1 to 130h_level4 Horizontal processing filter section
130v, 130v_level1 to 130v_level4 Vertical processing filter section
130_level1 ~ 130_level4 filter part
200 Coding unit

Claims (13)

  A wavelet transform device that performs a plurality of levels of wavelet transform, wherein each of the wavelet transform levels has a one-to-one correspondence with each other, a plurality of independent memories, and a filter unit common to all wavelet transform levels, A wavelet transform device comprising: a control unit that controls data transfer inside the device, data transfer with the outside of the device, and operations of the plurality of memories.   A wavelet transform device that performs a plurality of levels of wavelet transform, wherein each of the wavelet transform levels has a one-to-one correspondence with each other, a plurality of independent memories, and a filter unit common to all wavelet transform levels, A control unit that controls data transfer inside the device, data transfer to the outside of the device, and operation of the plurality of memories, and the plurality of memories have independent read addresses and write addresses. A wavelet transform device characterized by being a memory capable of simultaneous writing. 3. The wavelet transform device according to claim 1, wherein the control unit selectively supplies at least a control signal of an address and an enable signal to the plurality of memories, data transfer inside the device, and data outside the device. 1. A wavelet transform device, which is divided into a part for controlling transfer and a part for controlling these two parts and for transmitting / receiving control information to / from the outside of the apparatus.   4. The wavelet transform apparatus according to claim 3, wherein at least three parts constituting the control unit are divided into a part dedicated for encoding and a part dedicated for decoding, respectively.   A wavelet transform apparatus that performs a plurality of levels of wavelet transform, and has a plurality of independent memories associated with each level of the wavelet transform, and a maximum number of words in the plurality of memories. A buffer memory common to all levels of wavelet transform having at least the same number of words as the memory, a filter unit common to all levels of wavelet transform, data transfer inside the device, data transfer outside the device, and the plurality And a controller for controlling the operation of the buffer memory.   6. The wavelet transform apparatus according to claim 5, wherein the filter unit includes two independent filter units, one of the two filter units being assigned to horizontal processing and the other being assigned to vertical processing. Conversion device.   A wavelet transform device that performs a plurality of levels of wavelet transform, wherein each of the levels of the wavelet transform has a one-to-one correspondence with each other, a plurality of independent memories, a line memory that is common to all levels of the wavelet transform, A filter unit common to all levels of the wavelet transform, and a control unit that controls data transfer inside the apparatus, data transfer to the outside of the apparatus, and operations of the plurality of memories and the line memory. Wavelet transform device.   8. The wavelet transform device according to claim 7, further comprising a horizontal processing filter unit and a vertical processing filter unit as the filter unit.   3. The wavelet transform device according to claim 1, wherein each of the plurality of memories includes a number of independent memories equal to the number of types of wavelet transform coefficients, and is used for both horizontal processing and vertical processing as the filter unit. A wavelet transform device comprising two independent filter units.   6. The wavelet transform device according to claim 5, wherein each of the plurality of memories and the buffer memory includes a number of independent memories equal to the number of types of wavelet transform coefficients, and performs horizontal processing and vertical processing as the filter unit. 2. A wavelet transform device comprising two independent filter units used for both.   3. The wavelet transform apparatus according to claim 1, wherein each of the plurality of memories has at least a bit depth equal to a sum of all kinds of bit depths of wavelet transform coefficients.   6. The wavelet transform device according to claim 5, wherein each of the plurality of memories and the buffer memory has at least a bit depth equal to a sum of all types of bit depths of the wavelet transform coefficients. Conversion device. The wavelet transform device according to any one of claims 1 to 12 and the wavelet transform device, wherein the output data of the wavelet transform device is encoded, or encoded data input from the outside is decoded and the An encoding / decoding device comprising: an encoding unit that inputs to a wavelet transform device.

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