JP3640630B2 - Matched filter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a matched filter used for synchronization acquisition in spread spectrum communication (CDMA communication).
[0002]
[Prior art]
In CDMA communication, the transmission side uses a spreading code (PN code) to perform spread modulation at a chip rate faster than the information rate, and transmits the spread signal. On the receiving side, a replica code (despread code) that is a replica of the spread code is generated, and the received signal is despread.
[0003]
Here, the timing of the replica code (despreading code) needs to exactly match the timing of the spreading code. In order to generate a replica code with accurate timing, first, it is necessary to strictly detect the timing of the spread code. This spreading code timing detection process needs to be performed at a high speed at several times the chip rate (for example, twice).
[0004]
For this purpose, oversampling is performed on the receiving side. That is, when A / D converting the received signal, oversampling is performed at a high rate several times the chip rate, and a correlation value is calculated from a plurality of sampling results for one chip. Thereby, timing detection accuracy (time resolution) can be improved.
[0005]
[Problems to be solved by the invention]
In the matched filter, a shift register is used to temporarily store received data. However, when the number of data is increased by m times due to oversampling, the number of taps (stages) of the shift register is also increased by a factor of m. The frequency of is also m times.
[0006]
In the shift register, the data of all the taps are shifted at the same time at the timing of the shift clock. Accordingly, charging / discharging of the signal line or the like occurs, and the power consumption increases.
[0007]
The increase in power consumption is contrary to the demand for lower power consumption, which is strictly required for mobile communication devices such as mobile phones.
[0008]
However, if there is a case where it is changed to a special configuration only for the purpose of reducing the power consumption of the matched filter, it becomes impossible to share the existing clock or match with the peripheral circuit, and to make it an integrated circuit. It becomes an obstacle.
[0009]
The present invention has been made to solve such problems, and its object is to reduce the power consumption of the matched filter without sacrificing the compatibility with surrounding circuits required for the IC. Is to achieve this efficiently.
[0010]
[Means for Solving the Problems]
In the present invention, a memory (RAM in a broad sense; including a collection of temporary storage elements) that can individually control read / write is used as means for accumulating input data, instead of a shift register. As a result, an operation for uniformly shifting all data becomes unnecessary, and power consumption can be reduced.
[0011]
On the other hand, only the above-mentioned memory is special in that the spread modulation signal is input serially in synchronization with the oversampling clock or the peripheral circuit operates in synchronization with such serial data input. It can not be operated at the right timing.
[0012]
Therefore, in one aspect of the present invention, a temporary storage element is provided in association with each phase of oversampling, and a selector is provided for each set of phases. And after making the data subject to correlation detection into a form that is divided for each phase (perform data conversion, or temporarily accumulate and control the read address), the data is , Input in parallel to the temporary storage element.
[0013]
Then, only the temporary storage element corresponding to the phase of the input data is activated to load (and hold) the data, and each selector selects the held data and supplies it to the portion that performs the correlation calculation.
[0014]
With such a configuration, the load timing of each temporary storage element can be generated at the same operation timing as the shift register, and the conventional technology can be followed. In addition, since the selector is periodically switched corresponding to each phase, the chip clock and the oversampling clock can be effectively used here. Furthermore, even when changing the multiple of oversampling, with such a configuration, it is only necessary to switch the number of temporary storage elements to be used and the number of inputs of the selector in response to the change, and to the required specifications. It can respond flexibly and easily.
[0015]
In this way, it is possible to efficiently achieve low power consumption of the matched filter without sacrificing consistency with surrounding circuits required for the IC.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
[0017]
(Embodiment 1)
FIG. 1 shows a configuration of a matched filter of double diffusion (m = 2: m is a multiple of oversampling) according to the first exemplary embodiment of the present invention.
[0018]
Since m = 2, corresponding to this, two flip-flops (FF: temporary storage element) are used as a basic unit, and the required number of flip-flops (multiple of 2) are arranged.
[0019]
In FIG. 1, for convenience of explanation, four flip-flops (FF) 101a, 101b, 102a, and 102b are provided and connected in parallel. The four flip-flops (FF) 101a, 101b, 102a, and 102b are elements constituting a kind of RAM 105 that can be individually read / written.
[0020]
Here, “a” and “b” attached to the end of the reference symbol correspond to any of two phases (this is referred to as A phase and B phase) generated by double oversampling. It shows how.
[0021]
In other words, every other flip-flop is arranged in association with every other phase.
[0022]
On the other hand, n selectors are prepared (only two reference numerals 107 and 108 are shown in FIG. 1), and one selector is arranged for every two adjacent flip-flops (a set of flip-flops). The output from each flip-flop is used as an input, and either one is selected.
[0023]
That is, one selector has two input terminals, a terminal and b terminal. Here, “a” and “b” of each terminal indicate which phase corresponds to two phases (A phase and B phase) generated by double oversampling. As shown in FIG. 1, the selectors 107 and 108 incorporate switches SW1 and SW2, respectively.
[0024]
The load timings of the flip-flops 101a to 102b are individually controlled by the control clocks CL0 to CL3 supplied from the clock control circuit 106.
[0025]
The selector control circuit 109 controls which input the selectors 107 and 108 select. In the circuit of FIG. 1, each time the selector switching signal SC is output, the switches (SW1, SW2) built in each selector are switched.
[0026]
The clock control circuit 106 and the selector control circuit 109 operate using the oversampling clock CK as a basic operation clock, and the selector control circuit 109 receives the selection signal SEC.
[0027]
The correlation calculation unit 6 includes multipliers 7 and 8 for multiplying a despread code (only two chips C0 and C1 are shown in FIG. 1) and a cumulative adder 9.
[0028]
The oversampled spread modulation signal (oversampling data series) is applied via the input terminal I0 in synchronization with the oversampling clock CK. As shown in the upper side of FIG. 2, oversampling data is input in a form in which A phase and B phase appear alternately, such as 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B,. Is done. Here, for example, “1A” indicates A phase data of the first sample, and “1B” indicates B phase data of the first sample.
[0029]
In the matched filter of FIG. 1, such input data is passed through the arrangement conversion circuit 100 to obtain a data string (Din) divided for each phase as shown in the lower side of FIG. The arrangement-converted data is supplied to the flip-flops 101a to 102b.
[0030]
As shown in the lower side of FIG. 2, the data after the layout conversion is classified for every A phase and every B phase so as to match the order of correlation calculation processing, such as 1A, 2A, 1B, and 2B. ing.
[0031]
The data string (Din) divided for each phase is loaded into the flip-flops 101a to 102b at the timing shown in FIG. 3, and the selectors 107 and 108 are switched to supply data to the correlation calculation unit 6. Then, despreading and correlation calculation are performed.
[0032]
As shown in FIG. 3, each circuit operates in synchronization with the positive edge of the oversampling clock CK. At time t1, the selector switching signal SC is output, whereby both the switches SW1 and SW2 built in the selectors 107 and 108 are switched to the a terminal side.
[0033]
On the other hand, at time t1, the control clock CL2 becomes active, and the flip-flop 102a is loaded with the data “1A” (A phase data of the first sample) of the spread modulation signal (Din) that has been oversampled twice. At time t2, the multiplier 8 performs multiplication of 1A × C1.
[0034]
At time t2, the control clock CL0 becomes active, and data “2A” (A phase data of the second sample) is loaded into the flip-flop 101a. Next, at time t3, the multiplier 7 sets 2A × C0. In addition to multiplication, the adder 9 performs multiplication of 1A × C1 + 2A × C0 and outputs a correlation value (calculation result).
[0035]
At time t3, a selector switching signal SC is output, and the switches SW1 and SW2 built in the selectors 107 and 108 are switched to the b terminal side.
[0036]
At the same time, the control clock CL3 becomes active at time t3, and data “1B” (B phase data of the first sample) is loaded into the flip-flop 102b. At time t4, data “2B” (B phase data of the second sample) is loaded.
[0037]
Then, at time t5, the adder 9 outputs the calculation result (1B × C1 + 2B × C0).
[0038]
As is clear from the above operation, the clocks CL0 to CL3 for controlling each flip-flop are synchronized with the oversampling clock as in the case of using a shift register without using the present invention (FIGS. 11 and 12). Therefore, the timing can be controlled by using the existing clock as it is, and the matching with the peripheral circuit is good, which is advantageous in design.
[0039]
Note that the matched filter using the shift register 5 shown in FIG. 11 shifts data to the right for each tap in synchronization with the oversampling clock CL. The operation timing is as shown in FIG.
[0040]
Similarly, the selector of the present invention may be switched regularly for each phase of oversampling, and in this case, the timing can be easily controlled using the existing clock as it is. Therefore, data flows efficiently in a pipeline in synchronization with the oversampling clock, as in the case of using a shift register, and efficient processing is maintained. On the other hand, since it is not necessary to shift a series of data by the shift register, power consumption is remarkably reduced. In addition, the configuration of FIG. 1 can be flexibly changed and expanded in accordance with the multiple of oversampling, the total number of chips of data included in the search range, and the like, and the circuit design is also highly flexible.
[0041]
(Embodiment 2)
FIG. 4 is a circuit diagram showing a configuration of the matched filter according to the second embodiment of the present invention.
[0042]
The basic configuration and operation are the same as those in the first embodiment. However, in the matched filter of FIG. 4, the flip-flop is a flip-flop with a load / hold function, has a FF control function instead of clock control, and the clock of each flip-flop is common. This is different from the matched filter of FIG.
[0043]
The register group 205 provided in the matched filter of this embodiment includes flip-flops 201 to 204 with a load / hold function. The clocks of the flip-flops 201 to 204 are inputted in parallel from the clock signal terminal CL, and the load / hold is controlled by F0 to F3 inputted from the FF control circuit 206 (1 is loaded, 0 is held) ).
[0044]
The circuit of FIG. 4 operates as shown in FIG. This operation is almost the same as that shown in FIG.
[0045]
(Embodiment 3)
FIG. 6 is a diagram illustrating a configuration of a matched filter according to the third embodiment. This matched filter uses the circuit configuration of FIG. 1 (may be the circuit configuration of FIG. 4) as it is, and temporarily stores oversampling data (data not subjected to data arrangement conversion) D0 in the memory 301. Read access is controlled by the read control circuit 302, and data of one phase is continuously supplied to the flip-flops 101a to 102b by the total number of chips belonging to the search range.
[0046]
Since the input data in the above-described embodiment has the data of each phase arranged alternately, the selector has to be switched for each phase. For example, in the case of double oversampling, it is necessary to switch the selector every two clocks. Since the power consumption that accompanies this switching cannot be ignored, in this embodiment, the number of times the selector is switched is extremely reduced to further reduce the power consumption.
[0047]
The characteristic operation of the matched filter shown in FIG. 6 will be described with reference to FIGS. 7 (a), (b), and (c).
[0048]
The search range of the matched filter in FIG. 6 is assumed to be equivalent to, for example, 512 chips as shown in FIG. In the matched filter of FIG. 6, first, as shown in FIG. 7A, the switches SW1 and SW2 of the selectors 107 and 108 are switched to the a terminal side.
[0049]
Then, only the A phase data for 512 chips is continuously output from the memory 301, and the correlation value in the entire search range is obtained for the A phase data.
[0050]
Next, as shown in FIG. 7 (b), the switches SW1 and SW2 are switched to the b terminal side, and similarly, only the B phase data for 512 chips is continuously output from the memory 301. The correlation value in the search range is obtained.
[0051]
In this case, switching of the selectors 107 and 108 may be performed once per 512 chips, and the power consumption in the selector is significantly reduced. In this example, one phase of data is continuously supplied for the number of chips corresponding to the entire search range, but the present invention is not limited to this.
[0052]
That is, the timing for reading data and the time width for continuously supplying data of one phase can be freely adjusted. This leads to an improvement in communication performance.
[0053]
FIG. 8 shows the operation timing of the matched filter of FIG. When a start signal is input to the memory 301, accumulation of the oversampling data D0 (arranged so that the data of each phase appear alternately) D0 is started from time t1. For example, when the accumulation of data corresponding to the search width is completed, the read address (add) is controlled from time t2, for example, reading of the A-phase data is started, and the read data DX is continuously read. The flip-flops 101a to 102b are supplied.
[0054]
The characteristic operations of the matched filter of the present invention described above are summarized as shown in FIG.
[0055]
That is, first, the number of temporary storage elements corresponding to a multiple of oversampling is provided, each temporary storage element is associated with each phase of oversampling, and a plurality of adjacent temporary storage elements corresponding to each phase of oversampling are provided. A set of outputs from the storage elements is provided, and a selector is provided for each set of outputs (step 400).
[0056]
Next, the oversampling data (received signal) is processed by rearranging the data so as to divide the data for each phase, or once stored in the memory and the read address is controlled, Data is extracted for each phase data and supplied to the temporary storage element (step 401). When supplying one phase of data after storage in memory, it is desirable to supply only one phase of data continuously over the entire interval of the search range.
[0057]
On the other hand, the selector is switched so as to correspond to the phase of the supplied data, and the load timing in the temporary storage element corresponding to the phase of the supplied data is controlled by the timing control signal to load the data appropriately. Then, correlation detection calculation is performed using the loaded data (step 402).
[0058]
When the processing of one phase of data is completed, the selector is switched to correspond to the next phase, and the same loading operation and correlation detection calculation are repeated (step 403).
[0059]
(Embodiment 4)
Embodiment 4 of the present invention is an example in which the matched filter of the above embodiment is applied to a CDMA receiver.
[0060]
FIG. 10 is a diagram of a configuration of a CDMA receiving apparatus according to the fourth embodiment of the present invention.
[0061]
The CDMA receiver according to the fourth embodiment includes a receiving antenna 901, a high-frequency signal processing unit 902 that performs filtering and amplification at a predetermined frequency, an AD conversion unit 903 that converts an analog signal into a digital signal, and data that demodulates the received signal. A demodulator 904, a data decoder 905 that performs decoding, a CODEC unit 906 that converts the decoded signal into speech, a matched filter 907 that acquires or maintains synchronization with the one that performs communication, and generates a despread code A code generation unit 908, a clock generation unit 909, and a timing control unit 910 are provided.
[0062]
The matched filter 907 receives a spread modulation signal composed of a digital signal subjected to spread modulation from the AD conversion unit 903, is applied with the clock CL 1 provided from the clock generation unit 909, and the despread code generated from the code generation unit 908 is received. Entered. The timing control unit 910 controls the timing for performing despreading. In the matched filter 907, a despreading operation is performed on the despread code provided from the code generator 908 and the spread modulation signal supplied from the AD converter 903, and the result of the despread operation is obtained as a result of synchronization acquisition or maintenance. It is output to 904. The data demodulating unit 904 demodulates data based on the timing result obtained from the matched filter 907 and gives data to the data decoding unit 905.
[0063]
The matched filter 907 has the same configuration as that of the first embodiment, for example, and the power consumption of the matched filter is greatly reduced, which contributes to lower power consumption of the entire receiving apparatus. .
[0064]
The matched filter of the present invention may be provided in a base station apparatus that performs CDMA mobile radio communication or a radio receiver of the mobile apparatus, or may be used as a radio receiver of other communication terminals.
[0065]
In the above description of the embodiment, the case of double oversampling has been described, but the present invention is not limited to this.
[0066]
【The invention's effect】
As described above, according to the present invention, it is possible to reduce the power consumption of the matched filter without sacrificing the compatibility with surrounding circuits required for the IC and maintaining the flexibility of the circuit. Can be achieved efficiently.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing the configuration of a matched filter according to a first embodiment of the present invention. FIG. 2 is a diagram for explaining the phase of a spread modulation signal (received data sequence) that has been oversampled by a factor of 2. FIG. 4 is a timing diagram for explaining the operation of the matched filter shown in FIG. 1. FIG. 4 is a circuit diagram showing the configuration of the matched filter in the second embodiment of the present invention. FIG. 6 is a circuit diagram showing the configuration of the matched filter in the third embodiment. FIG. 7A is a diagram for explaining the characteristics of the matched filter in FIG. 6 (continuous supply of A-phase data). FIG. 8B is a diagram for explaining the characteristics of the matched filter in FIG. 6 (continuous supply of B-phase data). FIG. 8C is a diagram showing the search range of the matched filter in FIG. FIG. 9 is a flow chart showing the characteristic operation of the matched filter of the present invention. FIG. 10 shows the overall configuration of a CDMA receiver equipped with the matched filter of the present invention. FIG. 11 is a circuit diagram showing the configuration of a conventional matched filter. FIG. 12 is a timing diagram for explaining the operation of the matched filter shown in FIG.
6 Correlation Operation Units 7 and 8 Multiplier 9 Adder 100 Arrangement Conversion Units 101a to 102b Flip-flop (Temporary Storage Element)
105 Data storage unit (RAM)
106 clock control circuits 107 and 108 selector 109 selector control circuit

Claims (2)

A matched filter that performs correlation detection on a spread modulated data sequence that has been oversampled m times (m is a natural number of 2 or more),
A memory for storing the data series;
The number of temporary storage elements corresponding to a multiple “m” of the oversampling, wherein the data load timing of each temporary storage element is individually controlled, and each temporary storage element has a phase of each oversampling. A plurality of temporary storage elements associated with
A plurality of sets provided for each set of phase data in order to selectively extract one of the sets of oversampling phase data output from each of the plurality of temporary storage elements. Selectors and
A correlation calculation unit that performs despreading and predetermined calculation for data output from each of the plurality of selectors;
Data of one phase over a predetermined time width is continuously output from the memory, and the data of the one phase is continuously supplied to the correlation operation unit via the temporary storage element and the selector. When the calculation process is performed and the supply of the data for the predetermined time width for the one phase is finished, the data for the predetermined time width for the other phase is continuously output, and the data of the other phase is output. Data is continuously supplied to the correlation calculation unit via the temporary storage element and the selector to perform a correlation calculation process, and the same process as the above process is performed on data of all phases of oversampling. Matched filter. A CDMA receiver equipped with the matched filter according to claim 1 .

Images