JP3533825B2 - Logical operation unit and logical operation device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logical operation unit.

[0002]

2. Description of the Related Art First, communication processing, which is one of the promising application areas of the present invention, will be described. The present invention can be widely applied to processing areas in which various inter-bit operations are performed.

Among various communication processes, a logical operation between bits is frequently used in a layer which directly handles a digital signal flowing through a transmission line. On the other hand, in order to achieve real-time processing of a high-speed signal, a digital signal serially flowing through the transmission line is expanded into a parallel signal at the entrance of the processing circuit. However, in the process of converting the serial signal to the parallel signal, no inter-bit operation is performed.

Next, the present processing means will be described. As a means for realizing a logical operation, two processes, a process by a wiring logic and a process by a program logic are known. The “processing by wiring logic” is processing for connecting a plurality of logic elements such as NAND elements and NOR elements to each other via metal wiring to realize a desired function. In this case, since the wiring between the logic elements can be freely determined, in the bit-to-bit logical operation, it is possible to handle whatever position the bit data to be operated is assigned by parallel expansion. it can. Also,
Since a specific operation can be processed with a small number of clocks, wiring logic processing is very often used in the field of high-speed digital signal processing. A custom LSI, a gate array, an FPGA, and the like are examples of devices that provide a processing circuit based on the wiring logic.

On the other hand, "processing by program logic" means that a program indicating a processing procedure is stored in a memory in advance,
If necessary, the program is decoded one by one, and the data to be processed stored in the memory or register is given to the arithmetic and logic unit that provides general-purpose arithmetic and logical operations, processed, and the result is stored in the memory. Alternatively, it is a process for realizing a desired function by repeating a series of simple operations of writing back to the register. A device that realizes processing by such program logic is generally called a processor, and the unit of data handled in one cycle is 8
It is a multiple of bits. Hereinafter, the unit of data handled in this one cycle is called a "word".

The logical operations provided by the processor are, in addition to data shift and rotation, AND, OR, EOR, etc. executed at the same bit positions between two data. Therefore, when bit data to be operated in the bit-to-bit operation exists in one data,
In the case where two data are allocated to different bit positions, a shift process of data is performed in advance, and a plurality of basic operations are combined to achieve a desired process. The operating speed of the processor itself has become extremely high in recent years, but in the field of high-speed signal processing in which there is processing with a small calculation granularity such as the above-mentioned bit-to-bit calculation, processing by program logic is rarely used.

[0007]

Next, the drawbacks of the conventional method in the case of operating a digital signal expanded in parallel between bits will be described.

It should be noted that the "logical operation unit" in this specification is not a dedicated arithmetic circuit in which the form of possible logical operation functions or data to be processed is fixed to one, but an external logic operation of a plurality of patterns. It is an arithmetic circuit that executes the arithmetic operation specified by.

When a function is realized only by a custom LSI or a mask programmable gate array, the function is determined and then a dedicated circuit is designed and manufactured, so that the circuit has no versatility and is not versatile as a logical operation unit. There is a problem.

When the function is realized only by the field programmable device such as FPGA, the circuit function can be changed by the in-system programming means, but the circuit cannot be reprogrammed at high speed during the system operation, so that the logical operation is performed. Its use as a unit is subject to severe restrictions.

When the function is realized by the program processing by the processor, the overhead becomes large if the processing is performed in a unit outside the unique word width of each processor. For example, for an inter-bit operation at an arbitrary position, an ordinary arithmetic logic operation unit has a method of processing by combining general-purpose instructions, and therefore consumes a large number of clocks. With this, there is a problem in that it cannot meet the demand for ultra-high-speed processing of digital signals.

The present invention is inflexible in the case where it is realized only by the conventional custom LSI or gate array in the inter-bit arithmetic processing which appears in the communication processing, the FPGA.
Slow speed of function change when realized only by
It is an object of the present invention to provide a logical operation unit capable of eliminating enormous clock consumption when a processor is used.

[0013]

The invention according to claim 1 is
n-bit data input to the n-bit data input port
Data, you must set whether to enable / disable each bit.
Based on the information of the
Input of n bits to change to a value that does not affect the logical operation between
Values on the input side masking circuit and the input side masking circuit
Input controlled n-bit data and output 1-bit
Perform the above bit-to-bit logical operation and output the output of that operation for m
A logical operation execution unit having various n-bit input and m-bit output,
About the m-bit output output from the logical operation execution unit
And m-bit output to enable / disable each bit
Side masking circuit and the output side masking circuit
Only the data of the bit position set to be valid by
It has an m-bit data output port for external output,
Any combination of bits from the input n-bit data
Inter-operation and perform one or more of the m bits.
A logical operation unit characterized by outputting to an arbitrary bit position
It is a knit. The invention according to claim 2 is a logical operation function type.
Function specification section that specifies the class and n-bit data input port
Function specified above for n-bit data input to the
Information of the logical operation function type input from each section and each bit
Based on the information that should be enabled / disabled for each
The value of the bit to be invalidated,
N-bit input mask to change to a value that does not affect arithmetic
Value is controlled by the input circuit and the masking circuit on the input side.
A bit that inputs n-bit data and outputs 1 bit
Performs a logical operation between them and outputs the output of the operation after branching it by m
n-bit input m-bit output logical operation function executing means,
The types of logical operation functions that can be specified by the above function specification section
Correspondingly, there are multiple types of logic operation execution units and the above logic
M-bit output from each logical operation function executing means of the arithmetic execution unit
Output, the logic input from the function specification section
Of the logical operation function execution means corresponding to the information of the operation function type
Select the output and enable / disable the settings for each bit.
Based on the information of power, the above logical operation function real
Set valid / invalid of each bit of m-bit output of line means
M-bit output side masking circuit and the output side mask
The data of the bit position set to be valid in the king circuit
M-bit data output that outputs only the data to the outside of the unit
Has a port and any of the input n-bit data
Performs a bitwise logical operation of the combination and out of m bits
Output to one or more arbitrary bit positions of
It is a characteristic logical operation unit.

[0014]

[0015]

[0016]

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION FIG. 1 is a block diagram of an 8-bit input 8-bit output function circuit FC1 according to an embodiment of the present invention.
2 is a block diagram showing a functional circuit including the logical operation unit according to claim 1. FIG.

8-bit input 8-bit output function circuit FC1
Is an n-bit input-side masking circuit IM, a maximum n-bit input m-bit output logical operation executing unit AE, an m-bit output-side masking circuit OM, and a data output port 1
3 is a logical operation unit for performing an arbitrary combination of bit operations from the input n-bit data and outputting the result to one or more arbitrary bit positions of the m bits.

The input side latch holds n-bit data input to the n-bit data input port 11 n.
Bit input latch. Input side masking circuit I
M is an n-bit input-side masking circuit that sets valid / invalid for each bit of the n-bit data output from the input-side latch, and is a 4-input 1-output selector SI0, SI1, SI2, SI3, SI4. , SI5, S
It has I6 and SI7.

The logical operation execution unit AE is a logical operation execution unit of maximum n-bit input and m-bit output which performs inter-bit logical operation on only the bit data set to be valid in the input side masking circuit IM as the operation target.

The output-side masking circuit OM is an m-bit output-side masking circuit that sets valid / invalid for each bit of the m-bit output output from the logical operation executing unit AE, and is a 4-input 1-output selector SO0. , SO1,
It has SO2, SO3, SO4, SO5, SO6, and SO7.

The data output port 13 is an m-bit data output port for outputting only the data of the bit position set to be valid in the output side masking circuit OM to the outside of the unit. Further, instead of the data output port 13, an m-bit output side latch that holds only the data of the bit position set to be valid in the output side masking circuit OM may be provided.

In this case, the bit width n of the input data is
Is set to 8 and the bit width m of the output data is also set to 8. Therefore, the widths of the port 11 on the input side, the port 13 for making mask information and the port 13 on the output side, and the mask information 14 are all 8. Further, the configuration is such that no latch is used on both the input / output side, and the inter-bit operation functions provided by the logic operation execution unit AE are the following four types.

Function (a): Logical product (referred to as "All AND") in which all valid bits are operated on. Function (b): Logical sum (referred to as "All OR") function in which all effective bits are operated on. (C): Exclusive-OR (referred to as "AllXOR") function that operates on all effective bits Function (d): Respective logical negation (referred to as "All NOT") of all effective bits Implements these functions The means may be any device that provides wiring logic.

For example, when the required logic function is known in advance as in this case, the hardware resource can be minimized by using a custom LSI or a mask programmable gate array. Also, FPG
If A is used, the circuit can be changed later.

In FIG. 1, the above functions (a), (b),
In each of (c) and (d), "00", "01",
Encode as "10" and "11", Function
The decoder is configured to expand to a 4-bit width. Of course, "0001", "0010", "010"
Decoded expressions such as "0" and "1000" may be used directly.

In order to hold the input side mask information 12 having an 8-bit width, the output side mask information 14, and the encoded function specifying information 15 having a 2-bit width, for example, an SRAM, a DRAM, a flash memory, or the like. Use an element that can hold the state.

The 8-bit data input from the input port 11 is first input side masking circuit I for each bit position.
Input to M.

FIG. 2 is a diagram showing the configuration of the 8-bit input side masking circuit IM in the above embodiment.

The selection operation of the 4-input 1-output selectors SI0 to SI7, which operate independently for each bit position, follows the following condition judging sequence.・ Condition judgment sequence: Input side masking information 21
The valid "1" or invalid "0" of the target bit is determined from, and when it is "1", the terminal 25 is selected. That is, the input bit information is output as it is and becomes the calculation target.・ Condition judgment sequence: Input side masking information 21
Is "0" and the ALL AND 26 is "1", the terminal 22 is selected. That is, in the AND operation of all the bits, the data of this bit position is invalidated by giving the data “1” to the Wide-AND element 16.・ Condition judgment sequence: Input side masking information 21
Is “0” and All OR27 is “1”,
Select the terminal 23. That is, in the OR operation of all bits, the data of "0" is given to the Wide-OR element 17 to invalidate the information of this bit position.・ Condition judgment sequence: Input side masking information 21
Is 0 and the All XOR 28 is 1, the terminal 23 is selected. That is, in the exclusive OR operation of all the bits, the data of this bit position is invalidated by giving the data “1” to the Wide-XOR element 18. -Condition determination sequence: When the input side masking information is "0" and AllNOT29 is "1",
Select the terminal 24. That is, in the NOT operation of all bits, the NOT operation of the input bit is performed by the NOT element 1.
It cancels by giving to 9 and invalidates the information of this bit position.

The above condition judgment sequences 1 to 3 can be easily realized by wiring logic using logic elements. That is, each of the 4-input 1-output selectors SI0 to SI7 can be easily realized by the wiring logic using the logic elements.

In the above embodiment, the information of the bit position to be invalidated is processed and output by the input side masking circuit IM according to the designated function so as not to affect the calculation. A logic element that uniformly performs a calculation can be used as the logic operation execution unit AE. That is, for the above functions (a) to (c), 8
Wide Gate 16 to 18 that inputs all bits are connected, and the function (d) is NOT Gate to all 8 bits.
19 is connected. Further, since the above functions (a) to (c) output 1 bit, this is branched into 8 bits.

The four types of logical operation results output from the logical operation executing unit AE are input to the output side masking circuit OM for each bit position. The task of the output side masking circuit OM is to write EN indicating whether each bit is valid or invalid.
This is to set and output the enable and the calculation result of the designated function.

FIG. 3 is a diagram showing the configuration of the 8-bit output side masking circuit OM in the above embodiment.

The Write Enable outputs "1" when the input side masking information is valid "1",
When it is invalid "0", "0" is output. Therefore, the masking information 14 on the output side is directly written.
It may be in the Enable state. 4-input 1-output selectors SO0, SO1, SO2, SO3, SO4 for each bit,
The selection operation in each of SO5, SO6, and SO7 follows the following condition determination sequences ~. Condition determination sequence: When the ALL AND 36 is "1", the terminal 32 is selected. That is, Wid
The result of the e-AND element is selected and output.・ Condition judgment sequence: All OR37 is "1"
In the case of, the terminal 33 is selected. That is, Wide-
The result of the OR element is selected and output. Condition determination sequence: When the ALL XOR 38 is "1", the terminal 34 is selected. That is, Wid
The result of the e-XOR element is selected and output. -Condition determination sequence: When All NOT 39 is "1", the terminal 35 is selected. That is, NOT
Select and output the result of the device.

The above-mentioned condition judging sequences can be easily realized by the wiring logic using the logic elements. That is, each of the 4-input / 1-output selectors SO0 to SO7 can be easily realized by the wiring logic using the logic elements.

According to the above-described embodiment, since the input side masking circuit IM extracts the bit information at an arbitrary position from the n-bit data input from the input port, the input side masking is performed. It is possible to generate bit data in any combination depending on the mask information set in the circuit IM.

The bit data generated here is
By inputting to the logical operation execution unit AE that supports only the inter-bit arithmetic function specific to the process to be applied, the target result of the inter-bit logical operation can be obtained with a small-scale hardware.

Further, as for the m-bit result output from the logical operation executing unit AE, the output side masking circuit OM extracts the bit information at an arbitrary position and outputs it to the output port. Depending on the mask information set in the side masking circuit OM, it is possible to output the operation result only to the desired bit position or perform the filtering process on the processing result.

Further, the latch circuit provided between each port on the input side / output side and each masking circuit IM, OM allows the input data and the output data to be input for a necessary period.
By keeping the inside of the logical operation unit, it is possible to perform a plurality of consecutive bit-to-bit arithmetic processing on the same data, a packing processing of a plurality of processing results into m-bit data, and the like.

FIG. 4 is a scramble pattern generation circuit SP for generating a scramble pattern to be combined with transmission data in the scramble processing of the digital communication system.
FIG. 4 is a diagram illustrating that can be realized by an embodiment configured with a functional circuit including the logical operation unit according to claim 3.

Here, "scramble" is a process of converting the transmitted bit string into a random pattern,
The generator polynomial of the scramble pattern is represented by X ⁷ + X ⁶ +1. That is, the scramble pattern at time t of the serial data is the pattern at time t-7,
It is calculated by exclusive OR with the pattern at time t-6. The scramble pattern when the serial data is parallel expanded to 8 bits can be calculated from the following formula.

The pattern at the x-bit position at time t is
If Dx (t), D7 (t) = D6 (t-1) xor D5 (t-1) D6 (t) = D5 (t-1) xor D4 (t-1) D5 (t) = D4 ( t-1) xor D3 (t-1) D4 (t) = D3 (t-1) xor D2 (t-1) D3 (t) = D2 (t-1) xor D1 (t-1) D2 (t ) = D1 (t-1) xor D0 (t-1) D1 (t) = D7 (t-1) xor D5 (t-1) D0 (t) = D6 (t-1) xor D4 (t-1) ) Is.

Here, a method of deriving the above D1 (t) and D0 (t) will be described. Generally, the scramble pattern at time t is calculated by the exclusive OR of the scramble pattern at time t−1 and the scramble pattern at time t−6, so D1 (t) = D0 (t−
1) xor D7 (t) and D0 (t-1) xor D
7 (t) = {D7 (t-1) xor D6 (t-1)} xo
r {D6 (t-1) xor D5 (t-1)} = D7
(T-1) xor D5 (t-1). Therefore,
As described above, D1 (t) = D7 (t-1) xor D5 (t-1). Also, D0 (t) = D7 (t) xor D6
(T), and D7 (t) xor D6 (t) = {D6
(T-1) xor D5 (t-1)} xor {D5 (t-
1) xor D4 (t-1)} = D6 (t-1) xor D
4 (t-1). Therefore, as described above, D0 (t) = D6 (t-1) xor D4 (t-1).

That is, the scramble pattern of each bit at the current time can be entirely calculated by the bitwise exclusive OR operation of the 8-bit scramble pattern at the previous time.

Next, a method of implementing the scramble pattern generation circuit SP will be described.

The scramble pattern generation circuit SP is a kind of logical operation unit and is composed of functional circuits 41 to 48. That is, the scramble pattern generation circuit SP
Is a branch circuit for branching n-bit data input from the input port into m sets, and m sets of the logical operation units (m sets of n-bit data output from the branch circuit, respectively). An 8-bit input 8-bit output function circuit FC1) and a pack circuit for bundling the 1-bit operation results output from each of the m sets of logical operation units and packing them into an m-bit width,
This is a logical operation unit that performs parallel processing by assigning the above-mentioned independent logical operation unit to each bit of output data.

Each of the functional circuits 41 to 48 in which the arithmetic units are arranged in parallel so that the scramble pattern at each bit position can be calculated simultaneously, has the 8-bit input 8-bit output functional circuit FC1 described with reference to FIGS. 1, 2 and 3. Is the same as.

By referring to the calculation formula of the 8-bit parallel scramble pattern, "1" is set in the bit position necessary for the calculation in the input side mask information 12. Further, "10" is set as the function designation information 15, and the exclusive OR operation between valid bits is designated. Output side mask information 1 so that the operation result at the x-bit position is output at the x-bit position.
Set 4. However, when the scramble pattern generation circuit SP shown in FIG. 4 is used as a scramble pattern generation circuit (not used as a multi-function arithmetic unit set), only exclusive OR is set as the function function,
The function designation information 15 may be omitted. Also,
Since the bit width m of the output data is 1, the output side mask information 14 can also be omitted.

If a circuit for extracting only 1 bit that is Write Enable from the 8-bit data output from the output side masking circuit OM is added to the 8-bit input 8-bit output function circuit FC1, scramble pattern generation is performed. The functional circuits 41 to 48 in the circuit SP can be created. Here, the above Write Enab
A circuit for extracting only 1 bit that is le can be easily realized by combining logic elements.

Scramble pattern generation circuit S shown in FIG.
In P, the input side latch and the output side latch are made common so that the scramble pattern at the current time can be supplied as calculation target data at the next time. For practical use, another circuit for initializing the scramble pattern is required.

According to the scramble pattern generation circuit SP, the same number of operation units as the number of bits to be output are prepared, and the operation for each bit is independently and simultaneously processed, so that the common input data can be used for a plurality of bit patterns. The processing time is shortened when the calculation is performed and the data is output to different bit positions.

In each of the above embodiments, the n-bit data input port and the n-bit input side masking circuit are directly connected, but the n-bit data input port and the n-bit data input port are connected.
An n-bit input-side latch that holds n-bit data may be provided between the bit input-side masking circuit. By providing the n-bit input-side latch in this way, it is possible to execute a plurality of clocks for the same data. When the above embodiment is used as a multifunctional circuit, it is not always necessary to provide an n-bit input side latch, but if an n-bit input side latch is not provided,
It is necessary to input data from the input port every time calculation is performed.

Also on the data output side, as in the case of the data input side, the latch may be omitted or the latch may be provided.

FIG. 5 is a block diagram showing the inter-processor logical operation unit AU in the above embodiment, and is a block diagram showing the inter-processor logical operation unit including the logical operation unit according to claim 2. .

Inter-bit logical operation unit A for processor
U has input side latches R _A and R _B , an input side masking circuit IM2, a logical operation execution unit AE2, an output side masking circuit OM2, and an output side latch R _C.

That is, in the inter-bit logical operation unit AU for processor, the set of the n-bit input side latch and the n-bit input side masking circuit is divided into a plurality of ports, latches and masking circuits with an arbitrary bit width. It is a logical operation unit that not only performs bit-to-bit operations within a single input data, but also performs bit-to-bit operations of arbitrary combinations between a plurality of arbitrary bit width input data.

Inter-bit logical operation unit A for processor
In U, the total bit width n of the input data is 16, and this is divided into 2 ports of 8 bits + 8 bits, and the bit width m of the output data is 8. Therefore, the input side latch R _A , the input side latch R _B ,
The bit widths of the input side mask information 51, the input side mask information 52, the output side latch _RC and the mask information 54 are
All are 8.

The inter-bit operation functions provided in the logic operation execution unit AE2 are the same as the inter-bit operation functions described in the 8-bit input 8-bit output function circuit FC1 shown in FIG. 1 (the logical product of all effective bits). , Logical sum, exclusive logical sum, logical negation of each valid bit). Therefore, the bit width of the function designation information 53 in the logical operation executing unit AE2 is 2.

The 8-bit input 8-bit output function circuit FC1 described with reference to FIGS. 1, 2, and 3 can be expanded to realize the processor inter-bit logical operation unit AU. That is, 8-bit latches R _A and R _B are provided, and two sets of input side masking circuits IM shown in FIG. 2 are prepared.
The input masking circuit IM2 is configured by these two sets of input side masking circuits IM, and the logical operation executing unit A shown in FIG. 1 is provided so as to correspond to the bit signal input 58 of 16 bits in total output from the input masking circuit IM2.
A logical operation execution unit AE2 is obtained by changing each logic element 16, 17, 18, 19 in E, and an 8-bit latch _RC is added to the output side masking circuit OM.
In this way, the processor inter-bit logical operation unit AU is configured.

To implement the arithmetic unit AU shown in FIG. 5 on the data path of the processor, two 8-bit + 8-bit input ports are connected to the two source buses of the data path, and the 8-bit output port is connected to the destination. Just connect to the bus. All the control of the arithmetic unit AU is executed by a control signal from the control unit or the instruction decoding unit of the processor.

Each latch R _A , R _B , R _C can be designated by a program like other general-purpose registers. In order to make the arithmetic unit AU programmable, the code format (opcode) of the instruction is expanded.

According to the multi-input logical operation unit AU,
By providing a plurality of sets of the input port, the input side latch, and the input side masking circuit, it is possible to perform an arbitrary inter-bit logical operation between a plurality of independent data. Further, since a plurality of calculation target data are treated independently, it is not necessary to input fixed data each time when performing an inter-bit logical operation between new data and fixed data.

FIG. 6 is a diagram showing an example of a code format (operation code) of an instruction for program controlling the inter-bit logical operation unit AU for a processor.

In FIG. 6, "Normal Operation"
The format indicated by "type instruction" represents a typical operation code of register-register ALU operation in a general-purpose processor. That is, data is read from each of the register designated by the latch R _A allocation source 62 and the register designated by the latch R _B allocation source 63, and they are input to the ALU, and the Operator is set.
The operation for performing the operation designated by 61 and the Function 65 and writing the result back to the register designated by the latch _RC allocation source 64 is instructed.

This time, the operation code of this format is also used for register-register transfer between a general-purpose register and a register in the processor inter-bit logical operation unit AU. That is, the latch _RA assignment source 6
The data of the register specified by 2, the latch is transferred to the R _A, latch R _B data register specified by the assignment source 63, the latch R transferred to _B, the latch latching the R _C data R _C assignment source 64 The opcode of the above format is used to instruct the transfer operation to the register specified by.

At this time, Operator 61 and Fu
The type of transfer is designated by the action 65.
For example, it is an instruction to instruct only the transfer relating to the latch R _A and the latch R _C and prohibit the data transfer to the latch R _B. By preparing an instruction to perform such independent control for each port, it becomes possible to fix some of the prepared input ports for holding constants or for holding internal states.

The input side mask information 51, 52, the output side mask information 54, and the function designation information 53 set in the inter-bit logical operation correspondence unit AU are "Bit" in FIG.
The value is set using a new format indicated by "Operation type instruction". That is, Mask.In.166
Specify the input side mask information 51, Mask.In.2 67
The input side information 52 is designated, Mask.Out 68 designates the output side mask information 54, and the BF 69 is a region for designating the function designation information 53.

In the column of Operator 610, a flag indicating the continuation / completion of the operation is given in addition to the flag clearly indicating the operation code for the unit corresponding to the inter-bit logical operation. This is to make it possible to distinguish it from the operation code for the other arithmetic logic operation unit and to enable the repeated execution of the logic operation for the same bit data (data loaded in the input side latches R _A and R _B ). It is a measure.

In response to a request for arbitrary bit-to-bit logical operation processing, the processing is performed in the following sequence using the processor bit-to-bit logical operation unit AU shown in FIG. 5 and the operation code of the format shown in FIG. To be realized.

Processing Sequence ': "Normal Op" in FIG.
An operation code of the "eration type instruction" is used to connect between each latch inside the unit and the general-purpose register. At this time, for the latches R _A and R _B , data transfer from the registers is immediately performed, but for the latch R _C , the data transfer is suspended while the connection with the transfer destination register is secured.

Processing Sequence ': "Bit" in FIG.
An operation code of the "Operation type instruction" format is used to perform set & operation execution for each mask information and function designation information inside the unit. This operation is called Opera
Repeated only while the operation continuation / completion flag in the tor column indicates continuation, and when the completion flag is detected, the latch R held in the above processing sequence 'is completed after completing the operation specified by the operation code at that time. Data transfer of _C is performed, and a series of bit-to-bit operations is completed.

By combining the processor inter-bit logical operation unit AU described with reference to FIG. 5 and the operation code illustrated in FIG. 6, the inter-bit operation processing between the transmission signal frequently occurring in the communication processing and the internal state is performed. It becomes possible to perform at high speed by the processor of the storage program processing method.

In each of the above-described embodiments, the logic operation execution unit AE that defines the inter-bit logic operation function is provided with a required logic circuit and its selection mechanism by a custom LSI or a mask programmable gate array, and the circuit is executed at the time of execution. Depending on the selected configuration, it is possible to provide a logical operation unit that fully corresponds to a desired function with a minimum of birdware resources.

Furthermore, if a field programmable device is used as a means for realizing the logic circuit and the necessary logic circuit is user-programmed before the processing is executed, it is extremely flexible to realize all the logic operation functions immediately in the field. It is possible to provide a high logic operation unit. In any case, since the function change during processing is performed by n + m bits of the mask information and a memory of several bits for indicating the selection state of the circuit or a plurality of sets thereof, the function can be changed at high speed.

Further, in each of the above-described embodiments, the program is incorporated into the data bus of the storage program processing system, and each unit is controlled by giving each masking information and function designation information by the program to control the unique word width of the processor. Flexible bit-to-bit arithmetic that is not restricted by constraints becomes possible. Therefore, even in the bit-to-bit operation that conventionally requires the shift processing of the source data, the operation can be performed directly by the mask information included in the operation code, and the number of clocks consumed can be significantly reduced.

[0077]

According to the invention described in claim 1, between bits
Outputs the result of logical operation (1 bit) to 1 output bit
Can be any or any of several bits
It is possible to output to the output bit at the position of . According to the second aspect of the invention,
Hardware resources to fully support desired functions
It is possible to provide an arithmetic unit and
The functions can be changed and the
Flexible bit-wise operation that is not restricted by the existing word width constraint
It is therefore possible to
Opcodes even for bit-to-bit operations that required soft processing
It is possible to calculate directly with the mask information included in
It is possible to reduce the number of clocks consumed
Has the effect of

[Brief description of drawings]

1 is a block diagram showing an 8-bit input 8-bit output function circuit FC1 which is an embodiment of the present invention;
3 is a block diagram showing a functional circuit including the logical operation unit described in FIG.

FIG. 2 is a configuration diagram of an 8-bit input side masking circuit IM in the above embodiment.

FIG. 3 is a configuration diagram of an 8-bit output side masking circuit OM in the above embodiment.

FIG. 4 is a diagram showing a scramble pattern generation circuit SP for generating a scramble pattern to be combined with transmission data in a scramble process of a digital communication system, which is composed of a functional circuit including a logical operation unit according to claim 3; It is a figure explaining what can be implement | achieved in an Example.

FIG. 5 is a block diagram showing a processor inter-bit logical operation unit AU in the above embodiment, and is a block diagram showing a processor inter-bit logical operation unit including the logical operation unit according to claim 2;

FIG. 6 is a diagram showing an example of a code format (opcode) of an instruction for program-controlling a processor inter-bit logical operation unit AU.

[Explanation of symbols]

FC1 ... 8-bit input 8-bit output function circuit, 11 ... Input port, 12 ... Input side mask information, 13 ... Output port, 14 ... Output side mask information, 15 ... Function designation information, 16 ... Wide-AND Gate, 17 ... Wide-OR Gate, 18 ... Wide-SOR Gate, 19 ... NOT Gate, IM, IM2 ... Input side masking circuit, AE, AE2 ... Logical operation executing section, OM ... Output side masking circuit, SI0-SI7 ... 4 input 1 output selector, SO0~SO7 ... 4-input 1-output selector, SP ... scramble pattern generating circuit, AU ... bit between logic unit processor, R _A, R _B ... input latch, A _C ... output latch.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-4-312118 (JP, A) JP-A-3-129425 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 9/305 G06F 7/00

Claims (6)

(57) [Claims] 1. The bit to be invalidated based on the information of valid / invalid set for each bit for n-bit data input to the n-bit data input port.
Change the value of the bit to a value that does not affect the bit-to-bit logical operation.
An n-bit masking circuit on the input side , the value of which is controlled by the masking circuit on the input side.
M output from the logic operation execution unit; logic operation execution unit and an n-bit input m-bit output you m branching the output of the arithmetic operation performs logical operation between the bit for outputting the 1-bit to input over data for bit output, the output-side masking circuit and the m-bit to enable / disable for each bit; m-bit data to output only data of the valid and set bit positions in the output-side masking circuit units outside A logical operation characterized by having an output port and; performing an arbitrary combination of bit-to-bit logical operations from input n-bit data and outputting to one or more arbitrary bit positions of m bits. unit. 2. A logical operation function type and function specifying unit that specifies, for n-bit n-bit data inputted to the data input port, a logical operation function <br/> several information inputted from the function specifying unit When the input side of the n bits to be changed to a value based on the information should be enabled / disabled, which is set for each bit, the influence of the value of the bit to be invalidated in the calculation of the logic operation function type does not appear and masking circuit; bit between logic operation for outputting the 1-bit type n-bit data controlled values in the input-side masking circuit
N-bit input for performing and branching the output of the operation concerned
The above-mentioned function is designated as the logical operation function executing means of m-bit output.
Multiple corresponding to the types of logical operation functions that can be specified by the section
Logic operation execution unit including type and; for m bits output from each logic operation function executing means of the logic operation execution unit, a logical operation corresponding to the logical operation function type of information that is input from the upper Symbol function specifying unit select the output of the function executing unit, based on whether the information should be enabled / disabled, which is set for each bit, a selected said logic
Outputs only data of the valid and set bit positions in the output-side masking circuit units outside; and an output-side masking circuit of m bits are used to set the validity / invalidity of respective bits of the m-bit output of the arithmetic function executing means and an m-bit data output port, which performs an arbitrary combination of bit-to-bit logical operations from input n-bit data and outputs the result to one or more arbitrary bit positions of the m bits. And a logical operation unit. 3. The structure according to claim 1 or 2, wherein the set of the n-bit data input port and the n-bit input side masking circuit is divided into a plurality of ports and masking circuits with an arbitrary bit width. Therefore, not only bit-to-bit arithmetic within a single input data, but also bit-to-bit theory of arbitrary combinations between multiple arbitrary bit-width input data
Logical operation unit and performing management operations. 4. The n-bit data holding port according to claim 1, wherein the n-bit data is held between the n-bit data input port and the n-bit input side masking circuit. A logical operation unit having an input side latch. 5. The method according to any one of claims 1 to 4.
There are, of the output-side masking circuit and m bits of the m-bit data
Output mastine between the output port and
Of the data at the bit position set to be valid in the
It has an m-bit output side latch that holds only
A logical operation unit to collect. 6. The method according to any one of claims 1 to 5.
A logical performance with m sets of the listed logical operation units
In an arithmetic unit , n-bit data input from the outside is branched into m sets
Then, the n-bit data is converted into the m sets of logical operation units.
A branching circuit for supplying to each of the m sets of logical operation units ; a packing circuit for bundling the 1-bit operation results output from each of the m sets of logical operation units into a m-bit width and outputting m-bit data to the outside. When; has, for each bit of the output data of m bits to be output to the outside allocation independent of the arithmetic logic unit, arithmetic logic unit, which comprises carrying out parallel processing.