JP3533365B2 - Solid-state imaging device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device for converting an incident light image into a digital video signal and outputting the digital video signal.
In particular, the present invention realizes a higher output data rate of a CMOS image sensor equipped with a column-parallel AD converter.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram for explaining a conventional CMOS image sensor equipped with a column-parallel type AD converter. AD converter 11 for one row
1, 112 to 11 m perform AD conversion on the output of one row of the pixels 121, 122 to 12 m all at once, and the output is the output of the shift register 14 and the output switches 151, 152 to 15
It is output as a digital video signal from the output amplifiers 191, 192 to 19n connected to the output signal lines 181, 182 to 18n via n.

Next row of pixels 131, 132 to 13 m
Is also converted by the AD converters 111, 112 to 11n and output as digital video signals from the output amplifiers 191, 192 to 19n.

Similarly, each row is sequentially AD-converted and output as digital video signals from the output amplifiers 191, 192 to 19n. The result of AD conversion needs to be held for a period of outputting a digital video signal for one row. However, by providing a latch at the output of the AD converter, the AD conversion time is up to the signal output period for one row. Can be stretched.

By the way, the data rate of the output digital video signal is determined by the clock driver 20 and the shift register 1.
4 and the delay time of the selection switches 151, 152 to 15n. Selection switches 151, 152-
15n connected output signal lines 181, 182-1
A parasitic capacitance of 8n particularly limited its speed. Also,
In order to improve the operation speed, it is necessary to increase the power supply voltage, which causes a problem that the power consumption increases beyond the improvement rate of the data rate.

A method of improving the data rate of the output digital video signal has also been considered. FIG. 10 shows a conventional method for improving the data rate. For the sake of clarity, only the output signal line corresponding to 181 in FIG. 9 and the selection switch for selecting the outputs of the AD converters 111, 112 to 11n by the shift register 14 are shown.

That is, the output signal line corresponding to the output signal line 181 is a plurality of output signal lines 181a and 181b, and a plurality of pieces of pixel information AD-converted by the AD converters 111 and 112 are simultaneously output. is there. By selectively outputting this output by the selection circuit MUX, the operating speed can be improved.

However, there is a problem in that the number of output signal lines increases, the wiring area increases, and the chip size increases. In addition, there is a problem that the power consumption increases because the parasitic capacitance of the total wiring also increases.

[0009]

In the above-mentioned conventional solid-state image pickup device, although a plurality of output signal lines are provided and information of a plurality of pixels is output at the same time, the data rate of the output digital video signal can be improved. There are problems that power consumption increases and chip size increases.

It is an object of the present invention to provide a solid-state image pickup device which realizes a high output data rate and low power consumption of a CMOS image sensor equipped with a column-parallel AD converter.

[0011]

In order to solve the above problems, according to the present invention, a plurality of pixels for converting the amount of incident light into electric signals and an analog signal obtained from the plurality of pixels are converted into digital signals. In a solid-state imaging device for scanning and outputting, each bit of a digital signal obtained from the pixel is converted into a multivalued signal for each of a plurality of adjacent pixels, and digital signals of a plurality of pixels are sequentially selected from the obtained multivalued signal. The feature is that the value is restored and output.

By the above-mentioned means, it is possible to reduce the signal output rate by converting into a multi-valued signal for each of a plurality of adjacent pixels, the number of wirings does not increase, and the total number of selection switches is also reduced to half. It is possible to reduce power consumption.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram for explaining a first embodiment of the present invention. The same components as those in FIG. 10 are designated by the same reference numerals, and different components are mainly shown here. explain.

In FIG. 1, the output signal of the pixel is supplied to the AD converters 111 and 112 to 11n, where it is converted into a digital signal. DA converters 211, 212-2
1n is a 4-bit value of “00”, “01”, “10”, “11” in which signals of the same bit of two adjacent pixels 121 and 122 on the same row are input, and information for two pixels is entered. It outputs the corresponding analog signal voltage.

FIG. 2 shows a concrete example of the configuration of this AD converter. The buffer amplifiers BA1 and BA2 output the power supply VHH or VLL according to the input logical value. The resistance value of the resistor R2 is twice the resistance value of the resistor R1.
VLL when the input signal voltage supplied to is “00”,
In the case of “01”, (2VLL + VHH) / 3, in the case of “10” (VLL + 2VHH) / 3, and in the case of “11”, four-valued analog voltages of VHH are output.

As a result, the selection switches 151, 152
The output voltage selected in ˜15n is output signal line 181,1
82 to 18n. Selection switch 151,15
2 to 15n are four-valued DA converters 211, 212 to 21
The output signal lines 181, 18 are controlled by controlling the output of each of n based on the output of the shift register 14.
2, 18n, and AD converters 231, 232-23
n respectively.

Similarly, the DA converters 221 and 222 to 22n respectively input the signals of the same bit of the adjacent two pixels 123 and 124 in the same row and have "00" and "00" having information for two pixels. The analog signal voltages corresponding to the four values of 01 ”,“ 10 ”, and“ 11 ”are output, and the bit data of 2 pixels are reproduced and output from these four-valued analog signals. Then, the output voltage from the DA converter selected by the selection switches 161, 162 to 16n is output to the output signal line 1
81, 182 to 18n. Selection switch 16
1, 162 to 16n are four-valued DA converters 221 and 22
The outputs of 2 to 22n are controlled by the output of the shift register 14, output from the output signal lines 181, 182 to 18n, and supplied to the AD converters 231, 232 to 23n, respectively.

An example of the configuration of the AD converters 231, 232 to 23n is shown in FIG. Each of the three voltage comparators VC1 to VC3 is (5VLL + VH) by the resistance voltage dividing shown in the figure.
H) / 6, (VLL + VHH) / 2, (VLL + 5VHH) / 6
3 voltages are being supplied. These three voltages are the DA of FIG.
It is the midpoint voltage between the four levels output by the converter. Therefore, the outputs of the voltage comparators VC1 to VC3 can be encoded to reproduce the bit information for two pixels.

As described above, the signal output rate to each output signal line can be reduced to 1/2, and the total number of selection switches can be reduced to half without increasing the number of wirings. This can reduce power consumption. Also, 2 at the same time
Since the pixel information can be obtained, for example, in the case of a 2 × 2 pixel cycle color filter such as the Bayer array color filter shown by the suffix in the light receiving diode in each pixel in FIG. It is possible to obtain at the same time.

FIG. 4 is a block diagram for explaining the second embodiment of the present invention. The same components as those in FIG. 1 are designated by the same reference numerals.

In this embodiment, DA converters 211 and 211 are used.
At 12 to 21 m, information for 4 pixels is multiplexed,
This is different from the configuration of FIG. 1 in that the AD converters 231, 232 to 23n separate the information for four pixels and output the information at each pixel timing.

By the way, when the number of input bits of the DA converter increases, the interval of the multi-level voltage decreases, so that DA
The accuracy of the converter and the AD converter in the subsequent stage becomes an issue. D that determines the analog value by the resistance ratio as shown in FIG.
When the A converter is composed of a CMOS circuit, it is difficult to achieve high accuracy because the ON resistance of the switch changes depending on the bias voltage, temperature and manufacturing variations. The ON resistance of the switch is unlikely to affect the accuracy, and can be realized by the switched capacitor circuit as shown in FIG.

FIG. 6 is a timing chart for explaining the operation of the DA converter shown in FIG. Capacitors C1 and C
2 have the same shape and have the same capacitance. First, prior to DA conversion, the switch Sr is closed to discharge the electric charges of the capacitors C1 and C2. Open the switch Sdac,
After the switch S1 is closed and the information voltage of the least significant bit is stored in the capacitor C1, the switch S1 is opened and the switch S1 is opened.
The dac is closed and the charges stored in the capacitors C1 and C2 are averaged (D0 / 2). Next, the switch Sdac is opened, the switch S2 is closed and one bit of information is stored in the capacitor C1, and then the switch S2 is opened and the switch Sdac is closed. Analog voltage (2D1 + D
0/4) is obtained.

Thereafter, in the same manner, the switches S3, Sda
By repeating desired opening and closing in the order of c, S4, and Sdac, it is possible to generate a DA-converted voltage of a 4-bit digital value. This voltage is buffered by the buffer amplifier 501 having a gain of 1 and output as (Vmix + Vof) to the output signal line Vo via the selection switch SELn.

Here, Vof is an offset voltage between the input and output of the buffer amplifier 501. Select switch SELn
When the switch Sr is closed and the electric charges of the capacitors C1 and C2 are discharged when is selected, the offset voltage Vof is output to the output signal line Vo. If the potential change at this time is detected, the offset of the buffer amplifier 501 is detected. The voltage can be canceled, and information of a plurality of pixels can be reproduced from the multi-valued level without error. This is because the coupling capacitor 502 and the clamp switch 503 clamp the signal line voltage at the timing of the CP pulse, and the sample hold circuit 504 samples and holds the voltage change amount at the time of discharge, and the influence of the offset voltage of the buffer amplifier 501. By inputting a non-existent signal to the AD converter, a multi-bit multiplexed signal can be reproduced without error.

FIG. 7 shows a successive approximation type AD conversion circuit which directly outputs a bit signal for each pixel from a multi-valued level signal corresponding to the multi-pixel multiple bit signal shown in FIG.
Will be described together with the timing chart of FIG.

The shift register 701 is connected to the STRT terminal.
D flip-flops 7011 to 7014 are set to 0. All of the SR flip-flops 7021 to 7024 are set to 1 by the SETP pulse, and D
The maximum value output of the DA converter is output from the A converter 703. The DA converter 703 uses a (multiplexed bit number + 1) bit resolution and inputs 1 to the least significant bit at the time of clamping and sets it to 0 at the time of voltage comparison.
It can be compared with the median voltage of the multiplexed signal level.

After the multilevel signal voltage IN input through the coupling capacitor 704 is clamped by the clamp switch 705, the reset switch Sr of the multilevel DA converter shown in FIG. 5 is closed to output 0 level. The inverting input terminal voltage of the voltage comparator 706 changes like the dotted line waveform of VDAC shown in FIG. Shift register clock SR
When CK enters, the first stage D flip-flop 7011 of the shift register 701 is set to 1, and the AND gate 70
The output of 81 becomes 0 level, the output voltage of the DA converter 703 decreases, and this change amount is compared with the change amount of the input voltage.

At this time, if the change of the input voltage is larger, the output of the DA converter 703 has a larger value, so that the output of the voltage comparator 706 becomes high level. Voltage comparator 7
If the output of 06 is high level, only the AND gate 7071 of the bit currently being compared when the reset pulse RSTP for the SR flip-flop circuit is input resets the SR flip-flop circuit 7021.

On the contrary, if the change in the output of the DA converter 703 is larger, the output of the voltage comparator 706 becomes low level, the AND gate 7070 containing the RSTP signal does not output a pulse, and the SR flip-flop circuit. 7021 maintains the same value. When the SRCK pulse is input, the bit having the next largest weight is compared, and the DA converter 703 that sequentially approximates the input signal voltage outputs the output. The output of the voltage comparator 706 is sampled by the determination pulse RSTP and serially output from the D-type flip-flop 709 from the most significant bit, so that a digital video signal for each pixel can be output.

In this embodiment, the DA converter of FIG.
By using the AD converter shown in FIG. 7, it is possible to cope with multi-level input. Therefore, since the number of input bits of the DA converter can be increased and the voltage interval can be reduced to a multilevel level, it is possible to realize accurate conversion into an analog voltage.

The present invention is not limited to the above-described embodiment, and an example of 2 or 4 pixels has been described as an example of multiplexing a plurality of adjacent pixels. Is also possible.

[0034]

As described above, according to the solid-state image pickup device of the present invention, the signal outputs of a plurality of pixels can be obtained at the same time without increasing the number of output signal lines. A high output data rate can be obtained. Further, since the number of selection switches connected to the signal line is also reduced, parasitic capacitance is reduced and power consumption is also reduced.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining a first embodiment of the present invention.

FIG. 2 is a block diagram for explaining a specific example of the DA converter shown in FIG.

FIG. 3 is a block diagram for explaining a specific example of the AD converter in FIG.

FIG. 4 is a block diagram for explaining a second embodiment of the present invention.

5 is a block diagram for explaining a specific example of the DA converter shown in FIG.

FIG. 6 is a timing chart for explaining the operation of FIG.

7 is a block diagram illustrating a specific example of the AD converter in FIG.

8 is a timing chart for explaining the operation of FIG.

FIG. 9 is a CMO equipped with a conventional column-parallel AD converter.
The block block diagram of an S image sensor.

FIG. 10 is a block diagram for explaining a conventional speed-up method.

[Explanation of symbols]

111, 112-11m, 231, 232-23n ... A
D converters 121, 122 to 12m, 131, 132 to 13m ... Pixel 14 ... Shift registers 151, 152-15n, 161, 162-16n ... Selection switch 181, 182-18n ... Output signal line 20 ... Clock drivers 211, 213 -21n ... DA converter

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/30-5/335 H01L 27/14

Claims (4)

(57) [Claims] 1. A solid-state imaging device, comprising: a plurality of pixels that convert an amount of incident light into an electric signal; and an analog signal obtained from the plurality of pixels that is converted into a digital signal for scanning output. The solid-state imaging device is characterized in that each bit is converted into a multi-valued signal for each of a plurality of adjacent pixels, and digital values of the plurality of pixels are restored and output from the multi-valued signal obtained by sequential selection. 2. When restoring and outputting a digital value,
The solid-state image pickup device according to claim 1, further comprising means for scanning the restored digital value, and outputting the pixel value as a continuous pixel digital signal. 3. The solid-state imaging device according to claim 1, wherein the digital value is restored and simultaneously output. 4. A serial output type A for sequentially deciding a digital value from the upper bits as means for scanning the digital value.
The solid-state imaging device according to claim 2, wherein the solid-state imaging device is D conversion.