JP3528927B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention applies a discharge to a match line which has been precharged by a matching circuit provided for each memory cell forming a memory matrix for storing data of a word length M with a bit length N. In the semiconductor memory device, it is possible to obtain the matching result between the search word data of the bit pattern input to the bit line and the stored word data of the bit pattern stored in the word row of the memory matrix by detecting whether or not Staff, especially,
The present invention relates to a semiconductor memory device capable of reducing the load on a power supply line due to a large current and reducing the intensity of power supply noise by reducing the peak maximum current flowing through the power supply line during a search operation.

[0002]

2. Description of the Related Art In recent years, digital circuit technology has come to be used in various fields due to various design technologies such as improvement in the degree of integration and design of logic circuits to be incorporated. In such digital circuit technology, CPU (centra
l processing unit) and other data processing, etc., as well as semiconductor memory devices such as RAM (random access memory) and external memory devices such as hard disk devices. Advances have been made and are being used in various fields.

For example, in data processing in a database, various signal processing and image processing, a large amount of data is often handled during the processing, and the number of accesses to the data being processed tends to increase. For example,
In the data processing in the database, the data stored in the semiconductor memory device is frequently searched for. Therefore, in a digital processing device that performs such processing, the configuration and performance of the storage device itself and the method of using the storage device have a great influence on the performance of the entire digital processing device.

For this reason, the semiconductor memory device itself, which is provided with a data search function that is frequently performed in data processing in a database, has been widely used in recent years. This semiconductor memory device detects whether a precharged match line has been discharged by a matching circuit provided for each memory cell forming a memory matrix that stores data of a word length M with a bit length N. Then, the collation result of the search data of the bit pattern input to the bit line and the stored word data of the bit pattern stored in the word row of the memory matrix is obtained. Or later,
Such a semiconductor memory device is called a semiconductor memory device with a search function.

FIG. 8 is a circuit diagram of a memory matrix of the semiconductor memory device with a search function which has been conventionally used.

The memory matrix of the semiconductor memory device with a search function shown in FIG. 8 has a bit length N and a word number M.
The data of is stored. Therefore, a total of (M × N) memory cells M11 to MMN that store 1-bit bit data are used. Each of the memory cells M11 to MMN has a bit line pair Bn and (Bn
Bar), word line Wm, and search enable line ENm
And the match line MCHm is input or output.

Further, such memory cells M11 to MMN
Are arranged in a matrix as shown in the drawing, and the word lines Wm, the search enable lines ENm, and the match lines MCHm are common to the N word lines in total. Further, the bit line pairs Bn and (Bn bar) are common to all of the same M bit strings.

FIG. 9 is a circuit diagram of a memory cell used in the conventional semiconductor memory device with a search function.

The memory cell shown in FIG. 9 is one of the memory cells M11 to MMN used in the semiconductor memory device with a search function shown in FIG.
It is called). The memory cell M includes a total of two inverter gates I1 and I2 and a total of six N-channels M.
It is composed of OS transistors T1 to T6.

First, the inverter gates I1 and I2
Are connected to each other so that one output is connected to the other output to hold bit data. Also, the N
The gates of the channel MOS transistors T1 and T2 are connected to the word line Wm. The N
The gates of the channel MOS transistors T4 and T6 are connected to the search enable line ENm. The gate of the N-channel MOS transistor T3 is connected to the input side of the inverter gate I1. The gate of the N-channel MOS transistor T5 is connected to the output of the inverter gate I1.

In the memory cell M as described above, first, when writing bit data, the word line Wm is written.
To the H state. As a result, the N-channel MOS
Both the transistors T1 and T2 are turned on. At the same time, by inputting bit data to be written from the bit line pair Bn and (Bn bar), this can be held by the inverter gates I1 and I2.

When reading the bit data held in the memory cell M, the word line Wm is set to the H state. As a result, the N-channel MOS transistors T1 and T2 are both turned on, and the held bit data can be read from the bit line pair Bn and (Bn bar).

Regarding the inverter gates I1 and I2 of the memory cell as shown in FIG. 9, the bit line Bn side, that is, the input of the inverter gate I1 is held in the H state, and the bit line ( Bn bar)
When the side, that is, the output of the inverter gate I1 is held in the L state, such a state is hereinafter referred to as "the H state (" 1 ") is held in the inverter gates I1 and I2". . This is because the bit lines Bn side of the inverter gates I1 and I2 is in the H state. On the other hand, regarding the inverter gates I1 and I2, when the bit line Bn side is held in the L state and the bit line (Bn bar) side is held in the H state, such a state will be referred to as “the inverter The L state (“0”) is held in the gates I1 and I2. ”

The bit line pair Bn and (Bn bar)
With respect to the above, the state in which the bit line Bn is in the H state and the bit line (Bn bar) is in the L state is described below.
This is called "the bit line pair Bn and (Bn bar) is in the H state". This is because the bit line Bn is in the H state for the bit line pair Bn and (Bn bar). On the other hand, regarding the bit line pair Bn and (Bn bar), when the bit line Bn is in the L state and the bit line (Bn bar) is in the H state, such a state will be referred to as "the bit line pair Bn." And (Bn bar) is L
"State".

In FIG. 9, the bit data in the memory cell M is searched, that is, the bit data held by the inverter gates I1 and I2 and the bit line pair Bn and (Bn bar) are input. The collation with the bit data to be performed is performed as follows.

That is, in the matching, first, the word line Wm and the search enable line ENm are left in the L state, and the match line MCHm is precharged to the H state. This precharge is based on the match line MCH
After connecting m to the power supply line, it is put in a floating state. By such precharge,
The logical state of the match line MCHm is the match line MCHm.
It is held in the H state by the electric charge accumulated in.

Against such precharge, on the other hand,
Bit data to be collated is input to the bit line pair Bn and (Bn bar). Upon inputting such bit data, the word line Wm remains in the L state and the search enable line ENm also remains in the L state, so the input bit data is held in the inverter gates I1 and I2. It does not affect the bit data to be stored or the precharged match line MCHm.

After the precharge is completed and bit data is input to the bit line pair Bn and (Bn bar), the search enable line ENm is set to the H state. By setting the search enable line ENm to the H state,
Both the N-channel MOS transistors T4 and T6 are turned on. Further, either one of the N-channel MOS transistors T3 or T5 is turned on according to the bit data held in the inverter gates I1 and I2. That is, when the bit data in the H state (“1”) is held by the inverter gates I1 and I2, the N channel MOS transistor T3 is turned on. On the other hand, when bit data in the L state (“0”) is held by these inverter gates I1 and I2, the N-channel MOS transistor T5 is turned on.

Therefore, when the search enable line ENm is in the H state in this way, the bit data held by the inverter gates I1 and I2 and the bit input by the bit line pair Bn and (Bn bar) are input. When the data matches the data, the H state precharged to the match line MCHm remains the H state.

For example, the inverter gates I1 and I
If the H state (“1”) is held in 2 and the H state is input from the bit line pair Bn and (Bn bar),
Since both the N-channel MOS transistors T3 and T4 are turned on and the match line MCHm is connected to the bit line Bn in the H state, the match line MCHm
Remains in the H state. Meanwhile, the inverter gate I
When the L state (“0”) is held in 1 and I2 and the L state is input from the bit line pair Bn and (Bn bar), the N channel MOS transistors T5 and T6 are Is also turned on, the match line MCHm is connected to the bit line (Bn bar) in the H state, and the match line MCHm remains in the H state.

On the other hand, the inverter gates I1 and I2
The bit data held by the bit line pair B
When the bit data input from n and (Bn bar) do not match, the match line MCHm is discharged and becomes L state.

For example, the inverter gates I1 and I
2 is held in the L state and the H state is input from the bit line pair Bn and (Bn bar), the N state is input.
The channel MOS transistors T5 and T6 are both turned on, the match line MCHm is connected to the bit line (Bn bar) in the L state, and the match line MCHm is connected.
Is discharged to the L state. Further, when the inverter gates I1 and I2 are kept in the H state and the bit line pair Bn and (Bn bar) is inputted in the L state, the N-channel MOS transistors T3 and T3.
4 are turned on, the match line MCHm is connected to the bit line Bn in the L state, and the match line MC
Hm is discharged to the L state.

According to the semiconductor memory device with a search function as described above, the search word data of the bit pattern input to the bit line is collated with the storage word data of the bit pattern stored in the word row of the memory matrix. Can be matched in parallel for many words.

For example, in the semiconductor memory device with search function shown in FIG. 8, bit line pairs (B1- (B1 bar)) to
By inputting the search word data to (Bn- (Bn bar)), all the search enable lines EN1 to ENM are simultaneously set to the H state, so that the words stored in all the M words in total are stored. The data can be collated with the input search word data all at once.
In addition, this matching result is the match lines MCH1 to MCHm.
Can be obtained from

[0025]

However, in the above-described conventional semiconductor memory device with a search function, the match lines of the word lines that do not match the input search word data are discharged all at once. Because
The current required for such discharge was concentrated on the power supply line for a period of time. For this reason, a large current would flow through the power supply line almost instantaneously.

If the current flowing through the power supply line is concentrated for a period of time as described above, a large current will burden the power supply line. For example, there is a risk that the power supply line will generate heat due to Joule heat due to the large current, and will be damaged by disconnection or the like. Further, in order to prevent such damage, the cross-sectional area of the power supply line has conventionally been increased, but if the power supply line is thickened in this way, the degree of integration of the semiconductor memory device is reduced. There is a problem. Further, if the current concentrates on the power supply line for a period of time, there is a problem that the intensity of power supply noise increases.

The present invention has been made to solve the above-mentioned conventional problems, and by reducing the peak maximum current flowing through the power supply line during the search operation in the semiconductor memory device with the search function, the power supply due to the large current is reduced. An object of the present invention is to provide a semiconductor memory device capable of reducing the load on the lines and reducing the intensity of power supply noise.

[0028]

SUMMARY OF THE INVENTION According to the present invention, a match line that has been precharged by a matching circuit provided for each memory cell forming a memory matrix for storing data of a word length M with a bit length N has been precharged. A semiconductor memory that obtains a matching result between the search word data of the bit pattern input to the bit line and the stored word data of the bit pattern stored in the word row of the memory matrix by detecting whether or not In the device, by arranging a plurality of divided memory matrix blocks of a total of P blocks each of which has a matching circuit and provided with a bit line for each bit string, data of a word length M with a bit length N is stored. Input the memory matrix and search enable signal,
At least P total search enable lines independent for each of the divided memory matrix blocks and a word that has been precharged before the search and the comparison result during the search does not match is a mismatched memory. At least a total sum of at least a total of (to transmit a matching match auxiliary signal corresponding to a precharge state, which is discharged by the matching circuit of the cell, is independent for each divided memory matrix block, and is independent for each word row of the memory matrix. M × P) a plurality of match lines, and a search enable timing circuit that generates the search enable signal for each of the search enable lines, the timings of which are shifted from each other, and the search is performed according to the matching match auxiliary signal. The result of matching between the word data and the stored word data is output as a match signal. By, in which to achieve the above objects.

In the semiconductor memory device, the memory matrix has a plurality of divided memory matrix blocks of a total of P blocks each having a matching circuit in which a bit line is provided for each bit string. A memory matrix for storing data of a word number M with a bit length N by further arranging the data in a plurality of divided memory matrix blocks. A plurality of at least M plural units provided for each word row of the memory matrix, which receives a signal and outputs a matching result of the matching word data of the corresponding word row and the search word data as a matching match signal. The above-mentioned problem is achieved by providing the collation result judging circuit.

[0030]

The memory matrix used in the semiconductor memory device with the search function of the present invention is a plurality of divided memory matrixes of P blocks in total, each memory cell having a matching circuit in which a bit line is provided for each bit string. By arranging blocks, data of a word length M with a bit length N is stored. Therefore, it can be said that the memory matrix of the present invention is divided into a plurality of divided memory matrix blocks, for example, a total of P blocks.

For example, a plurality of the divided memory matrix blocks may be arranged in the bit string direction as in the first embodiment described later. That is, for example, in the case of a memory matrix having a bit length of 64 bits and a word number of 128 words, for example, as in the first embodiment described later, a total of 2 blocks are provided, and the bit length is 16 bits and the word number is 128 words. The divided memory matrix blocks may be arranged and used in the bit string direction. Alternatively, the divided memory matrix block having a total of 4 blocks and having a bit length of 8 bits and a word number of 128 words may be arranged in the bit column direction and used for the memory matrix.

Alternatively, for example, a plurality of the divided memory matrix blocks may be arranged in the word address direction. In a second embodiment to be described later, a total of two blocks of the divided memory matrix having a bit length of 64 bits and a word number of 64 words are used, one is used for the first word address to the 64 word address, and the other is used for the sixth
Used from the 5th word address to the 128th word address,
As a whole, a total of 128 word addresses are used.
Further, the present invention is not limited to the use of two divided memory matrix blocks as in the second embodiment, and, for example, a total of three blocks or a total of four blocks may be arranged in the word address direction. Needless to say.

In the present invention, the memory matrix is divided into the total P blocks as described above, and the matching between the search word data and the stored word data is performed for each of the divided memory matrix blocks. I am trying to shift each other.

This is performed by inputting search enable signals whose timings are mutually shifted to independent search enable lines provided for each of the divided memory matrix blocks. The search enable signals whose timings are shifted from each other in this way can be generated by the search enable timing circuit while using a delay circuit or the like as in the embodiment described later.

As described above, in the present invention, the memory matrix to be used is divided into the plurality of divided memory matrix blocks, and the divided memory matrix blocks are sequentially searched, so that the current due to the discharge due to the mismatch of the collation during the search is generated. The peak maximum current that is distributed and flows through the power supply line during the search operation is reduced. For example,
When the memory matrix is divided into a total of two divided memory matrix blocks, it is possible to reduce the peak maximum current by almost half. By reducing the peak maximum current in this manner, for example, power supply noise radiated from the power supply line is also reduced. Further, for example, when the peak maximum current is halved, the thickness of the power supply line used can be halved, and the integration degree of the semiconductor memory device can be improved.

Although the present invention is not limited to this, in the case where the plurality of divided memory matrix blocks are arranged in the word address direction as described above and the second embodiment described later, From the collation matching auxiliary signal corresponding to each word row of each divided memory matrix block, the collation result of the search word data and the stored word data in the word row can be obtained. That is, in this case, it is possible to use the collation coincidence auxiliary signal as a collation coincidence signal for obtaining a collation result between the search word data and the stored word data in the word row.

Although the present invention is not limited to this, when a plurality of the divided memory matrix blocks are arranged in the bit column direction as described above and the first embodiment described later, The collation matching auxiliary signal of the divided memory matrix block and of each word row is
It cannot be directly used as the collation matching signal. That is, the collation matching auxiliary signal cannot be directly used for the collation result of the search word data and the stored word data in the word row. This is because the word data of each word address is divided in the bit string direction into the plurality of divided memory matrix blocks. Therefore, when the plurality of divided memory matrix blocks are arranged in the bit string direction,
The collation match auxiliary signals are input from the match lines of the corresponding word rows of a plurality of divided memory matrix blocks, and the storage word data of the corresponding word rows and the corresponding word rows are obtained by the logical product of the plurality of collation match auxiliary signals. The result of collation with the search word data may be output as a collation matching signal. For example, a collation result determination circuit for obtaining a collation result of the stored word data for one word and the search word data in this manner may be provided.

[0038]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of a main portion of a first embodiment of a semiconductor memory device to which the present invention is applied.

FIG. 1 shows the semiconductor memory device with search function of the first embodiment to which the present invention is applied.
The semiconductor memory device has a bit length of 64 bits and a word number of 128 words, and includes a memory matrix corresponding thereto. Also, the memory matrix is
A total of two blocks of the divided memory matrix block are arranged in the bit string direction. That is,
It is composed of a first divided memory matrix block and a second divided memory matrix block.

Each of these two divided memory matrix blocks has a bit length of 32 bits and a word number of 128 words. The memory matrix is composed of a total of 256 word memories MW1a to MW12.
8a and MW1b to MW128b. That is, the first divided memory matrix block is composed of the word memories MW1a to MW128a. On the other hand, the second divided memory matrix block includes the word memories MW1b to MW128.
It is composed by b.

These word memories MW1a to MW128
a and MW1b to MW128b are respectively shown in FIG.
The memory cell M having the above-described matching circuit shown in FIG.
32 are used in total. Therefore, each of the first divided memory matrix block and the second divided memory matrix block has the same structure as the memory matrix shown in FIG. 8, the bit length N of FIG. 8 is 32 bits, and the number of words M Is 128 words.

The word lines W1 to W128 of the first divided memory matrix block and the second divided memory matrix block are connected to each other and are common. All the search enable lines EN1 to EN1 of the first divided memory matrix block.
The EN128s are connected to each other, and the search enable signal E
Na has been entered. On the other hand, also in the second divided memory matrix block, the search enable lines EN1 to EN128 are connected to each other and the search enable signal ENb is input.

The search enable timing circuit 3 receives the search enable signal EN and generates these search enable signals ENa and ENb.

Further, in this embodiment, a total of 128 matching result judging circuits G1 to G128 using 2-input AND logic gates are used.

First, the collation result judging circuit G1 is arranged so that the match line M of the first divided memory matrix block.
The matching match auxiliary signal MCH1a is input by CH1 and the matching match auxiliary signal MC from the match line MCH1 of the second divided memory matrix block.
H1b is input and the logical product of these collation matching auxiliary signals is
It is output as the collation matching signal MC1. Also for the collation result determination circuit G2, the collation match auxiliary signal MCH2a is input from the match line MCH2 of the first divided memory matrix block, and the match line MCH2 of the second divided memory matrix block is input.
The collation matching auxiliary signal MCH2b is input from the above, and the collation matching signal MC2 is output by the logical product of these collation matching auxiliary signals. The same operation is performed for the collation result determination circuits G3 to G128 other than these.

That is, these collation result judging circuits G1 to G1
Reference numeral 28 denotes the matching match auxiliary signals MCH1a to MCH128a and MCH1b to MC for the match lines of the word lines of the first divided memory matrix block and the second divided memory matrix block corresponding to each other.
H128b is input, and by the logical product of these collation coincidence auxiliary signals, the collation coincidence signals MC1 to M of the word row are inputted.
C128 is generated. The generated matching match signals MC1 to MC128 become the matching result of the stored word data of the word row and the search word data.

FIG. 2 is a circuit diagram of the search enable timing circuit used in the embodiment.

As shown in FIG. 2, the search enable timing circuit 3 has a total of eight buffer gates B.
It is composed of.

In the search enable timing circuit 3, the input search enable signals EN are 1 in total.
It is output as a search enable signal ENa via the buffer gates B. Also, the search enable signal EN is sequentially passed through a total of seven buffer gates B,
It is output as the search enable signal ENb.

Since the search enable signal ENb is output through the buffer gate B, which is six more than the search enable signal ENa, the timing is delayed as compared with the search enable signal ENa. Therefore, the search enable signals ENa and ENb are shifted in timing from each other.

FIG. 3 is a time chart showing the operation of this embodiment.

In the time chart of FIG. 3, the search enable signals EN, ENa and ENb, the collation matching auxiliary signals MCH1a and MCH1b, and the collation matching signal MC1 are shown.

First, at time t ₁ , the search enable signal EN becomes H state. After that, the search enable signal ENa output through one buffer gate B in total becomes H state at time t ₂ . Also, a total of 7
The search enable signal ENb output via the buffer gates B becomes H state at time t ₄ .

First, when the search enable signal ENa goes into the H state at the time t _{2, the} search for the first divided memory matrix block is performed. by this,
For example, the collation coincidence auxiliary signal MCH1a of the first word line of the first divided memory matrix block, the time t ₃
Will change. In the time t _3, e.g., if the collation is a match becomes solid, for example, the collation becomes as a broken line if a mismatch. Further, when the collation does not match in this way, a power supply current due to discharge of the precharged charges flows.

On the other hand, when the search enable signal ENb is in the H state at the time t ₄ which is shifted in timing from the time t ₂ , the search in the second divided memory matrix block is performed. By such a search, for example, the first of the divided memory matrix blocks
The collation matching auxiliary signal MCH1b of the word line is
Change at ₅ . In the time t _5, for example, the first word line is as indicated by the solid line If collation coincidence, the dashed as if e.g. disagreement. If the collation does not match, the precharged electric charge is discharged, so that the power supply current flows.

The collation match signal MC1 changes at the time t ₃ or the time t ₅ according to the collation match auxiliary signal MCH1a or MCH1b.

As shown in the time chart of FIG. 3, first, the search enable signals ENa and ENb.
Are shifted in timing from each other (relationship between time t ₂ and time t ₄ ). As a result, the timings of changes in the matching and matching auxiliary signals MCH1a and MCH1b are also shifted from each other. Therefore, these collation matching auxiliary signals M
Even when both CH1a and MCH1b are discharged, the timings at which the power supply currents flow due to this are also shifted from each other. Therefore, the peak current flowing through the power supply line during the search operation is dispersed, and the peak maximum current is further reduced.

FIG. 4 is a circuit diagram of a main portion of a second embodiment of a semiconductor memory device to which the present invention is applied.

FIG. 4 shows a semiconductor memory device with a search function of the second embodiment to which the present invention is applied. The semiconductor memory device has a bit length of 64 bits and a word number of 64 words, and is provided with a memory matrix corresponding thereto. Further, the memory matrix is such that a total of two blocks of the divided memory matrix blocks are arranged in the word address direction. That is, it is composed of a first divided memory matrix block corresponding to the first word address to the 64th word address and a second divided memory matrix block corresponding to the 65th word address to the 128th word address.

Each of these two divided memory matrix blocks has a bit length of 64 bits and a word number of 64 words. In addition, the memory matrix has a total of 128 word memories MW1 to MW.
It is composed of 128. That is, the first divided memory matrix block is the word memory MW1.
~ MW64. Meanwhile, the second divided memory matrix block includes the word memory M.
It is composed of W65 to MW128.

These word memories MW1 to MW128
Are configured by using a total of 64 memory cells M each having the above-described matching circuit shown in FIG. Therefore, each of the first divided memory matrix block and the second divided memory matrix block has a structure like the memory matrix shown in FIG. 8, and the bit length N of FIG. 8 is 64 bits,
In addition, the word number M is set to 64 words.

The word line W of the first divided memory matrix block as shown in FIG. 8 is also used.
As shown in FIG. 4, 1 to W64 are used as word lines W1 to W64 in the entire memory matrix including the first divided memory matrix block and the second divided memory matrix block. On the other hand, the word lines W1 to W64 of the second divided memory matrix block as shown in FIG. 8 have the first divided memory matrix block and the second divided memory matrix block as shown in FIG. It is used as the word lines W65 to W128 in the entire memory matrix including the above.

The search enable lines EN1 to EN64 of all the word memories MW1 to MW64 of the first divided memory matrix block are connected to each other, and the search enable signal ENa is inputted. On the other hand, the search enable lines EN65 to EN128 of all the word memories MW65 to MW128 of the second divided memory matrix block are connected to each other, and the search enable signal ENb is inputted.

The search enable timing circuit 3 of the second embodiment is the same as that used in the first embodiment. That is, the search enable timing circuit 3
Receives the search enable signal EN and generates the search enable signals ENa and ENb. These search enable signals ENa and ENb are shifted in timing from each other by a predetermined time.
Specifically, the search enable timing circuit 3 is as shown in the circuit diagram of FIG.

In the second embodiment, the first
The matching result determination circuits G1 to G128 provided in the embodiment
Is no longer needed. This is because, in the second embodiment, the divided memory matrix blocks of a total of 2 blocks are arranged in the word address direction.
Therefore, the stored word data to be compared with the search word data input at the time of search corresponds to each of the word memories MW1 to MW128. Therefore, the search word data and the stored word data in the word row are calculated from the collation match auxiliary signal by the match line as shown in FIG. 8 corresponding to each word row of each divided memory matrix block. It is possible to directly obtain the collation result with the collation match signals MC1 to MC128.

In comparison, when the plurality of divided memory matrix blocks are arranged in the bit string direction as in the first embodiment, the storage to be compared with the search word input at the time of search. Word data is
Each word is divided into different word memories provided in different divided memory matrix blocks in the bit string direction. Therefore, in the case of the first embodiment, the verification result matching circuits G1 to G128 provide the verification result matching circuits G1 to G128 with the verification result matching signals of the different word memories obtained by dividing the one storage word data. Must be integrated.

As described above, also in the second embodiment, the search enable signal ENa input to the first divided memory matrix block and the search enable signal ENb input to the second divided memory matrix block. The timings of can be shifted from each other. Accordingly, the search execution time in the first divided memory matrix block and the search execution time in the second divided memory matrix block can be shifted, and the match line discharge time in the first divided memory matrix block can be shifted. And the discharge time of the match line of the second divided memory matrix block can be shifted from each other. Therefore, also in the second embodiment, it is possible to disperse the peak current flowing through the power supply line during the search operation and further reduce the peak maximum current.

FIG. 5 is a graph of the power supply current during the search operation in the conventional semiconductor memory device with the search function. on the other hand,
6 and 7 are graphs of the power supply current during the search operation in the semiconductor memory device with the search function of the first embodiment and the second embodiment.

First, in the prior art, as shown in FIG.
Power supply current during search operation is t ₁Concentrates on.
In comparison with this, in the first embodiment and the second embodiment,
As shown in FIG. 6 or FIG.
The peak currents of are distributed. For example, in FIG.
At time t₂And time t₃Are distributed in and. Also before
In Figure 7, time t_FourAnd time t_FiveDistributed in and
There is.

In FIGS. 6 and 7, the time t ₂ and the time t ₄ are peaks of the power supply current corresponding to the search operation in the first divided memory matrix block. On the other hand, the time t ₃ and the time t ₅ are
This is at the peak time of the power supply current due to the search operation in the second divided memory matrix block.

As is clear from comparing FIGS. 5 to 7, according to the first embodiment and the second embodiment, the peak maximum current flowing through the power supply line during the search operation is higher than that in the conventional case. It can be reduced to almost half.

[0073]

As described above, according to the present invention, the peak maximum current flowing through the power supply line during the search operation in the semiconductor memory device with the search function is further reduced, so that the load on the power supply line due to the large current is reduced. It is possible to obtain an excellent effect that it is possible to reduce or reduce the intensity of power supply noise.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of a first embodiment of a semiconductor memory device to which the present invention is applied.

FIG. 2 is a circuit diagram of a search enable timing circuit used in the first embodiment.

FIG. 3 is a time chart showing the operation of the first embodiment.

FIG. 4 is a circuit diagram of a main part of a second embodiment of a semiconductor memory device to which the present invention is applied.

FIG. 5 is a graph of power supply current during a search operation in a conventional semiconductor memory device with a search function.

FIG. 6 is a first graph showing a power supply current during a search operation in the first embodiment and the second embodiment.

FIG. 7 is a second graph showing a power supply current during a search operation in the first and second embodiments.

FIG. 8 is a circuit diagram of a memory matrix of a conventional semiconductor memory device with a search function.

FIG. 9 is a circuit diagram of a memory cell used in the memory matrix of the conventional semiconductor memory device with a search function.

[Explanation of symbols]

3 ... Search enable timing circuits M11 to MMN ... Memory cells MW1a to MW128a, MW1b to MW128b, MW1 to MW128 ... Word memories T1 to T6 ... N channel MOS transistors I1, I2 ... Inverter gates Bn, (Bn bar), B1 to BN , (B1 bar) ~ (B
N bar) ... Bit lines Wm, W1 to WM ... Word lines ENm, EN1 to ENM, ENa, ENb ... Search enable lines (or search enable signals) MCHm, MCH1 to MCHM ... Match lines (or matching match auxiliary signals) G1 G128 ... Collation result determination circuit MC1 to MC128 ... Collation coincidence output (or collation coincidence signal) EN, ENa, ENb ... Search enable signal B ... Buffer gate

Claims (2)

(57) [Claims] 1. A method of detecting whether or not discharge by a matching circuit provided for each memory cell forming a memory matrix for storing data of a word length M with a bit length N is applied to a precharged match line. In the semiconductor memory device that obtains the matching result between the search word data of the bit pattern input to the bit line and the storage word data of the bit pattern stored in the word row of the memory matrix, the bit for each bit string A memory matrix in which a plurality of divided memory matrix blocks each having a line and provided with memory cells each having a matching circuit are arranged so as to store data of a word number M with a bit length N; Independent of each divided memory matrix block that inputs enable signal Further, at least a total of P search enable lines are precharged before the search is executed, and a word for which the matching result during searching does not match is discharged by the matching circuit of the mismatched memory cell. Will be
At least a total of (M × P) plurality of match lines, which are independent for each of the divided memory matrix blocks and independent for each word row of the memory matrix, and which transmit the matching match auxiliary signal corresponding to the precharge state. A search enable timing circuit for generating the search enable signal for each of the search enable lines, the timings of which are shifted from each other, and a result of matching the search word data with the stored word data according to the matching match auxiliary signal. Is output as a collation matching signal. 2. A plurality of divided memory matrix blocks of a total of P blocks, each of which has memory cells each having a matching circuit, in which a bit line is provided for each bit column, in the memory column according to claim 1. A memory matrix that stores data of a word length M with a bit length N by arranging them, and further, from the match line of the corresponding word row of a plurality of divided memory matrix blocks, the collation matching auxiliary signal. For outputting a matching result between the stored word data of the corresponding word row and the search word data as a matching match signal, a plurality of at least M in total provided for each word row of the memory matrix. A semiconductor memory device comprising a matching result determination circuit.