JP3510072B2 - Driving method of plasma display panel - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type display panel constituted by a set of display elements (cells) having a memory function, and more particularly to an AC type plasma display panel (PDP), which is of high quality. The present invention relates to a driving method thereof capable of displaying various images.

[0002]

2. Description of the Related Art In a conventional AC type plasma display panel, as shown in Japanese Patent Laid-Open No. 6-186927, one field period is divided into two or more subfields, and all writing and erasing are performed in each subfield. A discharge period, an address discharge period, and a sustain discharge period are set.

The sustain discharge period of each subfield is determined by the number of repetitions of the sustain discharge weighted as a ratio of 1: 2: 4: 8: ...: 128 in binary code,
Each gradation is displayed by selecting and combining the number of times of light emission within one field period.

Further, during the entire writing and erasing discharge periods of each subfield, all the writing discharges and the erasing discharges are performed on all cells to make the charges uniform, and during the address discharge period, the sustain discharge is performed in the subfields. Address discharge is performed only in the cell (selected cell) to be made to accumulate positive charges in the vicinity of the Y electrode, and sustain discharge is performed using the charges. Then, during the sustain discharge period, sustain discharge pulses of the same voltage are alternately applied at equal intervals to the X electrode and the Y electrode. One set of sustain discharge pulses for one X electrode and one Y electrode is set, and this combination is repeatedly applied to each electrode according to the weighting of each subfield.

When the application of the last sustain discharge pulse in this sustain discharge period is finished, a positive voltage is applied to the electrode serving as the anode during the full write discharge in the next subfield, and full write discharge and erase discharge are performed. Further, the next subfield is repeated after the address discharge period and the sustain discharge period.

[0006]

By the way, in the sustain discharge period in the above-mentioned prior art, the sustain discharge pulse of the same voltage is repeatedly applied to the X electrode and the Y electrode at equal time intervals, and the last sustain discharge pulse is applied. Immediately after that, a voltage is applied to the electrode serving as an anode during the full write discharge of the next subfield to perform the full write discharge, and then the erase discharge is performed.

In such a plasma display panel driving method, all write and erase discharges are surely carried out in all the cells in the plasma display panel due to the miniaturization of the cells in accordance with the higher definition. There are some cells that do not exist, and malfunctions such as erroneous discharge of non-selected cells that do not sustain discharge and discharge failure of light-emitting (selected) cells may occur. The cause is that space charges are excessively generated due to the sustain discharge in the subfield immediately before the full write and erase discharge periods, and the wall charges on the electrodes are insufficient or the full write discharge occurs. It is considered that this is due to the attachment of electric charges that reduce the execution voltage.

An object of the present invention is to solve such a problem, to enable all write discharge and erase discharge to be performed reliably and with a sufficient discharge intensity, and erroneous discharge of non-selected cells and discharge failure of selected cells. It is an object of the present invention to provide a driving method of a plasma display panel, which eliminates such malfunctions as described above and can obtain a high-quality image with good uniformity over the entire panel.

[0009]

In order to achieve the above object, the present invention provides a final sustain discharge pulse to be applied between each subfield, that is, a sustain discharge period of a preceding subfield, and a subsequent sustain discharge pulse. between the complete book write discharge pulse to be applied to the complete book write and erase discharge period of the subfield, outermost
When the subsequent sustain discharge pulse is applied, the first and second
The potential relationship is similar to the potential relationship between the electrodes, and the width of the period in which the electrode serving as the cathode during the full write discharge has a high potential for 10 μsec or more and 500 μsec or less with respect to the electrode serving as the anode during the full write discharge is stabilized. By setting the pulse , the space charge existing in each discharge cell is reduced, and the positive charge is on the electrode that becomes the anode and the negative charge is on the electrode that becomes the cathode during the full write discharge. As a result, all the write and erase discharges in the succeeding subfields are surely performed with sufficient discharge intensity.

Specifically, the full write operation is performed between the last sustain discharge pulse applied during the sustain discharge period of the preceding subfield and the full write discharge pulse applied during the full write and erase discharge periods of the subsequent subfield. The voltage of the electrode serving as the anode during discharge is set to the ground level, and the state of applying a positive voltage to the electrode serving as the cathode is set for a period of 10 μsec or more and 500 μsec or less.

Alternatively, between the last sustain discharge pulse applied during the sustain discharge period of the preceding subfield and the full write discharge pulse applied during the full write and erase discharge periods of the subsequent subfield, the anode is generated during the full write discharge. Negative voltage is applied to the electrode that becomes the negative electrode, and positive voltage or the ground level is applied to the electrode that becomes the negative electrode.
Set the following period.

Furthermore, in order to reduce malfunctions such as erroneous discharges and discharge failures and improve image quality, the last sustaining discharge pulse applied in the sustaining discharge period of the preceding subfield and all write and erase discharges of the following subfields. 10 μsec or more, 50 between all write discharge pulses applied during the period
It is possible to change the voltage value applied to each electrode, the application time, and the application timing in a period of 0 μsec or less.

Further, the application time may be set according to the sustain discharge period for each subfield.

Alternatively, one cycle period of the vertical synchronizing signal and one
It is applied in the blank generated by the difference between the total writing and erasing discharge period of each subfield in the field and the total time of the address discharge period and the sustain discharge period, that is, the sustain discharge period of the last subfield of the preceding field. Even between the last sustain discharge pulse and the full write discharge pulse applied during the full write and erase discharge periods of the first subfield of the subsequent field, the electrode that becomes the cathode during the full write discharge becomes the electrode that becomes the positive electrode. The high potential period may be set to 10 μsec or more and 500 μsec or less.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. First, the structure of an AC type plasma display panel to which the present invention can be applied will be described with reference to FIG. However, 4 is a front glass substrate, 5a is an X transparent electrode, 5b is an X bus electrode, 6a is a Y transparent electrode, 6b is a Y bus electrode, 7 is a protective film, 8a and 8b are dielectric layers, and 9 is a partition wall 10R. , 10G and 10B are phosphors, 11 is an address electrode, 12 is a rear glass substrate, and 13 is a discharge space.
Further, the X electrode 5 including the X transparent electrode 5a and the X bus electrode is included.
Y including the Y transparent electrode 6a and the Y bus electrode 6b
It is called electrode 6.

In the following description, the last sustain discharge pulse is applied to the Y electrode 6 during the sustain discharge period of the preceding subfield, and the subsequent full write and erase discharge period of the subsequent subfield are performed. Although the discharge anode is the X electrode, it is obvious that the present invention is not limited to this.

In FIG. 2, a plurality of address electrodes 11 are arranged in parallel with each other on the rear glass substrate 12, and a dielectric layer 8b is formed so as to completely cover the address electrodes 11. On the dielectric layer 8b, the partition walls 9 are provided at positions where the address electrodes 11 are sandwiched.
1 are formed in parallel with each other, and a space extending in a direction parallel to the address electrodes 11 partitioned by the partition walls 9 is formed. Then, in each of these spaces, a phosphor that emits colored light by ultraviolet irradiation is applied to the wall surface of the partition wall 9 and the surface of the dielectric layer 8b, and the phosphors 10R applied to every two spaces are The phosphor 10G coated with red light emits green light, and the phosphor 10G coated with every other space emits blue light.

On the other hand, on the front glass substrate 4, X transparent electrodes 5a and Y transparent electrodes 6a are alternately and parallel to each other in a direction orthogonal to the address electrodes 11 formed on the rear glass substrate 12. Further, an X bus electrode 5b and a Y bus electrode 6b are formed on the X transparent electrode 5a and the Y transparent electrode 6a, respectively. Here, the adjacent X transparent electrodes 5a and Y transparent electrodes 6a
Assuming two electrode pairs, in the same electrode pair, the X bus electrode 5b is formed at the end of the X transparent electrode 5a opposite to the Y transparent electrode 6a, and the Y bus electrode 6b is the Y transparent electrode 6a.
The transparent electrode 5a is formed at the end opposite to the X transparent electrode 5a. A dielectric layer 8a is formed so as to completely cover the X transparent electrode 5a, Y transparent electrode 6a and the X bus electrode 5b, Y bus electrode 6b. Further, MgO or the like is formed on the dielectric layer 8a. A protective film 7 made of is formed.

The rear glass substrate 12 and the front glass substrate 4 thus provided with the respective electrodes are abutted against each other as shown by the arrow, and the protective film 7 on the front glass substrate 4 is placed on the partition wall 9 of the rear glass substrate 12. The plasma display panel is configured so that the two touch each other.

Then, the protective film 7 and the phosphors 10R, 10
A predetermined gas is enclosed in the space formed by the partition wall 9 coated with G and 10B and the dielectric layer 8b.
A space defined by the X bus electrode 5b and the Y bus electrode 6b in the same electrode pair and two adjacent partition walls 9 forms a discharge space 13 of one discharge cell.

FIG. 3 is a diagram showing the wiring of each electrode in the plasma display panel shown in FIG.
, Al (where l is an integer of 1 or more) are the address electrodes 11 shown in FIG. 2, and X1, X2, ..., Xm (where m is an integer of 1 or more) are the X transparent electrodes shown in FIG. 5a and X bus electrodes 5b, X electrodes 5, Y1, Y2, ..., Ym
Is the Y electrode 6 including the Y transparent electrode 6a and the Y bus electrode 6b shown in FIG.

In the figure, m X electrodes X1,
, Xm and Y electrodes Y1, Y2, ..., Ym are arranged in parallel and alternately, and one ends of these X electrodes X1, X2 ,. The same drive voltage is applied, but Y electrodes Y1, Y2, ...,
Ym are provided independently of each other, and different drive waveforms are applied to each. Also, l address electrodes A1, ..., A
l are independent of each other, and X electrodes X1, X2, ..., X
m and the Y electrodes Y1, Y2, ..., Ym are arranged so as to be orthogonal to each other, and different drive waveforms are applied to them.

In this case, m X electrodes X1 and X
, ..., Xm are all connected to one common end, but these X electrodes X1, X2, ..., Xm are divided into a plurality of groups, and each group has one X electrode.
You may make it connect to one common terminal.

FIG. 4 is a diagram showing an example of a conventional driving method in the subfield of the plasma display panel having the structure described above. The horizontal axis represents time, and the vertical axis represents Y electrodes Y1 to Y1.
Each represents Ym.

In the figure, here, one field period 15 includes eight subfields SF1 to SF8, the total time for all subfields, and one of the vertical synchronizing signals Vsync.
The blank period 14 is generated due to the difference from the cycle period.

FIG. 5 shows the n-th line in FIG. 4 (where n =
It is a figure which shows the structure of the subfield SFn of 1, 2, ..., 8). However, the description of this subfield SFn is the same for all subfields.

In the figure, the subfield SFn is composed of a full write and erase discharge period 1, an address discharge period 2 and a sustain discharge period 3. The entire write and erase discharge period 1 and the address discharge period 2 each require the same time length in all subfields SFn. For example, the time length of the address period 2 is the number of Y electrodes m (FIG. 3) and each Y electrode. 6 is determined by the cycle of the scan pulse sequentially applied. Further, the sustain discharge period 3 is determined by the pulse period and the number of pulses of the sustain discharge pulse forming the pulse train.

In the full write and erase discharge period 1, all cells are discharged between the X electrode 5 and the Y electrode 6 to generate charged particles to form wall charges. In the address period 2, the discharge is performed between the Y electrode 6 and the address electrode 11 in the cell in which the sustain discharge should be performed in the sustain discharge period 3, and the discharge cell in which the sustain discharge is performed is selected in the sustain discharge period 3. Then, the selected cell is repeatedly discharged by the number of sustain discharge pulses applied in the sustain discharge period 3 of the subfield. Here, as shown in FIG. 4, the number of subfields in one field is 8, and as described above, these subfields SF1, SF
2, ..., The number of sustain discharge pulses in the sustain discharge period 3 of SF8 is, for example, weighted by a binary code. Now, subfields SF1, SF2, ...,
The number of sustain discharge pulses applied in sustain discharge period 3 of SF8 (that is, the number of sustain discharges) is NSF1 to NSF8.
Then, the ratio of the number of sustain discharges is the weighting ratio, that is, NSF1: NSF2: ...
..: NSF8 = 1: 2: 4: 8: ...: 128, and 256 kinds of gray scale display are possible by the combination of subfields in which the sustain discharge is performed in the sustain discharge period 3. For example, in a certain discharge cell, when displaying the 10th gradation (excluding gradation 0) from the low brightness, the subfield SF2 in which the relative ratio of the number of sustain discharge pulses is 2 and 8 respectively. It suffices to select SF4 by address discharge and perform sustain discharge in each sustain discharge period 3.

FIG. 6 is a diagram showing a part of a driving waveform of an example of a conventional driving method for a plasma display panel having such a configuration, in which the horizontal axis represents time and the vertical axis represents the X electrode 5 in order from the top.
, The voltage applied to the Y electrode 6, and the voltage applied to the address electrode 11 are shown. here,
The same voltage is applied to all the X electrodes X1 to Xm, the voltage applied to the Y electrodes Y1 and Ym for the Y electrode 6, and the address electrode A1 for the address electrode 11.
It shows the voltage applied to.

In the example shown in FIG. 6, the preceding subfield S
When the application of the last sustain discharge pulse 17 of the voltage Vs is completed in the sustain discharge period 3 of Fn, the positive voltage is not applied to the Y electrode 6 and the next succeeding subfield SF (n +) is generated.
In the all-writing and erasing discharge period 1 of 1), the all-writing discharge pulse 19 having a positive voltage Vw is applied to the X electrode 5 serving as an anode during the all-writing discharge to perform all-writing discharge.
In such a driving method, as described above, there is a discharge cell in which all the writing discharge and the erasing discharge are not surely performed, and a malfunction occurs.

The above is one example of the conventional driving method,
Hereinafter, embodiments of the driving method according to the present invention will be described. In the embodiments described below, the plasma display panel having the configuration shown in FIGS. 2 and 3 is also used, and as shown in FIGS. It is assumed that each field is configured in.

FIG. 1 is a diagram showing drive waveforms in a first embodiment of a method for driving a plasma display panel according to the present invention. Similar to FIG. 6, the horizontal axis represents time and the vertical axis represents X sequentially from the top. The voltages applied to the electrodes 5, Y electrodes 6, and address electrodes 11 are shown respectively.

In the figure, first, in the entire write and erase discharge period 1 of the preceding subfield SFn, the positive voltage V
A full write discharge pulse 19 of w is applied to the X electrode 5, and a full write discharge with the X electrode 5 as an anode and the Y electrode 6 as a cathode is performed. Then, a positive voltage Vs (<Vw) is applied to the Y electrode 6,
In addition, the erase discharge pulse 2 of the ground level GND is applied to the X electrode 5.
By applying 8 respectively, erase discharge is performed,
Wall charges are formed on the X electrode 5, the Y electrode 6 and the address electrode 11, respectively.

Next, in the address discharge period 2, usually Y
The electrode 6 is held at a positive voltage Vsc (<Vs), but Y
A scan pulse 29 of the ground level GND is applied in the order of the electrodes Y1, Y2, ..., Ym, and at the same time as the scan pulse 29 is applied to the Y electrode 6 passing through the selected cell to emit light, the address passing through this selected cell is also applied. An address pulse 30 having a voltage Va is applied to the electrode 11, which causes address discharge in the selected cell.

Then, in the next sustain discharge period 3, the voltage V
The sustain discharge pulse 17 of s starts from the Y electrode 6 and is alternately applied to the X electrode 5 and the Y electrode 6, whereby the sustain discharge is performed in the selected discharge cell (that is, the selected cell).

When the last sustain discharge pulse 17 in the sustain discharge period 3 is applied to the Y electrode 6 and the sustain discharge ends, Y
When the voltage applied to the electrode 6 is once lowered to the ground level GND and the full writing and erasing discharge period 1 of the next succeeding subfield (n + 1) starts, Y which becomes a cathode during the full writing discharge is started.
A pulse of a positive voltage Vs is applied to the electrode 6 for a period of 10 μsec or more and 500 μsec or less (hereinafter referred to as 10 μsec to 500 μsec) (here, this pulse is referred to as a stabilizing pulse, and this is referred to as a stabilizing pulse. (Which is set in the charging and erasing period 1) 20 is applied, and then the full write discharge pulse 19 of the positive voltage Vw is applied to the X electrode 5 to make the X electrode an anode and the Y electrode a cathode. All write discharges are performed, and thereafter, the subfield SF (n +
For 1), the above operation is repeated.

FIG. 7 is a diagram showing a charge model in the discharge (selection) cell for the driving operation of the first embodiment shown in FIG. 1, and 10 is the phosphors 10R, 10G,
10B, any part corresponding to FIG. 2 is given the same reference numeral.

FIG. 7A shows the state in the discharge cell immediately after the last sustain discharge in the sustain discharge period 3 is completed. At this time, a large number of spaces generated by the sustain discharge so far. There is an electric charge.

At the next programming and erasing discharge period 1 of the next succeeding subfield (n + 1), as shown in FIG.
Stabilization pulse 20 of positive voltage Vs is applied to Y electrode 6 for 10 μs.
By being applied for a period of ec to 500 μsec, as shown in FIG. 7B, excessive space charges are attenuated by diffusion and recombination, and the Y electrode 6 side is relatively high potential and the X electrode is relatively high. Since the 5th side has a low potential, a negative charge 27 is generated on the dielectric layer 8a on the Y electrode 6 and the protective film layer 7 (hereinafter, on the Y electrode 6 for simplification of expression) and the X electrode 5 Positive charges 26 are respectively accumulated as wall charges on the upper dielectric layer 8a and the protective film layer 7 (hereinafter, referred to as the X electrode 5 for simplifying the expression). In addition, the address electrode 11
Also on the upper side, a small amount of positive charge 26 on the X electrode 5 is accumulated, but the positive charge 26 is accumulated. Where cell 1
At least 10 to several tens of μ is required for the decay of the space charge in 3
A time period of sec is required, and if it is 500 μsec or less, it is sufficiently attenuated.

FIG. 7 (c) shows a state in which the space charge in the discharge space 13 of the selected cell is sufficiently attenuated to form the wall charge. In this state, as shown in FIG. When the full write discharge pulse 19 is applied to the X electrode 5, reliable full write discharge is performed, and malfunctions such as erroneous discharge and discharge failure can be eliminated.

The application timing of the stabilizing pulse 20 shown in FIG. 1 and its voltage value (here, Vs) are shown as an example, and the present invention is not limited to this.

That is, the space charge generated by the discharge is
The number of Y-electrodes 6 increases immediately after the discharge. Therefore, after the last sustain discharge pulse 17 is applied, that is, immediately after the last sustain discharge pulse 17 applied to the Y electrode 6 falls, the Y electrode 6 is discharged.
By applying a positive voltage stabilizing pulse 20 to
More wall charges can be stored.

By adjusting the period from the fall of the stabilizing pulse 20 to the application of the full write discharge pulse 19, the amount of wall charges involved in the full write discharge can be adjusted.

Further, by adjusting the pulse width of the stabilizing pulse 20, the amount of wall charges accumulated can be adjusted.

Further, by adjusting the voltage value of the stabilizing pulse 20, the amount of accumulated wall charges can be adjusted.

Further, before the application of the stabilizing pulse 20 is completed (that is, before the Y electrode 6 reaches the ground level GND).
Then, a positive voltage is applied to the X electrode 5 and all write discharge pulses 1
The application of the stabilizing pulse 20 may be completed before the application of 9.

FIG. 8 is a diagram showing a driving waveform in the second embodiment of the driving method of the plasma display panel according to the present invention. Similar to FIG. 1, the horizontal axis represents time and the vertical axis represents X in order from the top. The voltages applied to the electrodes 5, Y electrodes 6, and address electrodes 11 are shown respectively.

In the first embodiment, the last sustain discharge pulse 17 applied to the Y electrode 6 ends, the voltage of the Y electrode 6 once drops from the voltage Vs to the ground level GND, and then the Y electrode 6 is applied. Although the stabilizing pulse 20 having the positive voltage Vs is applied, in the second embodiment, as shown in FIG.
As shown in FIG. 7, in the Y electrode 6, the stabilization pulse 21 having the same voltage Vs as the last sustain discharge pulse 17 applied is applied.
Are connected and applied, and the application time of this stabilizing pulse 21 is 10 μs as in the first embodiment.
ec to 500 μsec.

Also in the second embodiment, the operation described in FIG. 7 similar to that of the first embodiment is performed, and the same effect as that of the first embodiment can be obtained.

Further, since the discharge caused by the application of the stabilizing pulse 21 is performed in the same state as the conventional sustain discharge, this discharge is included in the number of sustain discharges.

FIG. 9 is a diagram showing drive waveforms in the third embodiment of the plasma display panel drive method according to the present invention. Similar to FIG. 1, the horizontal axis represents time and the vertical axis represents X from top to bottom. The voltages applied to the electrodes 5, Y electrodes 6, and address electrodes 11 are shown respectively.

In this embodiment, as shown in FIG. 9, when the last sustain discharge pulse 17 applied to the Y electrode 6 in the preceding subfield SFn ends and the next succeeding subfield SF (n + 1) starts, In the full writing and erasing discharge period 1, the stabilization pulse 22 having a negative voltage of −Vs is applied to the X electrode 5 for a period of 10 μsec to 500 μsec, and then the full writing discharge pulse 19 is applied to the X electrode 5. All writing discharge is performed.

While the stabilizing pulse 22 is being applied, in the discharge cell, the voltage Vsc is applied relatively to the Y electrode 6 side and the potential is relatively high, and the X electrode 5 side is relatively low potential. Occurs for a period of 10 μsec to 500 μsec, whereby the operation shown in FIG. 7 is performed and an effect equivalent to that of the first embodiment is obtained.

FIG. 10 is a diagram showing drive waveforms in the fourth embodiment of the plasma display panel drive method according to the present invention. Similar to FIG. 1, the horizontal axis represents time and the vertical axis represents X sequentially from the top. The voltages applied to the electrodes 5, Y electrodes 6, and address electrodes 11 are shown respectively.

In this embodiment, as shown in FIG. 10, when the last sustain discharge pulse 17 applied to the Y electrode 6 in the preceding subfield SFn ends and the next succeeding subfield SF (n + 1) starts, In the full writing and erasing discharge period 1, a stabilizing pulse 23 having a negative voltage of −Vs / 2 is applied to the X electrode 5 serving as an anode during full writing.
The stabilizing pulse 24 of the positive Vs / 2 voltage is applied to the cathode Y electrode 6 at the same timing and the same 10 μse.
It is applied for a period of c to 500 μsec.

During the application of these stabilizing pulses 23 and 24,
In the discharge cell, a state in which the Y electrode 6 side is relatively high potential and the X electrode 5 side is relatively low potential is 10 μsec.
This will occur for a period of 500 μsec, which
The operation shown in FIG. 7 is performed and the same effect as that of the first embodiment is obtained.

FIG. 11 is a diagram showing drive waveforms in the fifth embodiment of the plasma display panel drive method according to the present invention. Similar to FIG. 1, the horizontal axis represents time and the vertical axis represents X sequentially from the top. The voltages applied to the electrodes 5, Y electrodes 6, and address electrodes 11 are shown respectively.

In this embodiment, as shown in FIG. 11, one cycle period of the vertical synchronizing signal Vsync and all write / erase discharge period 1, address discharge period 2, and sustain discharge period 3 of each subfield in one field are included. Blank 14 (that is, the last sustain discharge pulse 17 applied to the last subfield SF8 of the preceding field 15 and the full write discharge applied to the first subfield SF1 of the next subsequent field 15). (Between the pulse 19), a stabilizing pulse 25 of a positive Vs voltage is applied to the Y electrode 6 on the cathode side during the entire write discharge in the first subfield SF1 of the subsequent field 15 for 10 μsec.
The voltage is applied for a period of 500 μsec.

During the application of the stabilizing pulse 25, the state where the Y electrode 6 side is relatively high potential and the X electrode 5 side is relatively low potential within the discharge cell is 10 μsec to 500 μs.
This occurs for a period of ec, whereby the operation shown in FIG. 7 is performed and the same effect as that of the first embodiment can be obtained.

In the fifth embodiment, in the blanking period 14, as shown in FIG.
After the last sustaining discharge pulse 17 applied to the Y electrode 6, a stabilizing pulse of a positive Vs voltage is applied to the side.
It may be applied for a period of μsec to 500 μsec, or, as shown in FIG. 9, a stabilizing pulse having a negative voltage of −Vs on the X electrode 5 side is applied for 10 μsec to 50 μs.
The voltage may be applied for a period of 0 μsec, and as shown in FIG. 10, a negative −Vs is applied to the X electrode 5.
A stabilizing pulse of a voltage of / 2 is applied to the Y electrode at Vs /
The stabilizing pulses of the voltage of 2 may be applied at the same timing and for the same period of 10 μsec to 500 μsec. Also, with this, the same field 15
In the entire writing and erasing discharge period 1 of each subfield in the same, the stabilizing pulse may be similarly applied.

Further, in each of the above embodiments, one field is composed of eight subfields, but the present invention is not limited to this, and it is composed of other numbers of subfields. You can also do
The number of gray scales to be displayed can be changed according to the number of subfields forming one field. Generally, one field is composed of N subfields, and the ratio of the number of sustain discharge pulses in each subfield is
As described above, when represented by the ratio of binary codes, it is 2
The gradation of the Mth power of is obtained.

[0062]

As described above, according to the present invention,
Since excessive space charges in the discharge cells after the sustain discharge can be reduced and wall charges can be sufficiently accumulated, it becomes possible to perform all write discharges and erase discharges more reliably with sufficient strength, and to achieve high definition. As a result of the miniaturization of cells and the increase in the total number of cells in the plasma display panel, reliable discharge operation can be realized in the entire plasma display panel.

[Brief description of drawings]

FIG. 1 is a diagram showing drive waveforms in a first embodiment of a method for driving a plasma display panel according to the present invention.

FIG. 2 is an exploded perspective view showing a part of the structure of an AC type plasma display panel.

FIG. 3 is a diagram schematically showing an arrangement relationship of electrodes in an AC type plasma display panel.

FIG. 4 is a diagram showing a field structure for driving an AC type plasma display panel.

5 is a diagram showing a configuration of a subfield in FIG.

FIG. 6 is a diagram showing drive waveforms of an example of a conventional plasma display panel driving method.

7 is a diagram showing a charge model in a discharge cell of an AC type plasma display panel for the embodiment shown in FIG.

FIG. 8 is a diagram showing drive waveforms in the second embodiment of the plasma display panel drive method according to the present invention.

FIG. 9 is a diagram showing drive waveforms in a third embodiment of a plasma display panel drive method according to the present invention.

FIG. 10 is a diagram showing drive waveforms in a fourth embodiment of a method of driving a plasma display panel according to the present invention.

FIG. 11 is a diagram showing a driving waveform in a fifth embodiment of the driving method of the plasma display panel according to the present invention.

[Explanation of symbols]

1 All write and erase discharge period 2 address period 3 sustain discharge period 4 Front glass substrate 5 X electrodes 5a X transparent electrode 5b X bus electrode 6 Y electrodes 6a Y transparent electrode 6b Y bus electrode 7 protective film 8a, 8b Dielectric layer 9 partitions 10R, 10G, 10B Fluorescent body 11 address electrodes 12 Rear glass substrate 13 discharge space 14 blank period 15 fields 17 Sustain discharge pulse 18 Final sustain discharge pulse 19 All write discharge pulse 20-25 stabilization pulses 26 Positive charge 27 Negative charge 28 Erase discharge pulse 29 scan pulses 30 address pulse

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Sasaki 4-6 Kanda Surugadai, Chiyoda-ku, Tokyo Hitachi, Ltd. Home Appliances and Information Media Business Division (72) Inventor Hiroshi Otaka Hiroshi Kanda-Surugadai, Chiyoda-ku, Tokyo 6-chome, Hitachi, Ltd. Home Appliances and Information Media Division (56) References JP-A-9-62225 (JP, A) JP-A-8-160909 (JP, A) JP-A-8-129357 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G09G 3/28 G09G 3/20 611 G09G 3/20 622 G09G 3/20 624 G09G 3/20 670

Claims (4)

(57) [Claims] 1. A plasma display panel in which a plurality of first and second electrodes are arranged in parallel and alternately on a front glass substrate, one field is divided into a plurality of subfields, and each subfield is divided into a plurality of subfields. In a method of driving by supplying a drive pulse according to a predetermined rule to the first and second electrodes for each period, which is composed of a full write and erase discharge period, an address discharge period and a sustain discharge period. , The last in the sustain discharge period of the preceding subfield
After the application of the sustain discharge pulse, the full write discharge pattern in the subsequent full write and erase discharge periods of the subfield is applied.
The last sustain discharge pulse was applied before applying the loose
The same potential relationship as the potential relationship between the first and second electrodes when
In addition, a stabilizing pulse having a width of a predetermined period in which the electrode of the first and second electrodes, which becomes the cathode at the time of full write discharge, has a higher potential than the electrode which becomes the anode, is set. Driving method for plasma display panel. 2. The voltage according to claim 1, wherein during the predetermined period of time, a voltage of the one of the first and second electrodes, which serves as an anode at the time of full write discharge, to a ground potential, is applied to the electrode that serves as a cathode. A method for driving a plasma display panel, characterized in that a positive constant voltage is applied to each. 3. The electrode according to claim 1, wherein, during the predetermined period, a negative constant voltage is applied to the electrode of the first and second electrodes that serves as an anode during full write discharge, and the electrode that serves as a cathode is grounded. A method of driving a plasma display panel, which comprises applying a voltage having a potential or a constant positive voltage, respectively. 4. The method according to claim 1, 2 or 3, wherein the predetermined period is 10 μsec or more and 500 μsec.
A driving method of a plasma display panel, characterized in that the period is as follows.