JP3506585B2 - Light emitting diode array - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode array, and more particularly to a light emitting diode array used as an exposure source for a photosensitive drum of a page printer. 2. Description of the Related Art FIGS. 4 and 5 show a conventional light emitting diode array. FIG.
FIG. 5 is a sectional view taken along line AA of FIG. 4. 4 and 5, 21 is a semiconductor substrate, 22 is a buffer layer, 23 is one conductivity type semiconductor layer, 24 is a reverse conductivity type semiconductor layer, 25 is an ohmic contact layer, 26 is a first electrode, and 27 is a second electrode. The electrode 28 is a protective film. The semiconductor substrate 21 is made of, for example, silicon (S
i) or a single crystal semiconductor substrate such as gallium arsenide (GaAs). Buffer layer 22, one conductivity type semiconductor layer 2
3. The opposite conductivity type semiconductor layer 24 and the ohmic contact layer 25 are made of a compound semiconductor layer such as gallium arsenide or aluminum gallium arsenide. A semiconductor junction is formed at the interface between the one conductivity type semiconductor layer 23 and the opposite conductivity type semiconductor layer 24. The one-conductivity-type semiconductor layer 23 and the opposite-conductivity-type semiconductor layer 24 are formed in an island shape by, for example, mesa etching after forming a single crystal semiconductor layer made of gallium arsenide, aluminum gallium arsenide, or the like by MOCVD, MBE, or the like. Is done. On almost the entire back surface of the semiconductor substrate 21,
A first electrode 26 is formed. A protective film 28 made of, for example, silicon nitride (SiN _x ) is formed on the surface portions of the one conductivity type semiconductor layer 23 and the opposite conductivity type semiconductor layer 24. , A second electrode 27 made of, for example, gold (Au) is formed. The second electrode 27 is formed from the upper surface portion of the opposite conductivity type semiconductor layer 24 via the wall surface portion.
The adjacent semiconductor layer 22 is extended to near the end face of the semiconductor substrate 21.
２５25 to alternately extend to the other end face side. Note that the second electrode 27 is connected to the semiconductor layers 22 to 25.
May be provided on the same column side. The island-shaped semiconductor layers 22 to 25 and the first electrode 26
Each of the light-emitting diodes is constituted by the second electrode 27 and these light-emitting diodes are arranged on the semiconductor substrate 21 in a line. The second electrode 27 is connected to an external circuit by a bonding wire or the like at a wide portion thereof. However, in this conventional light emitting diode array, a first electrode 26 is provided on the back side of the semiconductor substrate 21 and a second electrode 27 is provided on the front side of the semiconductor substrate 21.
Is provided, the first electrode 26 and the second electrode 2
There is a problem that the forming process of Step 7 is performed twice and the manufacturing process becomes complicated. The first electrode 26 and the second electrode 2
When 7 is on both the front and back surfaces of the semiconductor substrate 21, there is also a problem that the connection work is difficult when connecting to an external circuit by a wire bonding method or the like. Accordingly, the present inventors have disclosed in Japanese Patent Application No. 7-192.
No. 857, as shown in FIGS. 6 and 7, a semiconductor layer 23 is provided on a semiconductor substrate 21 with a buffer layer 22 interposed therebetween.
An opposite conductivity type semiconductor layer 24 having an area smaller than that of the one conductivity type semiconductor layer 23 is provided thereon, and a first electrode 26 is connected to an exposed portion R of the one conductivity type semiconductor layer 23. A light emitting diode array in which the second electrode 27 is connected to the layer 24 via the ohmic contact layer 25 has been proposed. In FIG. 7, reference numeral 28 denotes a protective film made of a silicon nitride film or the like. With this configuration, the first electrode 26 (26a, 26b) and the second electrode 27 can be provided on the same side of the semiconductor substrate 21, and the first electrode 26 and the second electrode 27 Can be simultaneously formed in one process, so that the manufacturing process of the light emitting diode array is simplified and
Since the first electrode 26 and the second electrode 27 are located on the same side, a connection operation with an external circuit by a wire bonding method or the like is also facilitated. The first electrode 26 (26a, 26b)
Is, as shown in FIG. 6, the adjacent one conductivity type semiconductor layer 23.
The second electrodes 27 are provided so as to belong to different groups, and belong to different groups, and adjacent opposite conductive semiconductor layers 24 are provided so as to be connected to the same second electrodes 27. ing. In this conventional light emitting diode array, exposed portions R are provided on both sides of a light emitting element row so as to alternately expose opposite ends of adjacent one conductivity type semiconductor layers 23, and the exposed portions R are provided. And the second electrode 27 is also connected to the adjacent reverse conductivity type semiconductor layer 2.
Every four are connected to the opposite end side. However, in this conventional light emitting diode array, the second electrode 27 is connected to the ohmic contact layer 25.
Is formed over a long region substantially at the center of the opposite conductivity type semiconductor layer 24, and the second electrode 27 blocks the strongest light emitted at the center of the semiconductor junction,
There is a problem that the light extraction efficiency is reduced and the overall light emission efficiency is reduced. In addition, since the strongest light is emitted at the center of the light emitting element at the semiconductor junction, even if the second electrode 27 is slightly displaced, the light emission intensity distribution in the light emitting element increases. There were also problems. The present invention has been made in view of such a problem of the conventional device, and it is possible to eliminate a decrease in light extraction efficiency due to an electrode formed on a light emitting element, and to displace the electrode pattern. It is an object of the present invention to provide a light emitting diode array in which light emission variations caused by the above are eliminated. In order to achieve the above object, in a light emitting diode array according to the present invention, one conductive semiconductor layer is provided in an island shape on a substrate, and the one conductive semiconductor layer is provided. An intrinsic semiconductor layer is provided on the one conductivity type semiconductor layer so that one end side of the semiconductor layer is exposed, and a reverse conductivity type semiconductor region reaching the one conductivity type semiconductor layer in a depth direction at a substantially central portion of the intrinsic semiconductor layer. Are provided in a strip shape, and electrodes are respectively connected to the exposed portion of the one conductivity type semiconductor layer and the opposite conductivity type semiconductor region on the end side facing the exposed portion. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a view showing one embodiment of a light emitting diode array according to the present invention, and FIG.
FIG. 3 is a sectional view taken along line A. 1 and 2, 1 is a substrate, 2 is a buffer layer, 3 is a one conductivity type semiconductor layer, 4 is an intrinsic semiconductor layer, 5 is a reverse conductivity type semiconductor region, 6 is an ohmic contact layer, and 7 (7a, 7b). Is the first electrode, 8 is the second electrode
Electrodes. The substrate 1 is made of, for example, a single crystal semiconductor substrate such as silicon (Si) or gallium arsenide (GaAs), or a single crystal insulating substrate such as sapphire (Al ₂ O ₃ ). Even when a semiconductor substrate is used as the substrate 1, it is desirable to use a semiconductor substrate having as high a resistance as possible. In the case of a single crystal semiconductor substrate, a (100) plane or the like is used, and in the case of sapphire, a C plane or the like is used. On the substrate 1, a buffer layer 2 made of gallium arsenide or the like having a thickness of about 1 to 4 μm is formed in order to reduce misfit dislocation due to a difference in lattice constant between the substrate 1 and the one conductivity type semiconductor layer 3. Provide. A semiconductor layer 3 of one conductivity type is provided on the buffer layer 2. The semiconductor layer 3 of one conductivity type is made of gallium arsenide or aluminum gallium arsenide (Al _x Ga _{1 -x} As). ) Or selenium (Se), such as 1 × 10 ¹⁶ to 10 ¹⁹ atoms.
It contains about s / cm ³ . This one conductivity type semiconductor layer 3 is formed to a thickness of about 0.1 to 3 μm. Further, it is desirable to provide a layer containing a high-concentration one-conductivity-type semiconductor impurity at a connection portion between the one-conductivity-type semiconductor layer 3 and a first electrode described later. The exposed portion R is formed on the one-conductivity-type semiconductor layer 3 at one end of the one-conductivity-type semiconductor layer 3.
An intrinsic semiconductor layer 4 is formed. The intrinsic semiconductor layer 4 is also made of a compound semiconductor layer such as aluminum gallium arsenide (Al _y Ga _{1 -y} As), but has a semiconductor impurity of 1 × 10 ^15.
Contains not more than atoms / cm ³ . This intrinsic semiconductor layer 4 is formed to a thickness of about 0.1 to 3 μm. In a substantially central portion of the intrinsic semiconductor layer 3, a reverse conductivity type semiconductor region 5 is formed in a band shape. The opposite conductivity type semiconductor region 5 contains a reverse conductivity type semiconductor impurity such as zinc (Zn) at about 1 × 10 ¹⁶ to 10 ¹⁸ atoms / cm ³ and is formed in a semicircular or semielliptical shape having a diameter of about 2 μm. ing. The opposite conductivity type semiconductor region 5 is formed so as to reach the one conductivity type semiconductor layer 3 in the depth direction of the intrinsic semiconductor layer 4, and is formed in a band shape in the width direction of the intrinsic semiconductor layer 4. . Further, an ohmic contact layer 6 containing 1 × 10 ¹⁹ atoms / cm ³ or more of a semiconductor impurity of the opposite conductivity type is provided at a connection portion between the opposite conductivity type semiconductor region 5 and a second electrode 8 described later. Therefore,
The opposite conductivity type semiconductor region 5 and the second electrode 8 are connected via the ohmic contact layer 6. A semiconductor junction is formed at the interface between the one conductivity type semiconductor layer 3 and the opposite conductivity type semiconductor region 5. The opposite conductivity type semiconductor region 5 may be formed in a plurality of layers having different compound crystal ratios of the compounds. The semiconductor layers 2 to 6 formed in an island shape are covered with a protective film 9 made of, for example, a silicon nitride film or the like, and extend from the exposed portion R of the one conductivity type semiconductor layer 2 onto the semiconductor substrate 1. Then, a first electrode 7 (7a, 7b) made of, for example, gold (Au) is formed. Every other conductivity type semiconductor layer 3 is alternately connected to different first electrodes 7 (7a, 7b). That is, the one conductivity type semiconductor layer 3 is divided into two groups, and the first electrodes 7 (7
a, 7b). A second electrode 8 is formed so as to extend from the surface of the opposite conductivity type semiconductor region 5 to the semiconductor substrate 1 via a wall surface opposite to the first electrode 7. That is, the second electrode 8 is connected and provided for each adjacent light emitting diode belonging to a different group. The bent portion of the second electrode 8 serves as a wire bonding terminal for connecting to an external circuit. By selecting a combination of the first electrode 7 (7a, 7b) and the second electrode 8, individual light emitting diodes can be selected to emit light. In the above-described light emitting diode, if the one conductivity type semiconductor layer 3 is n-type and the opposite conductivity type semiconductor region 5 is p-type, the gap between the opposite conductivity type semiconductor region 5 and the one conductivity type semiconductor layer 3 is assumed. When a current is applied in the forward direction to one of the first electrodes 7
If the other first electrode 7b is connected with a opened, only the light emitting diode connected to the other first electrode 7b emits light. Therefore, even if the common second electrode 8 is provided for each of the adjacent opposite conductivity type semiconductor regions 5, the first electrodes 7 (7a, 7b) are separately connected. (7a, 7b) and second electrode 8
The adjacent light emitting diodes can be selectively made to emit light by changing the connection state between them. Next, a method for manufacturing a light emitting diode array according to the present invention will be described with reference to FIG. First, substrate 1
A buffer layer 2 made of gallium arsenide or the like, a semiconductor layer 3 of one conductivity type made of aluminum gallium arsenide or the like, an intrinsic semiconductor layer 4 made of aluminum gallium arsenide or the like,
And an ohmic contact layer 6 made of gallium arsenide or the like is sequentially laminated (see FIG. 1A). These semiconductor layers 2 to 6 are formed by, for example, MOCVD or MBE. That is, when the semiconductor substrate is used as the substrate 1 and formed by MOCVD, a natural oxide film of the semiconductor substrate is removed at a high temperature of 800 to 1000 ° C.
After growing an amorphous gallium arsenide film serving as a nucleus at a low temperature of 50 ° C. or less to a thickness of about 0.1 to 2 μm,
The temperature is raised to about 700 ° C. and recrystallization is performed to grow a gallium arsenide single crystal (two-step growth method). In this case, trimethyl gallium ((CH ₃ ) ₃ G
a) is used, and arsine (A) is used as a raw material of arsenic.
sH ₃ ) and the like. Next, 750-1000 ° C
Post-annealing such as repeating several times of annealing at a high temperature and rapid cooling to a low temperature of 600 ° C. or less (temperature cycle method). Subsequently, the buffer layer 2 is grown to a predetermined thickness, and the one conductivity type semiconductor layer 3, the intrinsic semiconductor layer 4, and the ohmic contact layer 6 are successively grown. When forming an aluminum gallium arsenide layer, trimethyl aluminum ((CH ₃ ) ₃ Al) or the like is used as a raw material of aluminum. As a semiconductor impurity gas for controlling the conductivity type, silane (SiH ₄ ) or the like is used. Next, each of the semiconductor layers 2 to 6 is formed into an island shape by mesa etching. The upper surface and the side wall portion of the island portion are made of aluminum oxide (Al ₂ O ₃ ), and the upper surface portion is formed in a stripe shape. The diffusion control layer 10 having the slit 11 is formed by a sputtering method or the like (see FIG. 2B). Next, paste-like zinc (Zn), which is an impurity of the opposite conductivity type, is applied to the slit 11 of the diffusion control layer 10 and annealed in a nitrogen atmosphere at 700 to 800 ° C. (see FIG. 3C). ). As a result, in the intrinsic semiconductor layer 4, zinc (Zn), which is an impurity of the opposite conductivity type, is diffused to form an impurity region 5 of the opposite conductivity type. In this case, zinc (Zn) is 1 × 1
If it is diffused by about 0 ¹⁶ to 10 ¹⁸ atoms / cm ³ , it can be used as a light emitting region (see FIG. 4D). Next, the diffusion control layer 10 is removed by etching, and the intrinsic semiconductor layer 4 is further etched so that one end of the one conductivity type semiconductor layer 3 is exposed to form an exposed portion R in the one conductivity type semiconductor layer 3. Then, the protective film 9, the first electrode 7, and the second electrode 8 are formed to complete (see FIG. 2). As described above, according to the light emitting diode array of the present invention, one conductive semiconductor layer is provided on the substrate in an island shape, and one end of the one conductive semiconductor layer is exposed. An intrinsic semiconductor layer is provided on the one-conductivity-type semiconductor layer, and a reverse-conductivity-type semiconductor region that reaches the one-conductivity-type semiconductor layer in a depth direction is provided in a substantially central portion of the intrinsic semiconductor layer in a strip shape. Since the electrodes are connected to the exposed portion of the one conductivity type semiconductor layer and the opposite conductivity type semiconductor region on the end side facing the exposed portion, the position of the semiconductor junction can be limited, A decrease in luminous efficiency due to the electrodes can be suppressed. Further, by reducing the area of the semiconductor junction, the current can be concentrated and the luminous efficiency can be increased. Further, since the semiconductor bonding portion is positioned by patterning for one row, the luminous concentration does not depend on the arrangement of the electrode contacts, so that the seriality of light spots is improved and the printing quality is improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing one embodiment of a light emitting diode array according to the present invention. FIG. 2 is a sectional view taken along line AA in FIG. FIG. 3 is a process chart showing a method for manufacturing a semiconductor device according to the present invention. FIG. 4 is a view showing a conventional light emitting diode array. FIG. 5 is a sectional view taken along line AA in FIG. 4; FIG. 6 is a diagram showing another conventional light emitting diode array. FIG. 7 is a sectional view taken along line AA in FIG. [Description of Signs] 1... Substrate, 3... One conductivity type semiconductor layer, 4... Intrinsic semiconductor layer, 5 reverse conductivity type semiconductor region, 7... First electrode, 8. 2 electrodes

Claims (1)

(57) [Claim 1] A one-conductivity-type semiconductor layer is provided on a substrate in an island shape, and the one-conductivity-type semiconductor layer is exposed such that one end side of the one-conductivity-type semiconductor layer is exposed. An intrinsic semiconductor layer is provided thereon, and a reverse-conductivity-type semiconductor region that reaches the one-conductivity-type semiconductor layer in a depth direction is provided in a band shape at a substantially central portion of the intrinsic semiconductor layer, and an exposed portion of the one-conductivity-type semiconductor layer is provided. A light emitting diode array in which electrodes are connected to the exposed portion and the opposite conductivity type semiconductor region on the end side facing the exposed portion;