JP3587806B2 - Semiconductor device and manufacturing method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device using a compound semiconductor substrate such as a Ga-As substrate and a method for manufacturing a semiconductor device, and particularly to a semiconductor device having a via hole in a substrate and having a metal interlayer connection.
[0002]
[Prior art]
Conventionally, in a semiconductor device using a compound semiconductor substrate (hereinafter, simply referred to as a compound semiconductor device), a compound semiconductor substrate is used.ofA technique has been adopted in which a wiring is formed on the back surface and connected to an electrode formed on the substrate surface via a connection hole (via hole).
[0003]
FIG. 11 is a schematic cross-sectional view illustrating an example of a semiconductor device having a structure having via holes in a compound semiconductor substrate.
In this compound semiconductor device, an Au electrode 102 is pattern-formed on a surface of a compound semiconductor substrate 101 such as a Ga-As substrate, and a wiring 103 and an electrode 102 formed on the back surface of the substrate 101 are connected to via holes 104. Connected within. The wiring 103 is formed by depositing a NiCr layer 111 and an Au layer 112 by a vapor deposition method, and forming an Au plating layer 113 using the deposited layer as a power supply metal.
[0004]
[Problems to be solved by the invention]
However, when the above-described wiring structure is formed in a compound semiconductor device, there is a serious problem that failures such as breakage of a metal film constituting the wiring 103, depression of the Au electrode 102, and destruction of the semiconductor substrate 101 occur.
[0005]
FIG. 12 is a schematic cross-sectional view showing a state in which the above-described failure has occurred in a compound semiconductor device by a conventional method.
As shown in FIG. 12A, the sidewall of the via hole 104 is formed in a tapered shape, so that the thickness of the semiconductor substrate 101 near the bottom of the via hole 104 is reduced to about several μm. As a result, the stress of the semiconductor substrate 101, the Au electrode 102, and the wiring 103 acts on the thin portion 112 of the substrate in contact with the Au electrode 102 and the via hole 104, and the substrate is broken as shown in FIG. Further, this substrate destruction causes disconnection 113 in the Au electrode 102 and the wiring 103.
[0006]
As described above, conventionally, in order to respond to recent demands for miniaturization and miniaturization of compound semiconductor devices, if a via contact is attempted using the back surface of the substrate, stress is necessarily applied to a thin portion. There is a problem that the substrate and its neighboring structures are concentrated and damaged.
[0007]
Therefore, the present invention has been made in view of the above-described problems, and prevents a substrate from being broken or broken in the vicinity of a connection hole formed in a compound semiconductor substrate, and has excellent reliability in manufacturing yield. And a method of manufacturing the same.
[0008]
[Means for Solving the Problems]
As a result of intensive studies, the present inventor has reached various aspects of the invention described below.
[0009]
The inventor of the present invention has found that, due to the destruction of the substrate or the breaking of the metal film in the vicinity of the connection hole formed in the compound semiconductor substrate, visual inspection failure due to electrode depression or characteristic failure due to an increase in wiring resistance are caused. It could be concluded that this was the main cause of the decrease in the yield as a semiconductor device. The present invention proposes an optimum semiconductor device structure and a method of manufacturing the same in order to prevent substrate breakdown and metal film disconnection.
[0010]
A semiconductor device according to the present invention includes a compound semiconductor substrate in which a connection hole is formed, a wiring formed as a stacked structure in the connection hole, and a wiring formed on the compound semiconductor substrate and electrically connected to the wiring. And the laminated structure of the wiring includes a first wiring layer and a second wiring layer having a higher hardness than the first wiring layer.Only, the first wiring layer and the second wiring layer are made of the same metal material.It is characterized by the following.
[0011]
In one aspect of the semiconductor device of the present invention, the connection hole is formed on a back surface of the compound semiconductor substrate, and the wiring is formed between the first wiring layer and the second wiring layer in the connection hole. Are laminated to form the laminated structure.
[0012]
In one aspect of the semiconductor device of the present invention, the connection hole is configured such that a first hole formed on a surface of the compound semiconductor substrate communicates with a second hole formed on a back surface of the compound semiconductor substrate. The first wiring layer is formed in one of the first hole and the second hole, and the second wiring layer is formed in the other.
[0013]
In one embodiment of the semiconductor device of the present invention, the first wiring layer and the second wiring layer are both metal films formed by a plating method.
[0014]
In one aspect of the semiconductor device of the present invention, the first wiring layer and the second wiring layer are formed by different growth methods.
[0015]
Semiconductor device of the present inventionForming a connection hole in the compound semiconductor substrate, forming a first wiring layer in a region including the inside of the connection hole, and forming the first wiring on a surface of the first wiring layer. Forming a second wiring layer having a hardness higher than that of the first wiring layer, wherein the first wiring layer and the second wiring layer are formed of the same metal material.It is characterized by the following.
[0016]
Semiconductor device of the present inventionIn one aspect of the manufacturing method, the connection hole is formed on the back surface of the compound semiconductor substrate, and the wiring is formed by laminating the first wiring layer and the second wiring layer in the connection hole. It is formed as follows.
[0017]
Manufacturing method of semiconductor device of the present inventionIn one aspect, the connection hole, a first hole on the front surface of the compound semiconductor substrate, and a second hole on the back surface of the compound semiconductor substrate are respectively formed, and the first hole and the second hole are formed. The first wiring layer is formed in one of the first hole and the second hole, and the second wiring layer is formed in the other. I do.
[0018]
In one embodiment of the method for manufacturing a semiconductor device of the present invention,The method further includes forming an electrode on the compound semiconductor substrate so as to be electrically connected to the first wiring layer and the second wiring layer.
[0019]
In one embodiment of the method for manufacturing a semiconductor device of the present invention,The first wiring layer and the second wiring layer are formed by different growth methods.
[0020]
Manufacturing method of semiconductor device of the present inventionForming a connection hole in the compound semiconductor substrate, forming a first wiring layer in a region including the inside of the connection hole, forming a first wiring layer on the surface of the first wiring layer, Forming a second wiring layer having high hardness, wherein at least one of the first wiring layer and the second wiring layer is formed by a plating method, and when the plating method is performed, a plating current is reduced. The hardness of the first wiring layer and / or the hardness of the second wiring layer is adjusted by controlling the supply amount.
[0021]
In one embodiment of the method for manufacturing a semiconductor device of the present invention,The connection hole is formed on the back surface of the compound semiconductor substrate, and the wiring is formed such that the first wiring layer and the second wiring layer are stacked in the connection hole.
[0022]
In one embodiment of the method for manufacturing a semiconductor device of the present invention,The connection hole, a first hole on the surface of the compound semiconductor substrate, and a second hole on the back surface of the compound semiconductor substrate, respectively, so that the first hole communicates with the second hole. The first wiring layer is formed in one of the first hole and the second hole, and the second wiring layer is formed in the other.
[0023]
In one embodiment of the method for manufacturing a semiconductor device of the present invention,The method further includes forming an electrode on the compound semiconductor substrate so as to be electrically connected to the first wiring layer and the second wiring layer.
[0024]
In one embodiment of the method for manufacturing a semiconductor device according to the present invention, both the first wiring layer and the second wiring layer are formed by a plating method.
[0025]
In one embodiment of the method for manufacturing a semiconductor device of the present invention,When performing the plating method, the method further includes a step of forming a plating electrode before forming the first wiring layer.
[0026]
In one embodiment of the method for manufacturing a semiconductor device of the present invention,The plating electrode is formed to a predetermined thickness of 200 nm or less.
[0027]
Manufacturing method of semiconductor device of the present inventionForming a connection hole in the compound semiconductor substrate, forming a first wiring layer in a region including the inside of the connection hole, forming a first wiring layer on the surface of the first wiring layer, Forming a second wiring layer having high hardness, wherein both the first wiring layer and the second wiring layer are formed by a plating method, and the first wiring is formed when the plating method is performed. The layer is formed by supplying a smaller plating current than at the time of forming the second wiring layer.
[0028]
In one embodiment of the method for manufacturing a semiconductor device of the present invention,The connection hole is formed on the back surface of the compound semiconductor substrate, and the wiring is formed such that the first wiring layer and the second wiring layer are stacked in the connection hole.
[0029]
In one embodiment of the method for manufacturing a semiconductor device of the present invention,The connection hole, a first hole on the surface of the compound semiconductor substrate, and a second hole on the back surface of the compound semiconductor substrate, respectively, so that the first hole communicates with the second hole. The first wiring layer is formed in one of the first hole and the second hole, and the second wiring layer is formed in the other.
In one embodiment of the method for manufacturing a semiconductor device of the present invention, the method further includes a step of forming an electrode on the compound semiconductor substrate so as to be electrically connected to the first wiring layer and the second wiring layer. Including.
In one aspect of the method of manufacturing a semiconductor device of the present invention, the hardness of the first wiring layer and the second wiring layer is adjusted by controlling a supply amount of a plating current when performing the plating method. .
In one aspect of the method for manufacturing a semiconductor device of the present invention, the step of performing the plating method further includes a step of forming a plating electrode before forming the first wiring layer.
In one aspect of the method for manufacturing a semiconductor device of the present invention, the plating electrode is formed to a predetermined thickness of 200 nm or less.
[0030]
In the present invention, a wiring is formed by sequentially laminating a first wiring layer and a second wiring layer having a higher hardness than the first wiring layer in the connection hole. From a structural point of view, a second wiring layer having a high hardness is formed on the semiconductor substrate via a first wiring layer having a low hardness, and the second wiring layer is formed on the semiconductor substrate (and formed on the semiconductor substrate). Function as a buffer material for relieving the stress on the applied electrode) and the stress on the first wiring layer. Furthermore, since the second wiring layer is densely formed in proportion to its hardness, the components of the dicing material formed on the second wiring layer are prevented from diffusing into the second wiring layer. Thus, the hardness of the second wiring layer is maintained. As a result, occurrence of substrate destruction due to stress concentration and prevention of disconnection of wiring and depression of electrodes caused by the destruction are realized.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments to which the present invention is applied will be described in detail with reference to the drawings.
[0032]
(1st Embodiment)
In the present embodiment, a MESFET using a compound semiconductor substrate is exemplified as a semiconductor device.
[0033]
-Wiring structure in via hole of semiconductor substrate-
In the present embodiment, a wiring structure formed in a via hole of a semiconductor substrate in a MESFET is disclosed as a main configuration. Therefore, first, the wiring structure will be described with reference to FIG.
[0034]
In the wiring structure according to the present embodiment, an Au electrode 2 formed by patterning an Au film formed by plating on the surface of a compound semiconductor substrate 1 made of GaAs or the like is formed, and the Au electrode 2 is electrically connected to the Au electrode 2. The wiring 4 is formed in the back surface region including the inside of the via hole 3 formed so as to expose a part of the surface of the Au electrode 2 from the back surface of the semiconductor substrate 1.
[0035]
The wiring 4 is an Au wiring formed by a plating method, and has a two-layer structure of a first wiring layer 11 having a low hardness and a second wiring layer 12 having a high hardness. is there.
[0036]
Specifically, first, a NiCr film 13 and an Au film 14 serving as power supply metals (plating electrodes) for supplying a plating current are sequentially formed in the via hole 3 so as to be connected to the Au electrode 2. A low-hardness Au plating film and a high-hardness Au plating film are sequentially formed thereon by a plating method, and a low-hardness wiring layer 11 and a high-hardness wiring layer 12 are formed by patterning to provide a two-layer structure having different hardnesses. The wiring 4 is obtained. In order to change the hardness by plating, the amount of plating current to be supplied may be changed. The amount of plating current is small when forming the wiring layer 11 having low hardness, and the amount of plating current is low when forming the wiring layer 12 having high hardness. What is necessary is just to set a large amount of current.
[0037]
Then, an AuSn layer 15 used as a brazing material is formed so as to cover the wiring layer 12 and fill the via hole 3, and the semiconductor substrate 1 is diced to the package 10 by the AuSn layer 15.
[0038]
FIG. 2 shows a comparative example for comparison and study with the wiring structure of the present embodiment.
In this comparative example, as shown in FIG. 2A, a NiCr film 13 and an Au film 14 are formed in the via hole 3, a low-hardness Au plating film 17 is formed on the Au film 14, and a wiring 16 is formed from these. Was configured.
[0039]
In this comparative example, by forming the wiring 16 with a material having low hardness, the stress of the wiring 16 itself is reduced, and the stress of the semiconductor substrate 1, the NiCr film 13, the Au film 14, and the Au electrode 2 is reduced. 16 and tried to prevent the substrate from being broken.
[0040]
However, after forming the wiring 16, the AuSn layer 15 is formed in the same manner as in the present embodiment, and the package 10 is diced. As shown in FIG. 2B, the Sn component of the AuSn layer 15 Diffusion alloying (indicated by reference numeral 18 in the drawing) increased the plating hardness of the wiring 16. As a result, a strong stress was applied to the semiconductor substrate 1 from all of the various metals in the via hole 3, and the substrate was broken as in the conventional case.
[0041]
On the other hand, in the wiring structure of the present embodiment, the wiring 4 is formed by sequentially laminating the first wiring layer 11 and the second wiring layer 12 having higher hardness than the via hole 3. . From a structural point of view, a second wiring layer 12 having a high hardness is formed on the semiconductor substrate 1 via a first wiring layer 11 having a low hardness. It functions as a buffer that relieves the stress applied to the Au electrode 2 formed thereon and the stress applied to the first wiring layer 11. Further, since the second wiring layer 12 is densely formed in proportion to its hardness, the Sn component of the AuSn layer 15 which is a dicing material formed on the second wiring layer 12 is reduced by the second wiring layer. Diffusion into the layer 12 is prevented, and the hardness of the second wiring layer 12 is maintained. Thus, the occurrence of substrate destruction due to stress concentration, and the prevention of disconnection of the wiring 4 and the depression of the Au electrode 2 due to the destruction are realized.
[0042]
-Configuration and manufacturing method of MESFET-
Hereinafter, a configuration and a manufacturing method of the MESFET based on the above-described wiring structure will be described. For convenience, the configuration of the MESFET will be described together with its manufacturing process. 3 to 6 are schematic cross-sectional views showing a method of manufacturing the MESFET of the present embodiment in the order of steps, and FIGS. 4 and 5 are schematic cross-sectional views for specifically explaining the steps of manufacturing a wiring structure.
[0043]
First, as shown in FIG. 3A, a semi-insulating compound semiconductor substrate 1 made of GaAs or the like is prepared, and an overhang-shaped gate electrode 31 is formed by patterning.
[0044]
Specifically, for example, an Al alloy film (not shown) is formed on the semiconductor substrate 1 by a sputtering method, and then a resist pattern (not shown) having a predetermined shape is formed on the Al alloy film. Only the upper part of the alloy film is dry-etched, and subsequently the lower part of the Al alloy film is wet-etched. At this time, under the resist pattern, an overhang shape comprising the upper layer portion remaining following the shape of the resist pattern by dry etching and the upper layer portion formed narrower than the upper layer portion by wet etching. Gate electrode 31 is formed.
[0045]
Subsequently, as shown in FIG. 3B, after AuGe films 32 and 33 are pattern-formed on the source / drain formation portions of the semiconductor substrate 1, SiO 2 is formed on the semiconductor substrate 1 so as to cover the gate electrode 31.₂The gate insulating film 34 made of is formed.
[0046]
Subsequently, as shown in FIG. 3C, the gate insulating film 34 on the AuGe films 32 and 33 is selectively removed, and the thickness of the gate insulating film 34 is reduced to a thickness such that the gate electrode 31 is embedded.₂Is deposited to form an interlayer insulating film 41 made of. Then, via holes 42 and 43 are pattern-formed in the interlayer insulating film 41 so as to expose a part of the surface of the AuGe films 32 and 33 and a part of the Au electrode formation site.
[0047]
Next, in the via hole 42, an Au film 36 is formed via a Ni film 35, and the Ni film 35 and the Au film 36 are patterned to form a source electrically connected to the AuGe films 32, 33. An electrode 37 and a drain electrode 38 are formed.
[0048]
On the other hand, in the via hole 43, after forming an Au film 44 as a plating base, an Au film 45 is formed by a plating method, and the Au films 44, 45 are patterned to form the Au electrode 2.
[0049]
Subsequently, the above-described wiring structure is formed. For convenience, in each of FIGS. 4A and 4B, the Au electrode 2 composed of the Au films 44 and 45 is simplified in a single-layer structure.
Specifically, first, as shown in FIG. 4A, a protective film 51 is applied and formed so as to cover the surface of the semiconductor substrate 1, and this is cured. A grinding jig 52 is set on the cured protective film 51, and the back surface of the semiconductor substrate 1 is ground. Grinding is performed until the substrate thickness becomes about 20 to 300 μm in order to match the impedance of each semiconductor device.
[0050]
Subsequently, as shown in FIG. 4B, a thick film resist corresponding to the ground substrate thickness is applied to the back surface of the semiconductor substrate 1 and processed by photolithography to form a resist pattern 53. Then, using the resist pattern 53 as a mask, the semiconductor substrate 1 is subjected to phosphoric acid-based and hydrofluoric acid-based wet etching or chlorine-based and fluorine-based dry etching until a part of the surface of the Au electrode 2 is exposed, so that the wall surface is tapered. Is formed.
[0051]
Subsequently, as shown in FIG. 4C, a NiCr film 13 and an Au film 14 serving as a power supply metal are formed on the back surface of the semiconductor substrate 1 so as to cover the wall surfaces of the via holes 3.
[0052]
Subsequently, the semiconductor substrate 1 is immersed in an Au-based plating solution in a predetermined plating bath, and a low-hardness Au plating film and a high-hardness Au plating film (both not shown) are sequentially plated and formed, and these are patterned. A first wiring layer 11 having a low hardness and a second wiring layer 12 having a high hardness as shown in FIG. 5A are formed, and the wiring 4 having a two-layer structure is manufactured. At this time, it is preferable to change the amount of plating current as a simple method of adjusting the hardness of the Au plating film. The hardness can be set to be high when the amount of plating current is large, and to be low when the amount of plating current is small.
[0053]
Subsequently, as shown in FIG. 5B, the grinding jig 52 is removed, and the cured protective film 51 is subjected to a peeling treatment and removed.
[0054]
Subsequently, as shown in FIG. 5C, the semiconductor device 1 is divided into chips, and an AuSn layer 15 used as a brazing material is formed so as to cover the wiring layer 12 and fill the via hole 3. The semiconductor substrate 1 is diced to the package 10 by the layer 15 to complete the MESFET as shown in FIG.
[0055]
As described above, according to the present embodiment, it is possible to prevent substrate breakage, disconnection, and the like, which are likely to occur in the substrate 1 in the vicinity of the via hole 3 formed in the compound semiconductor substrate 1, and to achieve extremely high reliability in manufacturing yield. A high MESFET is realized.
[0056]
-Modification-
Here, a modified example of the first embodiment will be described.
In this example, when forming the wiring structure, as shown in FIG. 7, the NiCr film 13 and the Au film 14 serving as the power supply metal are patterned and formed only in the via hole 3 and in the vicinity thereof. After forming a low hardness Au plating film only in the vicinity thereof, a resist pattern (not shown) used for patterning the NiCr film 13 and the Au film 14 is removed, and a high hardness Au plating film is formed. By patterning the film, the first wiring layer 11 having a low hardness and the second wiring layer 12 having a high hardness are formed, and the wiring 4 having a two-layer structure is manufactured.
[0057]
Also in the case of this example, as in the first embodiment, by forming the wiring 2 having the two-layer structure, stress is reduced and the Sn component of the AuSn layer 15 which is a dicing material is changed to the second wiring. Diffusion into the layer 12 is prevented, substrate breakage, disconnection, and the like, which tend to occur in the semiconductor substrate 1 near the via hole 3 formed in the compound semiconductor substrate 1, are prevented, and extremely high reliability with excellent manufacturing yield is obtained. MESFET is realized.
[0058]
(Second embodiment)
Next, a second embodiment of the present invention will be described. Here, a MESFET is illustrated as in the first embodiment, but is different in that a low hardness first wiring layer and a high hardness second wiring layer are formed apart from each other.
[0059]
-Wiring structure in via hole of semiconductor substrate-
In the present embodiment, a wiring structure formed in a via hole of a semiconductor substrate in a MESFET is disclosed as a main configuration. Therefore, first, the wiring structure will be described with reference to FIG.
[0060]
In the wiring structure according to the present embodiment, an Au electrode 2 formed by patterning an Au film formed by plating on the surface of a compound semiconductor substrate 1 made of GaAs or the like is formed, and the Au electrode 2 is electrically connected to the Au electrode 2. The wiring 22 is formed through a via hole 21 formed in the semiconductor substrate 1.
[0061]
The via hole 21 includes a surface hole 21a formed below the Au electrode 2 on the surface of the semiconductor substrate 1, and a back surface hole 21b formed from the back surface of the semiconductor substrate 1 so as to communicate with the surface hole 21a. .
[0062]
The wiring 22 is an Au wiring formed by a plating method, and includes a low-hardness wiring layer 11 formed in the front surface hole 21a and a high-hardness wiring layer 12 formed in a region including the back surface hole 21b. In a two-layer structure.
[0063]
Specifically, first, before forming the Au electrode 2, a Ti film 23 and an Au film 24 serving as a power supply metal for supplying a plating current are formed in the surface holes 21a. The first wiring layer 25 having a low hardness made of a low-hardness Au plating film is formed by patterning, and the Au electrode 2 is formed on the low-hardness wiring layer 25.
[0064]
On the other hand, a NiCr film 13 and an Au film 14 serving as a power supply metal for supplying a plating current are sequentially formed on the back surface of the semiconductor substrate 1 including the inside of the back surface hole 21b, and are formed on the Au film 14 by plating and patterning. A high hardness second wiring layer 26 made of a hard Au plating film is formed. In this manner, the first wiring layer 25 having a low hardness and the second wiring layer 26 having a high hardness are electrically connected via the power supply metal, and the wiring 22 having a two-layer structure having different hardness is configured. You.
[0065]
Then, an AuSn layer 15 used as a brazing material is formed so as to cover the wiring layer 12 and fill the back surface hole 21b, and the semiconductor substrate 1 is diced to the package 10 by the AuSn layer 15.
[0066]
In the wiring structure of the present embodiment, the first wiring layer 25 is provided in the front surface hole 21 a and the second wiring layer 26 having higher hardness than the first wiring layer 25 is provided in the back surface hole 21 b with respect to the via hole 21. Are laminated to form the wiring 22. From a structural point of view, a high-hardness second wiring layer 26 is formed on the semiconductor substrate 1 with the low-hardness first wiring layer 25 interposed therebetween. It functions as a buffer that relieves the stress applied to the Au electrode 2 formed thereon and the stress applied to the first wiring layer 25. Further, since the second wiring layer 26 is densely formed in proportion to its hardness, the Sn component of the AuSn layer 15 which is a dicing material to be formed on the second wiring layer 26 depends on the second wiring layer 26. Diffusion into the layer 26 is prevented, and the hardness of the second wiring layer 26 is maintained. Thus, the occurrence of substrate destruction due to stress concentration, and the prevention of disconnection of the wiring 4 and the depression of the Au electrode 2 due to the destruction are realized.
[0067]
-Configuration and manufacturing method of MESFET-
Hereinafter, a configuration and a manufacturing method of the MESFET based on the above-described wiring structure will be described. For convenience, the configuration of the MESFET will be described together with its manufacturing process. 9 to 11 are schematic cross-sectional views for illustrating a method of manufacturing the MESFET of the present embodiment in the order of steps, and particularly for explaining in detail a step of manufacturing a wiring structure.
[0068]
First, as in the first embodiment, as shown in FIGS. 3A and 3B, an AuGe connected to an overhang-shaped gate electrode 31 and source / drain electrodes is formed on a compound semiconductor substrate 1. The films 32 and 33 and the gate insulating film 34 are formed.
[0069]
Subsequently, as shown in FIG. 9A, a surface hole 21a is formed in the Au electrode formation site of the semiconductor substrate 1, and a Ti film 23 and an Au film 24 serving as a power supply metal are formed in the surface hole 21a. A low-hardness first wiring layer 25 made of a low-hardness Au plating film is formed on the Au film 24 by plating and patterning.
[0070]
Next, the Au electrode 2 is formed on the interlayer insulating film 41, the via holes 42 and 43, the source electrode 37, the drain electrode 38, and the low-hardness first wiring layer 25, respectively. 9A to 9C, only the Au electrode 2 is shown on the surface of the semiconductor substrate 1 for convenience, and the illustration of the interlayer insulating film 41 and the like is omitted.
[0071]
Subsequently, as shown in FIG. 9B, the semiconductor substrate 1 is fixed to a grinding jig 52 via a protective film 51 covering the Au electrode 2, and the back surface of the semiconductor substrate 1 is ground. Grinding is performed until the substrate thickness becomes about 20 to 300 μm in order to match the impedance of each semiconductor device.
[0072]
Subsequently, as shown in FIG. 9C, a back surface hole 21b having a tapered wall surface is formed on the back surface of the semiconductor substrate 1 so that a part of the surface of the Au electrode 2 is exposed. At this time, the front surface hole 21a and the back surface hole 21b communicate with each other to form the via hole 21.
[0073]
Next, a NiCr film 13 and an Au film 14 serving as a power supply metal are formed on the back surface of the semiconductor substrate 1 so as to cover the wall surface of the back surface hole 21b, and a high-hardness Au plating film is plated and patterned. Thereby, the second wiring layer 26 having high hardness is formed.
[0074]
Subsequently, the grinding jig 52 is removed, and the cured protective film 51 is subjected to a peeling process to remove it.
Then, the semiconductor device 1 is divided into chips, an AuSn layer 15 used as a brazing material is formed so as to cover the wiring layer 12 and fill the via holes 3, and the semiconductor substrate 1 is diced into the package 10 by the AuSn layer 15. To complete the MESFET as shown in FIG.
[0075]
As described above, according to the present embodiment, it is possible to prevent substrate breakage, disconnection, and the like, which are likely to occur in the substrate 1 in the vicinity of the via hole 3 formed in the compound semiconductor substrate 1, and to achieve extremely high reliability in manufacturing yield. A high MESFET is realized.
[0076]
In the first and second embodiments, the first wiring layers 11 and 25 having low hardness and the second wiring layers 12 and 26 having high hardness are formed by the electroplating method. It is not limited to a film forming method. For example, as a preferred example, in a combination of a first wiring layer having a low hardness and a second wiring layer having a high hardness, electroless plating-electroplating, electroplating-sputter, electroless plating-sputter, sputter-sputter, electric field Examples include plating-deposition, electroless plating-deposition, deposition-sputtering, and deposition-deposition.
[0077]
Further, for the first wiring layer and the second wiring layer, a combination of film-forming metals that sufficiently exhibit the above-described effects is selected from Au, AuGe, Cu, Pt, and Pd as low-hardness metals. A plating film is formed by using one or a plurality of kinds, and a plating film is formed by using one or more kinds selected from Au, AuGe, Cu, Pt, and Pd as a metal having high hardness. In this case, all possible combinations of metals of both hardnesses are suitable.
[0078]
Further, after plating film formation using one or more kinds selected from Au, AuGe, Cu, Pt, and Pd as low hardness metals, Au, AuGe, Cu, Pt, and high hardness metals are used. One or more selected from Pd may be used to form a multilayer plating film.
[0079]
Furthermore, after forming a plating film using Au or Cu as a low-hardness metal, sputtering is performed using one or more of Au, AuGe, Cu, Pt, and Pd as a high-hardness metal. Alternatively, a multilayer may be formed by vapor deposition growth.
[0080]
Further, after forming by sputtering using Au or Cu as the low hardness metal, sputtering is performed using one or more kinds selected from Au, AuGe, Cu, Pt and Pd as the high hardness metal. Alternatively, a multilayer may be formed by vapor deposition growth.
[0081]
Furthermore, after forming by vapor deposition using Au or Cu as a low-hardness metal, it may be formed by vapor deposition growth using one or more selected from AuGe, Pd, and Pt.
[0082]
Au, AuGe, Cu, Pt, and Pd having a thickness of 50 to 500 nm are used as the power supply metal in the electrolytic plating. By forming a film of Ti and NiCr before forming the power supply metal, the adhesion between the semiconductor substrate, the electrode, and the power supply metal can be enhanced. However, the thickness of Ti and NiCr in contact with the compound semiconductor substrate 1 and the Au electrode 2 itself is a source of stress, and therefore the thickness is desirably 200 nm or less. When the thickness of the low-hardness plating layer is 1 μm or more, the thickness of Ti and NiCr as adhesion strengthening is 200 nm at the maximum, or when the thickness of the low-hardness plating layer is 5 times or more, the stress of Ti and NiCr has No substrate destruction occurs.
[0083]
In the first and second embodiments, a GaAs substrate is exemplified as a compound semiconductor substrate, but an InP substrate or the like may be preferably used.
[0084]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the destruction of a board | substrate and disconnection which tend to occur in the vicinity of the connection hole formed in the compound semiconductor substrate are prevented, and the highly reliable semiconductor device excellent in manufacturing yield is realized.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view showing a wiring structure in a MESFET according to a first embodiment.
FIG. 2 is a schematic cross-sectional view showing a comparative example for comparing and studying with the wiring structure of the first embodiment.
FIG. 3 is a schematic cross-sectional view showing a method for manufacturing the MESFET of the first embodiment in the order of steps.
FIG. 4 is a schematic cross-sectional view showing a method of manufacturing the MESFET of the first embodiment (a step of manufacturing a wiring structure) in the order of steps, following FIG. 3;
FIG. 5 is a schematic cross-sectional view showing a method of manufacturing the MESFET of the first embodiment (a step of forming a wiring structure) in the order of steps, following FIG. 4;
FIG. 6 is a schematic sectional view showing the completed MESFET of the first embodiment.
FIG. 7 is a schematic sectional view showing a wiring structure in a modification of the MESFET of the first embodiment.
FIG. 8 is a schematic cross-sectional view showing a wiring structure in the MESFET of the second embodiment.
FIG. 9 is a schematic cross-sectional view for illustrating a method of manufacturing the MESFET of the second embodiment in the order of steps, and particularly for explaining in detail a step of manufacturing a wiring structure.
FIG. 10 is a schematic sectional view showing a completed MESFET of the second embodiment.
FIG. 11 is a schematic sectional view showing a conventional example of a semiconductor device having a via hole in a compound semiconductor substrate.
FIG. 12 is a schematic cross-sectional view showing a state in which the above-described fault has occurred in a compound semiconductor device by a conventional method.
[Explanation of symbols]
1 Compound semiconductor substrate
2 Au electrode
3,21,42,43 Via hole
4,16,22 wiring
10 packages
11,25 Low hardness first wiring layer
12,26 High Hardness Second Wiring Layer
13 NiCr film
14, 24, 36, 44, 45 Au film
15 AuSn layer
21a Surface hole
21b Back hole
23 Ti film
31 Overhang gate electrode
32,33 AuGe film
34 Gate insulating film
35 Ni film
37 source electrode
38 Drain electrode
41 Interlayer insulating film
51 Protective film
52 Grinding jig
53 resist pattern

Claims (24)

A compound semiconductor substrate having connection holes formed therein,
Wiring formed as a laminated structure in the connection hole,
An electrode formed on the compound semiconductor substrate and electrically connected to the wiring,
The laminated structure of the wiring includes a first wiring layer, said saw including a high hardness second wiring layers than the first wiring layer, the first wiring layer and the second wiring layer Semiconductor devices made of the same metal material . The connection hole is formed on a back surface of the compound semiconductor substrate,
2. The semiconductor according to claim 1, wherein the wiring has a structure in which the first wiring layer and the second wiring layer are stacked in the connection hole to form the stacked structure. 3. apparatus. The connection hole is formed such that a first hole formed on the front surface of the compound semiconductor substrate and a second hole formed on the back surface of the compound semiconductor substrate communicate with each other;
2. The device according to claim 1, wherein the first wiring layer is formed in one of the first hole and the second hole, and the second wiring layer is formed in the other. 13. The semiconductor device according to claim 1. 4. The semiconductor device according to claim 1, wherein the first wiring layer and the second wiring layer are both metal films formed by a plating method. 5. The semiconductor device according to claim 1, wherein the first wiring layer and the second wiring layer are formed by different growth methods. Forming a connection hole in the compound semiconductor substrate;
Forming a first wiring layer in a region including the inside of the connection hole;
Look including the step of forming the first second wiring layer higher hardness than that of the first wiring layer on the surface of the wiring layer,
A method for manufacturing a semiconductor device, wherein the first wiring layer and the second wiring layer are formed from the same metal material . Forming the connection hole on the back surface of the compound semiconductor substrate;
7. The method according to claim 6 , wherein the wiring is formed such that the first wiring layer and the second wiring layer are stacked in the connection hole. The connection hole,
A first hole is formed on the front surface of the compound semiconductor substrate, and a second hole is formed on the back surface of the compound semiconductor substrate, so that the first hole and the second hole communicate with each other. And
7. The method according to claim 6 , wherein the first wiring layer is formed in one of the first hole and the second hole, and the second wiring layer is formed in the other. A method for manufacturing a semiconductor device. 9. The method according to claim 6 , further comprising: forming an electrode on the compound semiconductor substrate so as to be electrically connected to the first wiring layer and the second wiring layer. 9. The method for manufacturing a semiconductor device according to claim 1. The method according to claim 6 , wherein the first wiring layer and the second wiring layer are formed by different growth methods. Forming a connection hole in the compound semiconductor substrate;
Forming a first wiring layer in a region including the inside of the connection hole;
Look including the step of forming the first second wiring layer higher hardness than that of the first wiring layer on the surface of the wiring layer,
At least one of the first wiring layer and the second wiring layer is formed by a plating method, and when the plating method is performed, a supply amount of a plating current is controlled, so that the first wiring layer and / or the second wiring layer are formed. Alternatively, a method for manufacturing a semiconductor device, comprising adjusting the hardness of the second wiring layer . Forming the connection hole on the back surface of the compound semiconductor substrate;
12. The method according to claim 11 , wherein the wiring is formed such that the first wiring layer and the second wiring layer are stacked in the connection hole. The connection hole,
A first hole is formed on the front surface of the compound semiconductor substrate, and a second hole is formed on the back surface of the compound semiconductor substrate, so that the first hole and the second hole communicate with each other. And
12. The device according to claim 11 , wherein the first wiring layer is formed in one of the first hole and the second hole, and the second wiring layer is formed in the other. A method for manufacturing a semiconductor device. 14. The method according to claim 11 , further comprising: forming an electrode on the compound semiconductor substrate so as to be electrically connected to the first wiring layer and the second wiring layer. 9. The method for manufacturing a semiconductor device according to claim 1. The method according to any one of claims 11 to 14 , wherein both the first wiring layer and the second wiring layer are formed by the plating method. 16. The semiconductor device according to claim 11 , further comprising a step of forming a plating electrode before forming the first wiring layer when performing the plating method. Production method. 17. The method according to claim 16 , wherein the plating electrode is formed to a predetermined thickness of 200 nm or less. Forming a connection hole in the compound semiconductor substrate;
Forming a first wiring layer in a region including the inside of the connection hole;
Look including the step of forming the first second wiring layer higher hardness than that of the first wiring layer on the surface of the wiring layer,
The first wiring layer and the second wiring layer are both formed by a plating method, and when the plating method is performed, the first wiring layer is formed with a higher plating current than when the second wiring layer is formed. A method for manufacturing a semiconductor device, characterized by forming a semiconductor device by supplying a small amount of silicon. Forming the connection hole on the back surface of the compound semiconductor substrate;
19. The method according to claim 18 , wherein the wiring is formed such that the first wiring layer and the second wiring layer are stacked in the connection hole. The connection hole,
A first hole is formed on the front surface of the compound semiconductor substrate, and a second hole is formed on the back surface of the compound semiconductor substrate, so that the first hole and the second hole communicate with each other. And
19. The method according to claim 18 , wherein the first wiring layer is formed in one of the first hole and the second hole, and the second wiring layer is formed in the other. A method for manufacturing a semiconductor device. 21. The method according to claim 18 , further comprising forming an electrode on the compound semiconductor substrate so as to be electrically connected to the first wiring layer and the second wiring layer. 9. The method for manufacturing a semiconductor device according to claim 1. 22. The method according to claim 18 , wherein when performing the plating method, the hardness of the first wiring layer and the second wiring layer is adjusted by controlling a supply amount of a plating current. 2. The method for manufacturing a semiconductor device according to claim 1. 23. The semiconductor device according to claim 18 , further comprising a step of forming a plating electrode before forming the first wiring layer when performing the plating method. Production method. 24. The method according to claim 23 , wherein the plating electrode is formed to a predetermined thickness of 200 nm or less.

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