JP3575922B2 - Spread spectrum wireless communication equipment - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a radio communication apparatus used in a radio communication system such as an automobile / cellular phone system, a cordless telephone system, a wireless LAN system, etc., and particularly to a code division multiple access (CDMA: Code) using a spread spectrum communication system. The present invention relates to a spread-spectrum wireless communication device used in a system capable of Division Multiple Access (Communication).
[0002]
[Prior art]
2. Description of the Related Art In recent years, as one of communication systems used in a mobile communication system, a spread spectrum communication system that is resistant to interference and interference has attracted attention.
In a wireless communication system using a spread spectrum communication system, for example, a transmitting device first converts digitized voice data or image data into a wideband baseband signal using a spreading code. As the spreading code, a pseudo noise code (PN code; pseudorandom noise code) or a Gold code is used. Next, the radio carrier is digitally modulated by the converted transmission baseband signal, and then the modulated wave signal is filtered by a bandpass filter and then transmitted from the antenna. For example, BPSK or QPSK modulation is used as the digital modulation.
[0003]
On the other hand, the receiving device mixes the received radio frequency signal with the local oscillation signal and frequency-converts it into a baseband signal, and then passes the received baseband signal through a low-pass filter to remove unnecessary wave components. After removal, the signal is converted into a digital signal and input to the data demodulation unit. In the data demodulation unit, the digital reception signal is despread by using the same code as the spreading code used in the transmitting device, and the output signal is subjected to one symbol length of the reception data by the integral dump filter. The integrated data is integrated every time, and the integrated output is determined by the determination unit to restore the received data.
[0004]
By the way, in the method of symbol-integrating the despread digital received signal with the integral dump filter, the received signal level is sampled once for each chip of the spread code and added over one symbol length of the received signal. There is something to do. In this method, for example, assuming that the symbol rate of the received signal is 19.2 KHz and the chip rate of the spread code is 1.23 MHz, 64 received signal level sample values are mutually added. However, in this method, when the cutoff characteristic of the reception filter provided in the radio unit is not steep, the reception quality is likely to deteriorate due to the influence of the tone interference wave.
[0005]
On the other hand, as another method of the integral dump filter, a received signal level is sampled at a sampling cycle of, for example, 4 to 8 times the chip rate for each chip of the spread code, and these sampled data are added over one symbol length of the received signal. There is something to do. In this method, for example, if the symbol rate of the received signal is 19.2 KHz, the chip rate of the spread code is 1.23 MHz, and the sample rate is 9.84 MHz (8 times the chip rate), then 64 × 8 = 512 received signals. The sample values of the levels are added together. In this method, the number of sample data can be increased as compared with the one-chip one-sample method described above, so that the influence of the tone interference wave can be reduced.
[0006]
For example, as shown in FIG. 8, when a 900 KHz tone interference wave is added to a radio frequency signal having a bandwidth of 1,25 MHz and a reception filter for removing the tone interference wave is not provided in the radio unit, FIG. 9 shows the relationship between the reception S / N and the frequency of the tone interference wave. As is apparent from this characteristic, the S / N characteristic (A) based on the one-chip eight-sample system is about 9 dB higher than the S / N characteristic (B) based on the one-chip one-sample system. .
[0007]
[Problems to be solved by the invention]
However, the integral dump filter to which such a one-chip multiple sample method is applied has the following problems to be solved. That is, when a clock phase shift occurs in the clock tracking unit, and the timing between the received signal and the received spread code shifts due to the influence, sampling data of the received signal in the period of the timing shift is input to the integration dump filter as noise. To the integrated value, and as a result, the reception quality deteriorates.
[0008]
The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent the influence of a clock phase shift from affecting the processing of the integral dump filter, thereby providing a tone interference wave and the like. It is an object of the present invention to provide a spread spectrum wireless communication device capable of maintaining a high reception quality with respect to a wireless communication.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a method for receiving a spread-spectrum radio signal, converting the frequency of the received radio signal into a baseband signal, and then performing sampling at an integer multiple of a chip rate of a spread code. Sampling, spectrum despreading of the sampled received signal by a spreading code, integration by a one-chip multiple-sampling integration dump filter, and determination of a level of the integrated output by a determination unit to reproduce information data. In a spread wireless communication device,
Data selection means is provided at a preceding stage of the integral dump filter, and the data selection means selects one chip length of the plurality of sampling data of the reception signal corresponding to the spread code every one chip long period. Only the sampling data of the central portion excluding the predetermined both ends during the period is selected, and the selected sampling data is integrated by the integration dump filter through the spectrum despreading process by the spreading code. is there.
[0010]
The data selection means includes a gate signal generation means and a reception signal gating means, and the gate signal generation means determines both end portions or both end portions determined according to the sampling period in one chip long period of the spread code. A gate signal representing a central portion excluding the above is generated, and based on the gate signal generated by the gate signal generating means, the reception signal is gated by the reception signal gating means. A signal may be subjected to a spectrum despreading process using the spreading code and integrated by the integration dump filter.
[0011]
Further, as another data selection means, in addition to the gate signal generation means described above, a spread code gate means is provided, and based on the gate signal generated by the gate signal generation means, the spread code is generated by the spread code gate means. It is conceivable that gate processing is performed and the spread code after the gate processing is subjected to spectrum despreading processing of the received signal.
[0012]
As a result, according to the present invention, for example, even if the clock phase of the clock tracking unit is shifted and the timing between the received signal and the received spread code is shifted due to the influence, the sampling data of the received signal in the period of the timing shift is Only the sampling data which is removed by the data selecting means and which is not affected by the timing shift is input to the integral dump filter. For this reason, the integration dump filter can perform the integration processing of the received sampling data without being affected by the above-mentioned timing deviation, thereby making it possible to perform the determination of the information data with high accuracy and to maintain the reception quality high. It becomes possible.
[0013]
In addition, since the data selection processing is performed by the gate processing of the received signal or the spreading code in the preceding stage of the integration dump filter, the existing integration dump filter can be used as it is, thereby allowing the gate processing in the integration dump filter. , The circuit configuration or the integration process can be simplified.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
FIG. 1 is a circuit block diagram showing a configuration of a receiving system of a spread spectrum wireless communication apparatus according to the first embodiment of the present invention.
[0015]
In FIG. 1, a radio signal received by an antenna 1 is low-noise amplified by an analog front end 2 and frequency-converted into a baseband band, and then predetermined by an analog / digital converter (A / D) 3. Is sampled at a sampling rate of At this time, the sampling rate is set to, for example, eight times the chip rate of the PN code. The received signal sampled by the A / D converter 3 is input to three data demodulators 4, 5, 6 and a search receiver 7, which are called finger circuits.
[0016]
The data demodulators 4, 5, and 6 spread and demodulate the transmission data transmitted from the base station according to the PN synchronization information captured by the search receiver 7. Each symbol data demodulated by these data demodulators 4, 5, and 6 is input to a symbol combiner 8 together with synchronization information. The symbol combiner 8 combines the integrated outputs of the received signals output from the data demodulators 4, 5, and 6 to reproduce a data component, and supplies the reproduced data component to the data determination unit 9. The data determination section 9 reproduces the received data by performing the level determination of the reproduction data component and the like.
[0017]
The reason why the three data demodulators 4, 5, and 6 are provided is to receive a multipath received signal at a high SN ratio by using a path diversity effect and to set a base station of a connection destination to a wireless channel during communication. This is for performing a so-called soft handoff that is switched without disconnection.
[0018]
The search receiver 7 performs a PN search on a pilot signal broadcast from a base station, and has basically the same configuration as the data demodulators 4, 5, and 6. The power control data obtained by the PN search operation of the search receiver 7 is notified to a microprocessor (not shown). The microprocessor has a PN search control function in addition to the usual various control functions related to the operation of the mobile station, and performs the PN search control based on the power control data.
[0019]
The data demodulators 4, 5, and 6 generate independent clocks using the sampling clock of the A / D converter 3 as a reference clock, and operate independently of each other using the unique clocks. Is composed of
[0020]
FIG. 2 is a circuit block diagram showing the configuration. That is, each of the data demodulators 4, 5, and 6 includes a data demodulation unit 10, an initial acquisition unit 20, a clock tracking unit 30, a PN code generator 40, and a voltage controlled oscillator (VCO) 50. .
[0021]
First, the initial acquisition unit 20 performs an initial acquisition operation of PN code synchronization by, for example, a sliding correlation method. Every time an integrated value for a predetermined symbol of a received signal is obtained, the initial phase of the PN code is set to １ ／ to 〜. By shifting one chip at a time, when the reception power level equal to or higher than the predetermined level is observed, the synchronization acquisition operation is shifted to the clock tracking unit 30.
[0022]
That is, the received signal is multiplied by the PN code generated from the PN code generator 40 in the multiplier 21 and despread, and then a predetermined symbol of the output signal is integrated by the integration dump filter 22. The integrated value, that is, the correlation output between the received signal and the PN code is converted to a power value by squaring in the squarer 23, and then input to the threshold comparator 24. At 24, it is compared to a threshold. The mode setting unit 25 sets the mode to the initial acquisition mode and sets the changeover switch 26 to the initial acquisition unit 20 side until the threshold comparison unit 24 detects a received power value equal to or greater than the threshold. . On the other hand, when a received power value equal to or greater than the threshold is detected, the mode is shifted from the initial acquisition mode to the clock tracking mode, and the changeover switch 26 is switched to the clock tracking unit 30 side.
[0023]
The clock tracking unit 30 performs a clock tracking operation using the PN code Early and the PN code Late generated separately from the PN code from the PN code generator 40 as follows.
[0024]
That is, the PN code generator 40 outputs a PN code Early having a phase advanced by チ ッ プ chip with respect to the PN code supplied to the initial capturing section 20 and a PN code Late having a phase delayed by チ ッ プ chip. You. FIG. 3 shows the phase relationship between these PN codes. The received signal is multiplied by the PN code Early and the PN code Late by multipliers 31 and 32, respectively, and despread, and then predetermined symbols of each output signal are integrated by integration dump filters 33 and 34, respectively. Then, the respective integrated values, that is, the correlation outputs of the received signal and the PN code Early and the PN code Late are squared by the squarers 35 and 36, respectively, converted into power values, and then mutually converted by the adder 37. Is added. Then, the added output signal is smoothed by the loop filter 38 and then supplied to the voltage controlled oscillator (VCO) 50 via the switch 26 as a clock phase variable instruction signal.
[0025]
FIG. 4 shows an example of a signal waveform obtained in the initial acquisition unit 20 and the clock tracking unit 30. FIG. 4A shows the phase of the PN code generated from the PN code generator 40 of the PN code of the received signal. This is the power value of the PN code correlation output output from the squarer 23 of the initial acquisition unit 20 when the phase matches the phase. On the other hand, (b) and (c) are output from the squarers 35 and 36 of the clock tracking unit 30 when the phases of the PN code Early and the PN code Late respectively match the phase of the PN code of the received signal. (D) is the power value of the correlation output output from the adder 37 of the clock tracking unit 30.
[0026]
Accordingly, for example, if the power value of the correlation output output from the adder 37 of the clock tracking unit 30 is at the position A in FIG. 4D, the clock phase is delayed from the clock tracking unit 30 to the VCO 50. Is supplied. Therefore, the phase of the PN code generated from the PN code generator 40 changes in the delay direction, whereby the correlation output level of the adder 37 moves from the position A to the position B. On the other hand, when the power value of the correlation output of the adder 37 is at the position C in FIG. 4D, an instruction signal for advancing the clock phase is supplied from the clock tracking unit 30 to the VCO 50. You. For this reason, the phase of the PN code generated from the PN code generator 40 changes in the leading direction, whereby the correlation output level of the adder 37 moves from the position C to the position B.
[0027]
The position B is a position where the output level of the demodulated data component output from the integration dump filter 13 of the data demodulation unit 10 described later becomes the maximum, as apparent from FIG. The PN code generation phase of the PN code generator 40 is controlled via the VCO 50 so that the peak of the correlation output level of the device 37 approaches the position B.
[0028]
The data demodulation unit 10 includes a gate circuit 11, a multiplier 12, an integration dump filter 13, and a gate signal generation circuit 14.
The gate signal generation circuit 14 generates a gate signal based on the PN code generated from the PN code generator 40 and the sampling clock output from the A / D converter 3. The gate signal is a signal that is at the “H” level only during the remaining central portion, except for both ends of the PN code for one chip length and one clock length of the sampling clock. That is, when the sampling clock rate is set to eight times the chip rate of the PN code, as described above, the gate signal generation circuit 14 outputs the PN code of the PN code as shown in FIG. For each chip length, a gate signal is generated in which both ends are at "L" level for 1/8 chip length and the remaining central portion is at "H" level.
[0029]
The gate circuit 11 includes, for example, an AND gate, and is in a non-conductive state when the gate signal is at the “L” level, and is in a conductive state when the gate signal is at the “H” level. Then, the reception signal input during the “H” level period is passed. The multiplier 12 multiplies the received signal passed through the gate circuit 11 by the PN code generated from the PN code generator 40 to perform spectrum despreading, and inputs the output to the integration dump filter 13. The integration dump filter 13 integrates the input despread sampled data over one symbol period, and outputs the integrated addition value to the symbol combiner 8.
[0030]
Next, the operation of the data demodulation unit 10 in the spread spectrum wireless communication apparatus configured as described above will be described. Here, for the sake of simplicity, the information data to be transmitted is assumed to be all "1", and the base station on the transmitting side transmits the information data using a PN code in which "1" and "0" appear alternately. A case will be described as an example in which transmission is performed after spreading. At this time, the transmission signal waveform transmitted from the base station is as shown in FIG.
[0031]
When the transmission signal is received by the analog front end 2 via the antenna 1, the received signal is sampled by the A / D converter 3 at a sampling rate eight times the chip rate of the PN code. FIG. 5B shows the sampled reception signal (reception sampling data). On the other hand, at this time, a PN code is generated from the PN code generator 40 in synchronization with the received signal as shown in FIG.
[0032]
Then, in the data demodulation unit 10, in the gate signal generation circuit 14, based on the PN code and the sampling clock of the A / D converter 3, each chip period of the received PN code as shown in FIG. A gate signal whose both ends are at the “L” level for one sampling clock and at the “H” level during the other period is generated and supplied to the gate circuit 11. Therefore, in the gate circuit 11, according to the gate signal, the conductive state is maintained only during the “H” level period, and the received sampling data input during this period passes through and is input to the multiplier 12. FIG. 5E shows reception after the gate.
[0033]
The multiplier 12 multiplies the gated reception signal by the PN code and despreads the spectrum, and inputs the despread reception signal to the integration dump filter 13. In the integral dump filter 13, the input received signal (received sampling data) is integrated and added over one symbol period. Then, the integrated added value is input to the symbol combiner 8 as a demodulated data component, where it is combined with the integrated added value similarly output from another data demodulator, supplied to the data determination unit 9, and subjected to level determination. You.
[0034]
By the way, in such a state, a clock phase shift occurs in the clock tracking unit 30 due to, for example, a change in a wireless transmission path, and accordingly, the phase of the PN code with respect to the received signal becomes, for example, as shown in FIG. Suppose that it has shifted in the delay direction or the advance direction as shown in g). Then, when the multiplier 12 multiplies the reception signal by the PN code and performs spectrum inverse conversion, the reception sampling is performed in the phase shift section (the hatched section in FIGS. 5F and 5G) between the reception signal and the PN code. If data exists, noise is generated during a period corresponding to the hatched section of the received signal after the spectrum inverse conversion, and this noise is integrated and added by the integration dump filter 13 to cause deterioration of reception quality.
[0035]
However, in the configuration of this embodiment, as described above, the gate circuit 11 removes the portion of the received signal that is affected by the phase shift by gating in advance and removes the remaining portion that is not affected by the phase shift. Only the spectrum is despread by the multiplier 12 and then input to the integration dump filter 13 for integration and addition. Therefore, even if a phase shift occurs between the received signal and the PN code as described above, it is possible to eliminate the effect and maintain high reception quality.
[0036]
As described above, in this embodiment, the gate circuit 11 and the gate signal generation circuit 14 are provided in the data demodulation unit 10 before the multiplier 12 for spectrum despreading. Then, a gate signal is generated in which both ends become "L" level for one sampling clock and become "H" level in other periods. Then, the gate circuit 11 is gate-controlled by the gate signal, thereby removing a portion of the received signal that is affected by the phase shift. The received signal after the gate processing is spectrally despread by the multiplier 12 using a PN code. After that, the signal is input to the integral dump filter 13 to perform integral addition processing.
[0037]
Therefore, even if the phase shift of the PN code with respect to the received signal occurs due to the clock phase shift of the clock tracking unit 30, the influence can be eliminated and the reception quality can be kept high. In this embodiment, since the present invention is realized by newly adding the gate circuit 11 and the gate signal generation circuit 14 to the data demodulation unit 10, the existing multiplier 12 and integral dump filter 13 are used as they are. And can be realized with a relatively simple circuit configuration.
[0038]
(Second embodiment)
According to a second embodiment of the present invention, a gate process is performed on a PN code, a spread spectrum process is performed on a received signal using the gated PN code, and an output signal of the received signal is input to an integration dump filter and integrated and added. It is intended to be.
[0039]
FIG. 6 is a circuit block diagram showing a configuration of the data demodulation unit 100 according to this embodiment. 2, the same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description is omitted.
[0040]
The PN code generated from the PN code generator 40 is input to the gate circuit 15 before being input to the multiplier 12. The gate circuit 15 is made up of an AND gate, and is turned on in response to the gate signal generated from the gate signal generation circuit 14, whereby the PN code is gate-controlled and input to the multiplier 12. The gate signal is generated based on the PN code and the sampling clock of the A / D converter 3 as in the above-described embodiment. As shown in FIG. 7D, the gate signal is generated for each chip period of the received PN code. The signal at both ends is at the “L” level for one sampling clock, and at the “H” level during the other periods.
[0041]
With such a configuration, the PN code (FIG. 7C) generated from the PN code generator 40 is input to the gate circuit 15 by the gate signal (FIG. 7D) before being input to the multiplier 12. ), Whereby a portion of the received signal (FIG. 7B) which is affected by the phase shift of the PN code is removed in advance. FIG. 7E shows the signal waveform of the PN code after the gate. Therefore, the received signal after spectrum despreading by the multiplier 12 does not include the noise due to the phase shift, and therefore, the integration and dumping process that does not include the noise is also performed in the integration dump filter 13. .
[0042]
Therefore, also in the present embodiment, even if the phase shift of the PN code with respect to the received signal occurs due to the clock phase shift of the clock tracking unit 30, the influence is eliminated and the reception quality is not deteriorated and the reception of high S / N is achieved. It is possible to do.
[0043]
The present invention is not limited to the above embodiments. For example, in each of the above embodiments, the gate circuits 11 and 15 are provided before the multiplier 12 for spectrum despreading in order to realize a simple circuit configuration. Although the gate processing is performed, the gate signal may be supplied to the integration dump filter 13 and the integration and addition processing including the gate processing may be performed in the integration dump filter 13.
[0044]
In addition, the configuration of the gate circuit and the gate signal generation circuit, the insertion position of the gate circuit, the configuration of the data demodulation unit, the initial acquisition unit, and the clock tracking unit can be variously modified without departing from the gist of the present invention. Of course.
[0045]
【The invention's effect】
As described above in detail, in the present invention, the data selection means is provided at the preceding stage of the integration dump filter, and the data selection means makes it possible to provide a plurality of received signals corresponding to the spread code for every one chip long period of the spread code. Out of the sampled data, only the sampling data in the central portion excluding the predetermined both ends in the long term of one chip is selected, and the selected sampling data is subjected to the spectrum despreading process by the spreading code and the integration dump filter is used. Is used to perform the integration process.
Therefore, according to the present invention, even if the phase shift of the sampling clock occurs, the influence can be prevented from adversely affecting the processing of the integration dump filter, whereby the reception quality with respect to a tone interference wave or the like can be kept high. A spread spectrum wireless communication device can be provided.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram showing a configuration of a receiving system of a spread spectrum wireless communication apparatus according to a first embodiment of the present invention.
FIG. 2 is a circuit block diagram showing a configuration of a data demodulator of the device shown in FIG.
FIG. 3 is a diagram showing a phase relationship between three types of PN codes generated from the PN code generator shown in FIG. 2;
FIG. 4 is a signal waveform diagram for explaining a clock tracking operation by the data demodulator shown in FIG. 2;
FIG. 5 is a signal waveform diagram used for explaining the operation of the data demodulation unit shown in FIG. 2;
FIG. 6 is a circuit block diagram showing a configuration of a data demodulation unit of a spread spectrum wireless communication apparatus according to a second embodiment of the present invention.
FIG. 7 is a signal waveform diagram used for describing the operation of the data demodulation unit shown in FIG. 6;
FIG. 8 is a diagram showing spectra of a radio transmission wave and a tone interference wave.
FIG. 9 is a diagram showing S / N characteristics of a one-chip eight-sample system and a one-chip one-sample system.
[Explanation of symbols]
1. Antenna
2. Analog front end
3: Analog / digital converter (A / D)
4, 5, 6 ... data demodulator
7 Search receiver
8 ... Symbol synthesizer
9 ... Data determination unit
10, 100 ... data demodulation unit
11, 15 ... gate circuit
12 ... Multiplier
13 ... Integral dump filter
14 ... Gate signal generation circuit
20: Initial capture unit
21 Multiplier
22 ... Integral dump filter
23 ... Squaring machine
24: threshold value comparison unit
25… Mode setting section
26 ... Changeover switch
30: Clock tracking unit
31, 32 ... multiplier
33, 34 ... Integral dump filter
35, 36… Square device
37 ... Adder
38 ... Loop filter
40 ... PN code generator
50: Voltage controlled oscillator (VCO)

Claims (3)

The spread spectrum radio signal is received, the received radio signal is frequency-converted into a baseband signal, and then sampled at a sampling cycle that is an integral multiple of the chip rate of the spread code, and the sampled received signal is spread. A spread spectrum wireless communication apparatus that reproduces information data by performing spectrum despreading with a code, integrating with a one-chip multiple sample type integration dump filter, and determining the level of the integrated output with a determination unit.
For each one-chip long period of the spreading code, select only the sampling data of the central part excluding predetermined both ends during the one-chip long period from among the plurality of sampling data of the received signal corresponding to the period, A spread spectrum wireless communication apparatus comprising: data selection means for subjecting the selected sampling data to integration processing by the integration dump filter through spectrum despreading processing by the spreading code. The data selection means is
A gate signal generating means for generating a gate signal representing both end portions determined according to the sampling period or a central portion excluding the both end portions in one chip long period of the spread code,
The received signal is gated based on the gate signal generated by the gate signal generating means, and the gated received signal is subjected to spectrum despreading processing by the spread code and integrated by the integration dump filter. 2. The spread spectrum wireless communication apparatus according to claim 1, further comprising a reception signal gate unit. The data selection means is
A gate signal generating means for generating a gate signal representing both end portions determined according to the sampling period or a central portion excluding the both end portions in one chip long period of the spread code,
Spreading code gating means for subjecting the spread code to gate processing based on the gate signal generated by the gate signal generating means, and subjecting the spread code after the gate processing to spectrum despreading processing of the received signal. The spread spectrum wireless communication apparatus according to claim 1, wherein:

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