JP3568815B2 - Frame phase synchronization circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a frame phase synchronization circuit for synchronizing a clock phase of a PLL (phase locked loop) circuit or a frequency conversion circuit using a VCO (Voltage Controlled Oscillator) in a digital transmission device or the like, and also synchronizing the frame phase. Circuit.
[0002]
[Prior art]
A frame phase change circuit of a phase synchronization circuit for such an application is generally a frame phase change circuit via a memory such as an elastic store. However, it is required to add a slip control circuit that detects a slip that occurs when the input phase fluctuates and exceeds the memory capacity and forcibly changes the relationship between writing and reading of the memory.
[0003]
In order to meet such a request, for example, Japanese Patent Laid-Open Publication No. Hei 5-268684 proposes a "slip control circuit test method for a frame phase synchronizer". That is, a circuit for monitoring the relationship between writing and reading of the memory is added, and a circuit is provided for forcibly shifting the relationship between writing and reading when a slip is likely to occur. As shown in FIG. 8, a write counter 71 to which an input clock is input and a memory 72 to which an input frame is input are provided. Further, it has a slip control circuit 75, a read counter 74, a frequency division counter 73, a phase comparator 76, and a VCO 77.
[0004]
The input frame is written to the memory 72 in accordance with a write address generated from a write counter 71 operated by an input clock. The output frame is read from the memory 72 in accordance with a read address generated by a read counter 74 that operates on a clock obtained by dividing the output clock by the frequency divider 73. The slip control circuit 75 compares the write address with the read address, and if a slip is likely to occur, forcibly changes the relationship between the write address and the read address. The phase comparator 76 compares the input clock with the frequency-divided clock of the frequency-division counter 73 and inputs the output to the VCO 77, thereby obtaining the above-described output clock from the output of the VCO 77.
[0005]
Such a conventional technique is effective when the fluctuation of the input phase is smaller than the memory capacity. However, if the amount of change in the input phase exceeds the memory capacity, a slip occurs, and the data of the slipped frame becomes invalid. Also, the forced control of the read address at the time of slip detection involves a rapid change in the frame phase. If the amount of change in the input phase can be predicted, the occurrence of slip can be avoided by optimizing the memory capacity. However, in the case of a digital transmission path or the like, it is very difficult to predict the amount of phase fluctuation occurring in the transmission path. Further, there is a problem that the power consumption of the counter and the memory is larger than that of other circuits. Further, the slip control circuit requires a complicated circuit, and has a problem that the circuit scale is increased. A method using a microcomputer or the like for the slip control circuit is also conceivable, but the microcomputer is more expensive than a logic circuit.
[0006]
In order to solve such a problem, the present applicant has previously proposed a frame phase difference control circuit as shown in FIG. That is, it is composed of a flip-flop 41, a flip-flop 42, and a switch (selector) 43. The output frame is input to the D and D1 inputs of the flip-flops 41 and 42, and the output clock is input to the clock CK input of the flip-flop 41. The input frame is input to the clock CK input of the flip-flop 42, and the Q output of the flip-flop 41 is input to the D2 input. The outputs of Q1 and Q2 of the flip-flop 42 are input to the input terminals SELB and SELA of the switch 43. The output of the phase comparator is input to IN2 of the switch 43, and a VCO control voltage output is obtained from the output terminal OUT.
[0007]
FIG. 7 shows an operation timing chart of FIG. There are four types of H (high) / L (low) combinations of the output frame signal (a) and the delayed output frame signal (b) in FIG. 7, and they are divided into four sections i, j, k, and l in FIG. The switching signals for these sections i, j, k, and l are 00, 10, 11, and 01, respectively. It monitors which of the four sections the rising edge of the input frame signal is in, and if the phase of the output frame signal is ahead of the phase of the input frame signal, the output frequency of the VCO is temporarily changed. The phase is adjusted by lowering. When the phase of the output frame signal is behind the phase of the input frame signal, the phase is adjusted by temporarily increasing the output frequency of the VCO. That is, the value (switching control signal) obtained by latching the output frame signal (a) at the rising edge of the input frame signal by delaying the output frame signal (b) means the phase relationship at that time. Therefore, according to this value, the signal supplied to the VCO is switched as follows.
[0008]
In the section i: Since the output frame signal is in advance of the input frame signal, a fixed value “L” for lowering the output frequency of the VCO is selected.
[0009]
In the section j: Since the output frame signal is in phase with the input frame signal, the output of the phase comparator is supplied to the VCO without performing frame phase control.
[0010]
In the sections K and l: Since the output frame signal is behind the input frame signal, a fixed value “H” for increasing the VCO output frequency is selected by the switch.
[0011]
[Problems to be solved by the invention]
In the case of the above-mentioned conventional well-known technology, there are problems such as the difficulty of the slip generation circuit, the difficulty of predicting the phase fluctuation, the increase in power consumption of the circuit, and the increase in the scale and cost of the circuit configuration. Further, in the technique proposed earlier, the circuit configuration becomes relatively inexpensive, but when the section of the input frame phase changes from j to i, for example, the input of the VCO becomes a fixed value from the output of the phase comparator. Since the signal suddenly changes to "L", there is a problem that the output clock phase changes suddenly in response to this. Furthermore, in a high-speed data transmission device, a sudden clock phase change in the device causes a slip of data in the device and a jump in frame phase, so that a condition that the clock phase must be suppressed as much as possible is imposed.
[0012]
Accordingly, an object of the present invention is to reduce the amount of output phase fluctuation and reduce the amount of output phase fluctuations to reduce the amount of output phase fluctuations and to achieve higher quality synchronous data transmission in order to reduce sudden phase shifts in the device. Is to provide a circuit.
[0013]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the frame phase synchronization circuit according to the present invention employs the following characteristic configuration.
[0014]
(1) a phase comparator for comparing the phases of an input clock and an output clock, a VCO whose oscillation frequency is controlled by a control voltage, a frequency divider for dividing the output of the VCO to generate the output clock, A frame phase synchronization circuit including an output frame generation counter that counts an output clock of the VCO to generate an output frame, and a frame phase difference control circuit that receives the phase difference between an input frame and the output frame and controls the VCO. ,
A shift register that generates a plurality of delayed output frame signals delayed by a predetermined number of output clocks with respect to the output frame signal; and a shift register that outputs the delayed output frame signal to the input frame signal. A flip-flop which latches at the rising edge of the flip-flop to output the predetermined number of switching signals, and outputs one of a predetermined voltage predetermined based on the predetermined number of switching signals and an output from the phase comparator. A switch for selecting and outputting as the control voltage, setting a plurality of sections of a phase difference range between the input frame and the output frame, and generating a plurality of different VCO control voltages according to the phase difference. circuit.
[0015]
(2) The shift register according to (1), wherein the shift register generates three delayed output frame signals.
[0016]
(3) The frame phase synchronization circuit according to (1) or (2), wherein the DSP is controlled by an output of the frame phase difference control circuit using a DSP .
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a preferred embodiment of a frame phase synchronization circuit according to the present invention will be described in detail with reference to FIGS.
[0020]
FIG. 1 is a block diagram of a preferred embodiment of a frame phase synchronization circuit according to the present invention. FIG. 2 is a block diagram of a specific example of a frame phase difference control circuit which is a main part of FIG.
[0021]
As shown in FIG. 1, the frame phase synchronization circuit according to the present invention includes a phase comparator 11, a frame phase difference control circuit 15, a VCO 12, a frequency divider 13, and an output frame generation counter 14. The phase comparator 11 compares the input clock with the frequency-divided clock output from the frequency divider 13. For example, an exclusive-OR (EX-OR) circuit outputs a phase difference signal and supplies it to the frame phase difference control circuit 15. The VCO 12 outputs a clock signal having a frequency proportional to the voltage of the VCO control signal output from the frame phase difference control circuit 15 from the output terminal 16 as an output clock, and supplies the clock signal to the output frame generation counter 14 and the frequency divider 13. . The output frame counter 14 counts the output clock so as to generate an output frame synchronized with the output clock. The output of the output frame generation counter 14 is output from the output frame terminal 17 and supplied to the frame phase difference control circuit 15. The frequency divider 13 divides the frequency of the output clock signal to the input clock frequency and supplies the frequency to the phase comparator 11.
[0022]
Next, the frame phase difference control circuit 15 for controlling the output frame phase with respect to the input frame phase will be described. The frame phase difference control circuit 15 monitors whether or not the difference between the phase of the input frame and the phase of the output frame is within a predetermined range (for example, a range of 1/2 frame ± clock from the input frame). If it is within the specified range, the output of the phase comparator 11 is output to the VCO 12 as it is. If the difference is outside the specified range, the VCO 12 operates to output the VCO control voltage in the direction of reducing the frame phase difference to the VCO 12 in accordance with the phase difference.
[0023]
FIG. 2 is a block diagram of a specific example of the frame phase difference control circuit 15 of FIG. The frame phase difference control circuit 15 includes a shift register 1, a flip-flop 2, and a switching circuit (selector) 3. An output frame and an output clock are input to the D terminal and the CK terminal of the shifter register 1, respectively. Outputs from the three output terminals QA, QB, and QC of the shift register 1 are supplied to D1, D2, and D3 of the flip-flop 2, and an input frame is input to a CK terminal. The outputs of the three output terminals Q1, Q2, Q3 of the flip-flop 2 are input to the switching control terminals SELC, B, A of the switching circuit 3, respectively. The outputs of the phase comparator 11 are supplied to the input terminals INO, IN2 and IN5 of the switching circuit 3, and −0.5 V, −1.0 V, +0... To IN1, IN3, IN4, IN6 and IN7, respectively. Fixed values of 5V, + 1.0V and + 1.0V are input.
[0024]
Next, the circuit operation of FIGS. 1 and 2 will be described with reference to the timing chart of FIG. The shift register 1 generates delayed output frame signals 1 to 3 (see FIGS. 3B to 3D) which are delayed from the output frame signal (see FIG. 3A) by 1 to 3 clocks of the output clock. I do. The flip-flop 2 latches these delayed output frame signals 1 to 3 at the rising edge of the input frame signal, and supplies them to the switching control inputs SELC, B and A of the switching circuit 3. The switching circuit 3 selects and outputs any one of +1.0 V, +0.5 V, -0.5 V, -1.0 V, and the output of the phase comparator according to the three switching control signals. Note that +1.0 V, +0.5 V, −0.5 V, and −1.0 V are examples of the control voltage of the VCO 12. A positive voltage such as +1.0 V is a voltage value that increases the output frequency of the VCO 12. , −1.0 V means a voltage that lowers the output frequency of the VCO 12. The circuit example shown in FIG. 2 is an example in which the output frame phase difference with respect to the phase of the input frame is controlled to ± frame ± 1 clock width from the input frame. Needless to say, it can be set finely.
[0025]
The shift register 1, the flip-flop 2, and the switching circuit 3 of the frame phase difference control circuit 15 in FIG. 2 are well known to those skilled in the art, and are commercially available, and the detailed construction is omitted.
[0026]
The operation will be described in more detail. There are six combinations of “H” and “L” of the delayed output frame signals 1 to 3 in FIG. It is divided into six sections a, b, c, d, e, and f in FIG. 3, and generates switching signals 011, 001, 000, 100, 110, and 111, respectively (see FIG. 3).
[0027]
Therefore, it is monitored in which of the sections a to f the rising edge of the frame signal is located. As a result of the monitoring, when the phase of the output frame signal is ahead of the phase of the input frame signal, the frame frequency is adjusted by lowering the output frequency of the VCO 12. If the phase of the output frame signal is behind the phase of the input frame signal, the frame phase is adjusted by increasing the VCO output frequency with a positive VCO control voltage. That is, the switching control signal which is a value obtained by latching the output frame signal and the delayed frame signal at the rising edge of the input frame signal means the phase relationship at that time. Accordingly, the signal supplied to the VCO 12 is switched as follows.
[0028]
In the section a: Since the output frame signal is greatly advanced with respect to the input frame signal, -1.0 V is selected to lower the output frequency of the VCO.
In the case of the section b: The output frame signal is slightly advanced with respect to the input frame signal, but -0.5 V is selected as the VCO control voltage to lower the VCO output frequency.
[0029]
In the section c: Since the output frame signal is in a phase opposite to the input frame signal (here, a steady state), the frame phase difference control is not performed, and the output of the phase comparator 11 is supplied to the VCO 12 as it is. .
[0030]
In the section d: Since the output frame signal is slightly delayed from the input frame signal, +0.5 V is selected as the VCO control voltage to increase the VCO output frequency.
[0031]
In the section e: the output frame signal is significantly delayed with respect to the input frame signal, so that +1.0 V is selected as the VCO control voltage to increase the VCO output frequency.
[0032]
In the case of the section f: Since the output frame signal is in a state of being delayed or advanced in antiphase with respect to the input frame signal, in order to greatly change the VCO output frequency, +1.0 V or -1.0 V is set to either the VCO control voltage. However, in the example of FIG. 2, +1.0 V is selected.
[0033]
Next, another embodiment of the frame phase synchronization circuit according to the present invention will be described with reference to FIGS. The frame phase synchronization circuit of this embodiment uses a DSP (Digital Signal Processor). This DSP can be, for example, a device such as μPD7725 manufactured by NEC Corporation.
[0034]
FIG. 4 shows a block diagram of this frame phase synchronization circuit. This frame phase synchronization circuit includes a phase comparator 61, a phase difference counter 62, a DSP 63, a digital frequency control oscillator 64, a frequency divider 65, an output frame generation counter 66, and a frame phase difference control circuit 67. The input clock and the frequency-divided clock from the frequency divider 65 are input to the phase comparator 61, and the comparison result is output to the phase difference counter 62. The input of the input frame and the output of the output frame generation counter 66 are input to the frame phase difference control circuit 67, and the control output is supplied to the DSP 63. The output of the digital frequency controlled oscillator 64 is output to the output clock terminal 68 as an output clock, and is also input to the frequency divider 65 and the output frame generation counter 66. The output of the output frame generation counter 66 is output to the output frame terminal 69 as an output frame, and is also supplied to the frame phase difference control circuit 67 as described above.
[0035]
In the frame phase synchronization circuit of FIG. 4, the phase difference signal output from the phase comparator 61 is quantized by the phase difference counter 62. Further, the phase difference data from the phase difference counter 62 is supplied to the DSP 63, which performs smoothing, file processing, and the like by a program operating on the DSP 63, and outputs control data of the digital frequency oscillator 64.
[0036]
By adding an output frame generation counter 66 and a frame phase difference control circuit 67 to the frame phase synchronization circuit of FIG. 4 using the digital frequency oscillator 64, the same operation and effect as those of the preferred embodiment shown in FIGS. The effect is obtained. However, the output of the frame phase difference control circuit 67 becomes three switching control signals as shown in FIG. 2, which are supplied to the DSP 63, and the control data switching process to the digital frequency control oscillator 64 operates on the DSP 63. It is configured to incorporate a program.
[0037]
A schematic flowchart of the program incorporated in the DSP 63 is as shown in FIG. First, in step S1, the phase difference data from the phase comparator 61 is fetched from the phase difference counter 62. Next, the frame phase difference data described above is fetched from the frame phase difference control circuit 67 in step S2. In step S3, a digital filter operation is performed on the phase difference data. Subsequently, in step S4, a frame phase difference is determined. If the switching control signal is 011, the VCO control value is set to -1.0 V in step S5, and the VCO output frequency is reduced. If the switching control signal is 001, the VCO control value is set to -0.5 V in step S6 to slightly lower the VCO output frequency. If the switching control signal is 000, the VCO control value is set as the filter S output Xα in step S7. When the switching control signal is 100, the VCO control value is set to +0.5 V in step S8, and the VCO output frequency is slightly increased. Finally, when the switching control signal is 110 or 111, the VCO control value is set to +1.0 V in step S9 to increase the frequency of the VCO or the digital frequency controlled oscillator 64.
[0038]
The configuration and operation of the preferred embodiment of the frame phase synchronization circuit according to the present invention have been described above in detail. However, the present invention should not be limited to only such specific examples, and those skilled in the art can easily understand that various modifications can be made according to specific applications.
[0039]
【The invention's effect】
As will be understood from the above description, the frame phase synchronization circuit of the present invention has the following practically significant effects.
[0040]
First, it is possible to effectively prevent a frame from slipping with respect to a phase change of an input clock as compared with the related art. As a result, loss or superposition of the main signal can be prevented, and high-quality data transmission is possible. The reason is that the output frame is synchronized with the input frame by controlling the frequency of the output clock signal.
[0041]
Further, according to the frame phase synchronization circuit of the present invention, it is possible to reduce the cost and power consumption as compared with the prior art. The reason is that, compared to the prior art, it can be realized with a small-scale circuit and does not use a relatively expensive and large power consumption memory.
[0042]
Further, according to the present invention, since the increase and decrease of the frequency of the VCO or the digital frequency controlled oscillator are switched in a plurality of stages, the output phase is not sharply changed, and higher quality data transmission is possible. In other words, for relatively small input phase fluctuations, the output phase fluctuations are kept small.
[Brief description of the drawings]
FIG. 1 is a block diagram of a preferred embodiment of a frame phase synchronization circuit according to the present invention.
FIG. 2 is a specific example of a frame phase difference control circuit of the frame phase synchronization circuit of FIG. 1;
FIG. 3 is a timing chart illustrating an operation of the frame phase difference control circuit of FIG. 2;
FIG. 4 is a block diagram of another embodiment of the frame phase synchronization circuit according to the present invention.
FIG. 5 is a flowchart illustrating an example of a program operation of FIG. 4;
FIG. 6 is a block diagram of a frame phase difference control circuit previously proposed by the present applicant.
FIG. 7 is an operation explanatory diagram of the frame phase difference control circuit of FIG. 6;
FIG. 8 is a block diagram of a conventional frame phase synchronization circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Shift register 2 Flip-flop 3 Switching circuit 11 Phase comparator 12 VCO
13 frequency divider 14 output frame generation counter 15, 67 frame phase difference control circuit 63 DSP

Claims (3)

A phase comparator for comparing the phases of the input clock and the output clock, a VCO whose oscillation frequency is controlled by a control voltage, a frequency divider for dividing the output of the VCO to generate the output clock, An output frame generation counter that counts an output clock and generates an output frame, and a frame phase synchronization circuit that includes a frame phase difference control circuit that receives the phase difference between an input frame and the output frame and controls the VCO,
A shift register that generates a plurality of delayed output frame signals delayed by a predetermined number of output clocks with respect to the output frame signal; and a shift register that outputs the delayed output frame signal to the input frame signal. A flip-flop which latches at the rising edge of the flip-flop to output the predetermined number of switching signals, and outputs one of a predetermined voltage predetermined based on the predetermined number of switching signals and an output from the phase comparator. A switch for selecting and outputting the control voltage, setting a plurality of sections of a phase difference range between the input frame and the output frame, and generating a plurality of different VCO control voltages according to the phase difference. Frame phase synchronization circuit. 2. The circuit according to claim 1, wherein the shift register generates three delayed output frame signals. 3. The frame phase synchronization circuit according to claim 1, wherein the DSP is controlled by an output of the frame phase difference control circuit using a DSP.

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