JP3557225B2 - Digital image signal receiving / reproducing device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a digital image signal receiving / reproducing device, and more particularly to a device capable of correcting error data without using an error correction code.
[0002]
[Prior art]
When recording / reproducing a digital image signal by, for example, a VTR, it is common to perform error correction encoding as a measure against errors. As error correction codes, simple parity, Reed-Solomon codes, and combinations of these with interleaving have been put to practical use.
[0003]
[Problems to be solved by the invention]
However, in the case of an error correction code, if the error correction capability is to be improved, the number of parities increases, and the redundancy increases. If the error cannot be corrected, a concealment circuit for interpolating the erroneous pixel with surrounding correct pixel data is required. Data such as computer software is generally uncorrelated. However, in the case of image signals, there are spatial and temporal correlations.
[0004]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a digital image signal receiving / reproducing apparatus capable of correcting an error without using an error correction code, paying attention to the existence of a spatial correlation of the image signal.
[0005]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided an apparatus for receiving / reproducing a received or reproduced digital image signal.
A plurality of pixels at predetermined positions temporally or spatially close to the target pixel to be detectedTemporal or spatial correlation of valuesA class information output circuit that outputs class information based on
A memory circuit stored in advance that is prepared by training and that stores existence area data indicating an area where pixel data can exist in accordance with the class information,
A read circuit for reading the existence area data of the corresponding class of the memory circuit from the output of the class information output circuit;
A comparison circuit that compares the existence area data with the pixel data of the pixel of interest,
A digital image signal receiving / reproducing apparatus for detecting the presence or absence of an error based on an output of a comparison circuit.
[0006]
According to a second aspect of the present invention, in the above digital image signal receiving / reproducing apparatus,
Memory circuitToIsAccording to the class information prepared in advance by trainingrepresentativevalueStored,When the comparison circuit determines that the pixel data of the target pixel is out of the range of the existence area data, the representative value corresponding to the pixel data of the target pixel is determined.A digital image signal receiving / reproducing apparatus characterized by outputting.
[0007]
According to a third aspect of the present invention, in the above digital image signal receiving / reproducing apparatus,
The class information output circuit includes a plurality of pixels adjacent to the decoded target pixel.Temporal or spatial correlation of valuesA digital image signal receiving / reproducing apparatus characterized in that class information is output based on the digital image signal.
[0008]
According to a fourth aspect of the present invention, in the above digital image signal receiving / reproducing apparatus,
Digital image signal received or reproducedIs a digital image signal receiving / reproducing apparatus characterized in that DCT coefficient data is a signal obtained by performing variable length coding.
[0009]
According to a fifth aspect of the present invention, in the above digital image signal receiving / reproducing apparatus,
classInformation outputThe circuit has an ADRC encoding circuit that performs ADRC encoding on input pixel data,
ADRC code performedpluralBased on the pixel data,Output class informationA digital image signal receiving / reproducing apparatus characterized in that:
[0010]
According to a sixth aspect of the present invention, in the above digital image signal receiving / reproducing apparatus,
The existence area data is a digital image signal receiving / reproducing apparatus characterized in that it is a maximum value and a minimum value of a plurality of true values detected in training for each class.
[0011]
According to a seventh aspect of the present invention, in the above digital image signal receiving / reproducing apparatus,
representativeValues used standard video dataA digital image signal receiving / reproducing apparatus characterized in that it is an average value for each class of a plurality of true values detected in training.
[0012]
The invention according to claim 8 is the digital image signal receiving / reproducing apparatus,
Memory circuitToIs for each classThe coefficient data is stored, and when an error is detected, a representative value corresponding to the pixel of interest is output by weight-adding a plurality of pixel data using the coefficient data.A digital image signal receiving / reproducing apparatus characterized in that:
[0013]
According to a ninth aspect of the present invention, in the above digital image signal receiving / reproducing apparatus,
The coefficient data minimizes the error for each class of a plurality of true values detected in training.A digital image signal receiving / reproducing apparatus characterized in that:
[0014]
According to a tenth aspect of the present invention, in the digital image signal receiving / reproducing apparatus of the eighth aspect,
In a predetermined periodThe comparison circuit has determined that the pixel data of the target pixel is out of the range of the existence area dataCounter circuit that counts the number of pixelsHas,
Based on the output of the counter circuitExistence area dataIs a digital image signal receiving / reproducing apparatus characterized in that the digital image signal is varied.
[0015]
[Action]
An error is detected stochastically by classifying the data from the data adjacent to the target pixel and comparing the signal level existing area of the current pixel prepared for each class with the actual level. The error can be corrected by replacing with a predicted value prepared for each.
[0016]
【Example】
Below,ClearAn embodiment will be described. FIG. 1 shows a schematic configuration of this embodiment, that is, signal processing of a digital VTR. A digital video signal, for example, a signal in which one sample is quantized to 8 bits is supplied from an input terminal denoted by reference numeral 1. This digital video signal is supplied to the blocking circuit 2. In this embodiment, in the blocking circuit 2, the effective area of one field or one frame is divided into DCT blocks having a size of (8 × 8) pixels.
[0017]
The digital video signal scan-converted in the order of blocks from the blocking circuit 3 is supplied to a DCT (Discrete Cosine Transform) circuit 3. The DCT circuit 3 generates coefficient data composed of one DC component and 63 AC components. The coefficient data is supplied to the quantization circuit 4. In the quantization circuit 4, the coefficient data is requantized with a desired quantization step width, and the number of data bits is reduced. The output of the quantization circuit 4 is supplied to a VLC (variable length code) coding circuit 5, where it is subjected to variable length coding processing such as run length coding and Huffman coding, and is further compressed.
[0018]
The DC component data generated by the DCT circuit 3 is transmitted as it is without being processed by the quantization circuit 4 and the VLC encoding circuit 5 because the DC component data has a high importance for image restoration of the block. The framing circuit 6 configures the DC component, the variable-length coded data from the VLC coding circuit 5, and other control and ID data into continuous data of a synchronous block. Conventionally, error correction coding processing is performed at the time of framing, but in the present invention, error correction coding is not required.
[0019]
The output of the framing circuit 6 is supplied to the rotary head H via the recording circuit 7 and recorded on the magnetic tape T as an oblique track. The recording circuit 7 includes a channel encoding circuit, a recording amplifier, and the like. Channel encoding is a process for reducing the DC component of recording data. Typically, more than one rotating head is used, but for simplicity only one is shown.
[0020]
The reproduction data extracted from the magnetic tape T by the rotary head H is supplied to a reproduction circuit 11 including a reproduction amplifier, a channel decoding circuit, and the like, where channel encoding is decoded. The output data of the reproducing circuit 11 is supplied to the frame decomposing circuit 12, and various data are separated from the recording data. Output data of the frame decomposition circuit 12 is supplied to the VLC decoding circuit 13. The VLC decoding circuit 13 decodes variable-length coding.
[0021]
An inverse quantization circuit 14 is connected to the VLC decoding circuit 13. The inverse quantization circuit 14 performs processing opposite to the quantization of the quantization circuit 4 on the recording side. Output data of the inverse quantization circuit 14 is supplied to the inverse DCT circuit 15. The coefficient data is decoded by the inverse DCT circuit 15 into pixel data of (8 × 8) blocks. Output data of the inverse DCT circuit 15 is supplied to the block decomposition circuit 16. The block decomposition circuit 16 returns the data order from the block order to the raster scan order. Output data of the block decomposition circuit 16 is supplied to a correction circuit 17 according to the present invention. Output data is obtained at an output terminal 18 of the correction circuit 17.
[0022]
FIG. 2 shows an example of the correction circuit 17 according to the present invention. Reproduction data from the block decomposition circuit 16 is supplied to an input terminal 21. The reproduced data is supplied to the three-line memory 22, and the output data of the three-line memory 22 is supplied to the blocking circuit 23. The output data of the blocking circuit 23 is supplied to the ADRC encoding circuit 24.
[0023]
As shown in FIG. 4, when forming the block x1, the blocking circuit 43 forms the block x2, and then forms the block x3. That is, blocks shifted one pixel at a time in the horizontal direction are sequentially formed. A 3-line memory 22 is provided for forming overlapping blocks. In addition, when the formation of a block is completed for one line period and a new block is formed therebelow, a block shifted by one line is formed. One pixel at the center of each block is a target pixel for error detection and error correction.
[0024]
The ADRC encoder 24 detects a maximum value MAX, a minimum value MIN, and a dynamic range DR that is a difference between MAX and MIN of the pixel value for each block of 9 pixels, and quantizes the pixel value according to the dynamic range DR. I do. The ADRC encoding circuit 24 is an encoding circuit that generates 1-bit quantized data.
[0025]
FIG. 5 shows an example of the ADRC encoding circuit 24. In FIG. 5, a detection circuit 52 detects a maximum value MAX and a minimum value MIN for each block from data from an input terminal 51. MAX and MIN are supplied to the subtraction circuit 53, and a dynamic range DR is generated at the output. The input data and MIN are supplied to the subtraction circuit 54, and the minimum value is removed from the subtraction circuit 54, thereby generating normalized pixel data.
[0026]
The dynamic range DR is supplied to the division circuit 55, and the normalized pixel data is divided by the dynamic range DR, and is taken out to the output terminal 58 as quantized data DTx (for example, data to three decimal places). In FIG. 4, DTx1, DTx2, and DTx3 represent quantized data of blocks x1, x2, and x3. The output data of the division circuit 55 is supplied to the comparison circuit 56. The comparison circuit 56 determines whether the dividing power of the eight pixels other than the center pixel is larger or smaller based on 0.5. According to this result, data DT of '0' or '1' is generated. The comparison output DT is taken out to the output terminal 57.
[0027]
Returning to FIG. 2, DT in the output data of the above-mentioned 1-bit ADRC encoding circuit 24 is supplied to the synchronization circuit 25, and the quantized data DTx is supplied to the selector 26 and the comparison circuits 30 and 31. . As described above, the synchronizing circuit 25 synchronizes the comparison results DT of the eight pixels in the block excluding the pixel at the center position. Output data (8 bits) of the synchronization circuit 25, that is, class information is supplied to the memory 29a as a read address signal.
[0028]
As will be described later, the memory 29a stores existence area data (MAX # and MIN #) for each class formed in advance by training and a representative value (DTx #) predicted for each class. Given the class information from the synchronization circuit 25, the representative value corresponding to the class information is read from the memory 29a.
[0029]
Read representative value DTx # is supplied to selector 26. MAX # that has been read is supplied to comparison circuit 30, and MIN # is supplied to comparison circuit 31. The outputs of the comparison circuits 30 and 31 are supplied to the logic 32, and the logic 32 generates a control signal for controlling the selector 26. The comparison circuits 30 and 31 and the logic 32 function as a window comparator. That is, when MAX {<DTx <MIN}, since the quantized data DTx exists in the existence area, it is determined that the data DTx is not an error. DTx determines that an error has occurred.
[0030]
When there is no error, the selector 26 selects the output data DTx of the ADRC encoding circuit 24. When it is determined that there is an error, the selector 26 selects the read data DTx # from the memory 29a. Therefore, data DTx # is selected instead of the data determined to be in error. The selected output of the selector 26 and DR and MIN from the ADRC encoding circuit 24 are supplied to the ADRC decoding circuit 27.
[0031]
The ADRC decoding circuit 27 multiplies the dynamic range DR by the output data of the selector 26, and adds the minimum value MIN to the multiplication result, contrary to the above-described encoding. The output data with the error corrected is taken out to the output terminal 28 of the ADRC decoding circuit 27. As described above, the error pixel data can be corrected without using the error correction coding.
[0032]
The memory 29a stores existing area data created in advance by training and representative data predicted for each class. FIG. 3 shows a configuration at the time of training. In FIG. 3, a digital video signal is supplied to 41, which is supplied to a blocking circuit 43 via a three-line memory. The output of the blocking circuit 43 is supplied to the ADRC encoding circuit 44.
[0033]
The three-line memory 42, the blocking circuit 43, and the ADRC encoding circuit 44 are similar to the three-line memory 22, the blocking circuit 23, and the ADRC encoding circuit 24 of the correction circuit 17 described above. However, the input data is preferably standard video data for training, and for example, a signal composed of still images of various patterns can be adopted. The comparison output DT output from the ADRC encoding circuit 44 is supplied to the synchronization circuit 45, and the quantized data DTx is supplied to the memory 46a as its data input. The synchronizing circuit 45 parallelizes the comparison outputs of the other eight pixels except for the central pixel of the 3 × 3 block, similarly to the synchronizing circuit 25 described above.
[0034]
Eight bits from the synchronization circuit 45 are supplied to the memory 46a as its write address. The read address of the memory 46a is formed by an address counter 47. The write address for the memory 46a is 8-bit class information from the synchronization circuit 46, and the quantized data DTx of the central pixel actually obtained for each of the 256 classes is written in the memory 46a. Be included.
[0035]
When the writing is completed, data of each address (that is, each class) of the memory 46a is read from the memory 46a by the read address from the address counter 47. The read address is incremented from 0 to 255. The read data is supplied to the averaging circuit 48 and the detection circuit 49. The averaging circuit 48 predicts the representative value DTx # of each class, and the detection circuit 49 detects the maximum values MAX # and MIN # of the quantized data of each class.
[0036]
The output of the averaging circuit 48 and the output of the detection circuit 49 are supplied as data inputs to the memory 29a, and are written to an address defined by the output of the address counter 47. As a result of the training performed in this manner, the memory 29a stores, in the 3 × 3 area, a class defined by eight adjacent pixels, representative quantized data (DTx∧) of the class, and the class. Existence area data (MAX #, MIN #) is stored. This memory 29a is used in the correction circuit 17 as described above.
[0037]
FIG. 3 shows the principle of the training in an easy-to-understand manner.The area isInfinitely necessary and impractical. Therefore, the configuration shown in FIG. 6 is used. The 8-bit class information from the synchronization circuit 45 is supplied to the switching circuit 61. The quantized data DTx is supplied to comparison and selection circuits 65 and 66 and an addition circuit 67.
[0038]
The switching circuit 61 selects the output terminal b in the first half (reading period) of the period of one block, and selects the output terminal a in the latter half (writing period). The write address from the output terminal a of the switching circuit 61 is supplied to the memory 46b. The output terminal b is supplied to an input terminal d of the switching circuit 63. The output of the address counter 62 is supplied to the input terminal c of the switching circuit 63. This address counter 62 corresponds to the address counter 47 in FIG. The switching circuit 63 selects a read address from the input terminal d during training, and selects a read address from the input terminal c after training.
[0039]
The memory 46b has an accumulated value Σ, a maximum value, a minimum value, and a count value CNT as data input / output. The output of the accumulated value of the memory 46b is supplied to an addition circuit 67 and a division circuit 68. The addition output of the addition circuit 67 is used as the data input of the memory 46b. Therefore, the accumulated value of the quantized data of each class is input to the memory 46b.
[0040]
The comparison and selection circuit 65 is supplied with the quantized data DTx and the minimum value output from the memory 46b, selects smaller data, and supplies this to the memory 46b. The comparison and selection circuit 66 is supplied with the quantized data DTx and the maximum value output from the memory 46b, selects larger data, and supplies this to the memory 46b. The count value output is supplied to the adding circuit 64, and the added output of +1 is input to the memory 46b.
[0041]
Since the memory 46b performs reading and then writing, when the training period is terminated by the above-described configuration, the accumulated value, the maximum value, the minimum value, and the occurrence frequency of the quantized data are stored in the memory 46b. It is stored every time. After the end of the training, the switching circuit 63 is switched, and the incrementing address from the address counter 62 is supplied as a read address for the memory 46b and a write address for the memory 29b.
[0042]
The accumulated value from the memory 46b is divided by the frequency count value in the division circuit 68, and an average value, that is, predicted quantized data DTx # is generated at the output thereof, and is written into the memory 29b. The maximum value and the minimum value from memory 46b are taken into memory 29b as existence area data MAX # and MIN #. According to the configuration of FIG. 6, the data of each address of the memory 46b isThe area isIt is possible to prevent an infinite need.
[0043]
Next, another embodiment of the present invention will be described. The overall configuration of the recording circuit and reproducing circuit of the other embodiment is the same as that of FIG. Another example of the correction circuit 17 is shown in FIG. Circuit blocks corresponding to the above-described example of the correction circuit 17 (FIG. 2) are denoted by the same reference numerals. The memory 29c stores weight coefficient data ω1 to ω8 and error allowable range data σ by training described later.
[0044]
The blocking circuit 23 sequentially forms 3 × 3 blocks (pixel values in the blocks are represented by a to i), and the actual data e of the central pixel is supplied to the comparison operation circuit 71 and the selector 75. Eight other pixel data other than the center pixel are supplied to the ADRC encoding circuit 24 and the arithmetic circuit 72. The ADRC encoding circuit 24 has the same configuration as that of FIG. 5, but generates only the comparison output DT of eight pixels. The synchronizing circuit 25 connected to the ADRC encoding circuit 24 forms 8-bit class data, which is supplied as a read address of the memory 29c.
[0045]
The weight coefficient data ω1 to ω8 from the memory 29c are supplied to the arithmetic circuit 72, and the arithmetic circuit 72 generates a predicted value e∧ of the central pixel e represented by the following equation.
e∧ = ω1a + ω2b + ω3c + ... + ω8i
The estimated value e∧ from the arithmetic circuit 72 and the error range data σ are supplied to the addition circuit 73, and e∧ + σ is generated. The predicted value ∧ and the error range data σ from the arithmetic circuit 72 are supplied to the subtraction circuit 74, and ∧−σ is generated. The output data of the addition circuit 73 and the subtraction circuit 74 are supplied to the comparison operation circuit 71.
[0046]
The comparison operation circuit 71 determines that there is no error when the existence area, ie, ∧−σ <e <e∧ + σ, is satisfied, and otherwise determines that there is an error. The comparison operation circuit 71 generates a control signal for the selector 75. The selector 75 selects the actual data e when there is no error, and selects the predicted value e∧ when there is an error. The corrected output data is generated at the output terminal 76 of the selector 75.
[0047]
FIG. 8 shows a configuration of training for storing necessary data in the memory 29c. For training, a digital image signal of a standard picture is supplied to the input terminal 41. Circuit blocks corresponding to the configuration in FIG. 3 are denoted by the same reference numerals. As shown in FIG. 8, the block formed by the blocking circuit 43 is composed of pixel value data of reference symbols a to i. The data of each block is supplied to the ADRC encoding circuit 44, the identification circuit 77, and the error calculation circuit 78. The 8-bit class information from the synchronization circuit 45 and the sequential address from the address counter 47 are supplied to the identification circuit 77.
[0048]
The identification circuit 77 identifies the weighting coefficients ω1 to ω8 that minimize the sum of squares of the error by the least square method. The identification circuit 77 is provided with a data memory. In this data memory, the value of the pixel data in the block is written for the address that is the class information. For example, addresses corresponding to a certain class include pixel data a (a1, a2,..., An), pixel data b (b1, b2,..., Bn), and pixel data c (c1, c2). , Cn),..., (I1, i2,..., In) for the pixel data i. Pixel data is similarly stored for other classes of addresses.
[0049]
Next, coefficient data ω1 to ω8 that minimize the error are obtained by the least square method using the accumulated data. Focusing on one class, the following equation holds for this class.
e1 = ω1a1 + ω2b1 + ω3c1 + ... + ω8i1
e2 = ω1a2 + ω2b2 + ω3c2 +... + ω8i2
・
・
・
en = ω1an + ω2bn + ω3cn +... + ω8in
[0050]
Here, since a1 to an, b1 to bn,..., I1 to in are known, weighting factors ω1 to ω8 that minimize the square of the error with respect to e1 to en (actual values) are obtained. Desired. The same applies to other classes. The ω1 to ω8 of each class obtained by the identification circuit 77 are sequentially written into the memory 29c with respect to the address from the address counter 47.
[0051]
The error calculation circuit 78 calculates the identified coefficients ω1 to ω8 and the actual data excluding e in the block, generates a predicted value ∧, and calculates an error between the true value e and the predicted value ∧. The calculation for detecting this error is performed for each class. For a certain class, the following plurality of error data Ei are obtained.
E1 = e∧1-e1
E2 = e∧2-e2
・
・
・
En = e @ n-en
[0052]
Output data E1 to En of the error calculation circuit 78 are supplied to the detection circuit 79. The detection circuit 79 detects a maximum value MAX and a minimum value MIN of the error of each class. The output of the detection circuit 79 is supplied to the multiplication circuit 80. The multiplier 80 is supplied with a predetermined coefficient N (where 0 <N <1) from an input terminal 81. The multiplication circuit 80 performs the following operation to generate the allowable error range data σ.
σ = (MAX−MIN) × N / 2
It is desirable that the value of N be variable.
[0053]
The data σ generated by the multiplying circuit 80 is sequentially written to the data area of each address of the memory 29c. As described above, the weight coefficients ω1 to ω8 and the allowable range data σ are stored in the data area of each address by the training. This memory 29c is used in the correction circuit of FIG. As described above, it is possible to detect the presence or absence of an error and correct the error using the data in the memory 29c.
[0054]
Next, still another embodiment of the present invention will be described with reference to FIG. The above-described correction circuit in FIG. 7 fixes the allowable range data σ read from the memory 29c. Still another embodiment has a learning function of varying σ according to the error rate. In FIG. 9, the same reference numerals are given to circuit blocks corresponding to FIG.
[0055]
The allowable range data σ read from the memory 29c is supplied to the addition circuit 73 and the subtraction circuit 74 via the multiplication circuit 82. The multiplication circuit 82 is a circuit for changing σ. As described above, the comparison operation circuit 71 generates a 1-bit output signal indicating whether or not the reproduced pixel data e has an error. This output signal is supplied to the counter 83 and counts an output signal (for example, “1”) indicating an error. Although not shown, the counter 83 is reset for each line.
[0056]
As shown in FIG. 10, 3 × 3 blocks are sequentially formed by the blocking circuit 23. The counter 83 counts the number of errors for a plurality of blocks composed of three lines of pixel data. The count value of the counter 83 is held in the latch 84, and the output of the latch 84 is supplied to the ROM 85 as an address. The ROM 83 generates a coefficient K for variation (0 <K ≦ 1). The coefficient K is supplied to the multiplying circuit 82, which generates Kσ, and uses this value in the processing of the next one line.
[0057]
As a table stored in the ROM 83, K is small when the number of errors is small, and K is large when the number of errors is large. That is, if the number of errors is small, the rate of use of reproduced data is increased by reducing the allowable range of error σ, while if the number of errors is large, the rate of correction is increased by increasing the allowable range of error σ. increase. As a result, the quality of the reproduced image can be improved.
[0058]
Note that, unlike the above-described embodiment of the correction circuit, the training may be performed using DCT coefficients, and the correction may be performed using DCT coefficients. Also, as block coding for compressing the recording data amount, ADRC other than DCT, vector quantization, or the like may be used.
[0059]
【The invention's effect】
According to the present invention, an error of received or reproduced image data can be corrected without using an error correction code. Therefore, it is possible to prevent an increase in the redundancy of the transmission data. As shown in FIG. 11, the probability that actual data of the class is included within the range of the maximum value MAX and the minimum value MIN of each class formed by training, with the representative quantized data as the center, is extremely high. Errors can be corrected to accuracy.
[Brief description of the drawings]
FIG. 1 is an overall block diagram of a recording / reproducing circuit of a digital VTR to which the present invention can be applied.
FIG. 2 is a block diagram of an example of a correction circuit according to the present invention.
FIG. 3 is a block diagram illustrating an example of a configuration for creating correction data;
FIG. 4 is a schematic diagram for explaining blocking.
FIG. 5 is a block diagram illustrating an example of a 1-bit ADRC encoding circuit;
FIG. 6 is a block diagram of an example of a practical configuration for creating correction data.
FIG. 7 is a block diagram of another example of the correction circuit according to the present invention.
FIG. 8 is a block diagram of another example of a configuration for creating correction data.
FIG. 9 is a block diagram of still another example of the correction circuit according to the present invention.
FIG. 10 is a schematic diagram for explaining still another example of the correction circuit according to the present invention.
FIG. 11 is a schematic diagram for explaining error correction according to the present invention.
[Explanation of symbols]
17 Correction circuit
29a, 29b, 29c Memory storing correction data

Claims (10)

In a receiving / reproducing apparatus for a received or reproduced digital image signal,
Class information output means for outputting class information based on a temporal or spatial correlation of a plurality of pixel values at a predetermined position temporally or spatially close to a target pixel to be detected,
Memory means, which is prepared in advance by training and stores existence area data indicating an area where pixel data can exist in accordance with the class information;
Reading means for reading the existence area data of the corresponding class of the memory means from the output of the class information output means;
Comparing means for comparing the existence area data with the pixel data of the pixel of interest,
An apparatus for receiving / reproducing a digital image signal, wherein the presence / absence of an error is detected based on the output of the comparing means. 2. A digital image signal receiving / reproducing apparatus according to claim 1, wherein said memory means stores a representative value corresponding to the class information prepared in advance by training, and said comparing means stores a representative value of said pixel of interest. A digital image signal receiving / reproducing apparatus which outputs a representative value corresponding to the pixel data of the target pixel when it is determined that the data is outside the range of the existence area data. 2. The digital image signal receiving / reproducing apparatus according to claim 1, wherein said class information output means outputs class information based on a temporal or spatial correlation of a plurality of pixel values adjacent to the decoded target pixel. A digital image signal receiving / reproducing apparatus characterized in that it is made. 4. A digital image signal receiving / reproducing apparatus according to claim 3, wherein the received or reproduced digital image signal is a signal obtained by subjecting DCT coefficient data to variable length coding. Playback device. 2. The digital image signal receiving / reproducing apparatus according to claim 1, wherein the class information output unit includes an ADRC encoding unit that performs ADRC encoding on the input pixel data.
An apparatus for receiving / reproducing a digital image signal, wherein the class information is output based on a plurality of pixel data on which the ADRC code has been performed. 2. The digital image signal receiving / reproducing apparatus according to claim 1, wherein said existence area data is a maximum value and a minimum value for each class of a plurality of true values detected in said training. Signal receiving / reproducing device. 3. The digital image signal receiving / reproducing apparatus according to claim 2, wherein said representative value is an average value of a plurality of true values detected in said training using standard video data for each class. Digital image signal receiving / reproducing device. 2. A digital image signal receiving / reproducing apparatus according to claim 1, wherein said memory means stores coefficient data for each class, and when an error is detected, said plurality of pixel data is obtained by using said coefficient data. A digital image signal receiving / reproducing apparatus which outputs a representative value corresponding to the pixel of interest by performing weight addition. 9. The digital image signal receiving / reproducing apparatus according to claim 8, wherein said coefficient data minimizes an error for each class of a plurality of true values detected in said training. Receiving / reproducing device. The digital image signal receiving / reproducing apparatus according to claim 8,
The counter has a counter for counting the number of pixels that the comparison unit determines that the pixel data of the target pixel is outside the range of the existence area data during a predetermined period,
An apparatus for receiving / reproducing a digital image signal, wherein the presence area data is varied based on an output of the counter means.

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