JP3424282B2 - Pulse phase difference encoding circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for detecting a phase difference between two pulse signals having an arbitrary phase relationship,
In particular, it is a pulse phase difference encoding circuit that enables detection with extremely high accuracy over a wide range.

[0002]

2. Description of the Related Art Conventionally, a pulse phase difference encoding circuit (time A / D conversion circuit) for converting two pulse phase differences (pulse time difference) into a code (numerical value) is disclosed in, for example, Japanese Patent Laid-Open No. 3-220.
No. 814 is proposed. This is because a plurality of delay elements are connected in a ring shape, a first pulse input at an arbitrary timing is circulated, and the number of laps is counted, and a second pulse input with an arbitrary phase difference is input. The circular position of the first pulse corresponding to the timing is specified, and the phase difference between the two pulses is detected by the specific position and the count number.

[0003]

However, in the above-mentioned conventional pulse phase difference encoding circuit, it takes time for the output of the counter to stabilize in the counter that counts the number of times the pulse circulates. It is called "indefinite time"), and a plurality of counters are provided because it is necessary to select a stable output. Furthermore, since these plural counters are not formed at one place at the time of LSI implementation, they are formed at different places, respectively.
There is a problem in that wiring of the wiring from the counter output to the next stage and arrangement of other circuits become complicated, leading to an increase in the area of the entire circuit.

The present invention has been made in view of these problems, and an object of the present invention is to provide a pulse phase difference encoding circuit which can significantly reduce the circuit occupying area when integrated into an LSI by using one counter. To do.

[0005]

In a pulse phase difference encoding circuit according to the present invention for solving the above-mentioned problems, a plurality of signal delay means are connected to each other, and a first pulse is passed through a round trip time (TRG).
And the ring delay pulse generating means for circulating at a counting means for the ring delay pulse generating means and the first pulse counts the number of cycles to orbit, and outputs with a indeterminate time (TF), the ring delay pulse generating means When a circulating position detecting means for detecting a position where the first pulse is circulating and a second pulse having an arbitrary phase difference with respect to the first pulse are inputted, the counting means In the pulse phase difference encoding circuit for encoding the phase difference between the first pulse and the second pulse by encoding the outputs of the and the orbiting position detecting means into a binary number and obtaining a digital signal of a plurality of bits, Timing determining means for determining the timing for latching the output of the counting means after the indefinite period of time by the input of the second pulse; and the timing. Characterized by comprising at least two data latch means for latching more the output of the counting means.

[0006]

According to the present invention, in the pulse phase difference encoding circuit, the timing at which the counter output is latched by the data latch circuit is determined so as to remove the indefinite time of the output of the counter. Even if it is one, a stable counter output can be obtained.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, the configuration of the first embodiment of the pulse phase difference encoding circuit is shown in FIG. This circuit encodes (numerizes) a phase difference (time difference) from the rise of the pulse PA (start of measurement) to the rise of the pulse PB1 into a binary digital signal and outputs it. Here, the phase difference means the measurement time T1 or T2 in the time charts shown in the respective drawings. This also applies to all the examples below.

(First Embodiment) Input pulse PA and second pulse corresponding to the first pulse
In encoding the pulse phase difference of PB1 corresponding to the above, a "pulse phase difference encoding circuit" (Japanese Patent Laid-Open No. 31220/1990)
814), the pulse phase difference data upper bit portion HB and lower bit portion LB have the same configuration, and therefore the subsequent passage of HB and LB is omitted. Here, the ring delay pulse generation circuit 1 and the pulse are generated. Only the pulse selector 6, the encoder 7 and the multiplexer 8 which are the phase difference data lower bit generators, and the counter 2 and the data latch circuits 3 and 4 which are the pulse phase difference data higher bit generators are shown. It should be noted that this pulse phase difference encoding circuit has a high-order bit portion HB and a low-order bit portion LB.
To obtain the above-mentioned phase difference.

First, a pulse phase difference data lower bit generator having the same configuration as the above publication will be briefly described. First, a ring delay pulse generation circuit 1 in which 2 ⁿ stages (for example, 64 stages) of delay elements of the pulse PA are connected in a ring shape
Enter and make it orbit. This ring delay pulse generation circuit 1
Then, the number of revolutions and the revolution position of the pulse PA are output to the counter 2 and the pulse selector 6 corresponding to the revolution position specifying means. Then, when the pulse PB1 is input, the pulse selector 6 outputs the input signal from the delay element at that time to the encoder 7. The signal converted into the binary signal by the encoder 7 is the pulse PA
Is the lower bit portion LB representing the phase difference between the pulse PB1 and the pulse PB1.

Next, the pulse phase difference data upper bit generator which is the main part of this embodiment, that is, the counting means, the timing determining means and the output of the counting means according to the timing determined by the timing determining means The data latch means for latching will be described. The present embodiment particularly corresponds to an embodiment of the pulse phase difference encoding circuit according to claim 3.

One counter 2 for counting output pulse edges is connected to the final stage of the ring delay pulse generation circuit 1, and the counter output data CO (n bits: n = positive integer) is input to this counter 2. The two data latch circuits 3 and 4 are connected in parallel. Here, in order to make the data latch timings of the data latch circuit 3 and the data latch circuit 4 different, a pulse PB1 for determining the latch timing is directly input to the data latch circuit 3,
In addition, the data latch circuit 4 is provided with a third pulse through a delay circuit 5 corresponding to a delay means for generating the delay time T12.
A pulse corresponding to the pulse PB2 is input. The output data of the data latch circuit 3 when the pulse PB1 is input, that is, the counter output data CO is the cycle number data D1, and the output data of the data latch circuit 4 when the pulse PB2 is input is the cycle number data D2. . The selection of the circulation number data D1 and the circulation number data D2 is determined by the relationship between the input pulses PA and PB1 as in the above publication. If the MSB (most significant bit) of the low-order bit portion of the pulse phase difference data of the encoder output is 0, the multiplexer 8 corresponding to the timing selecting means selects the number-of-times data D2. Also, MS
If B is 1, the multiplexer 8 causes the number of revolutions data D
1 is selected and used as the upper bit part of the pulse phase difference data.

A description will be given of one configuration example of the ring delay pulse generating circuit 1. A 2-input NAND element and (2 ⁿ −
1) Inverter elements (63 in this case) are connected in series, and there are a total of 2 ⁶ (= 64) stages. Each inverter is connected so as to output to the next stage inverter and the pulse selector 6, and the output of the last stage inverter is input to the NAND element. NAND
The other input of the device is the pulse PA.

Next, an operation state of the ring delay pulse generating circuit 1 shown in FIG. 1 described above is shown in a time chart 1 of FIG. Here, since the lower bit part of the pulse phase difference data is the same as in the above-mentioned publication, only the upper bit part is shown. First, in order to clarify the time of the time chart, the time required for the number of rounds pulse to make one round in the ring delay pulse generation circuit 1, that is, the clock C
The time from K change to the next change is T _RG , the time when the clock CK is input to the counter 2 and the output of the counter 2 is in an undefined state is T _F, and the time when the counter output is in a stable state is Be T _A. Further, when the number-of-revolutions pulse circulates in the ring delay pulse generation circuit 1, until it passes from the NAND element to the (2 ^n-1 -1) th stage inverter element, that is, the 31st stage inverter element in this embodiment. _Let T _RGH be the time. This also applies to the following examples.

First, the operation of the ring delay pulse generation circuit 1 is started by the rising edge of the pulse PA, and the clock CK is input to the counter 2. When the clock CK is input, the output data CO of the counter 2 changes due to its edges (both rising and falling edges). However, the output data CO is indefinite immediately after the edge of the clock CK, and it takes some time to stabilize. Therefore, the output data CO has two states, that is, a time T _{F in which} it is in an indefinite state and a time T _A in which it is stable when one data is output.

Considering the method of selecting the number of revolutions data D1 and D2 described above, first, the lower bit portion of the pulse phase difference data of the encoder output is a plurality of delay elements in the ring delay circuit 1. It is a binary number indicating to which part of the pulse the round number pulse has passed.
And the most significant bit of this bit part, that is, the MSB is
When the delay element inside the ring delay circuit 1 to which the number-of-circulation pulse is first input passes through the 31st-stage inverter element connected in a ring shape, the value changes from 0 to 1. Therefore, when the MSB of the lower bit part of the pulse phase difference data is 0, the multiplexer 8 selects the frequency data D2,
There because laps data D1 by the multiplexer 8 when 1 is selected, in other words, fast data D2 than T _RGH rising point in its orbit of the pulse PA pulse PB1 is selected, than T _RGH This means that the data D1 is selected when it is late. Therefore, the data latch timing is T when the counter is output at that time.
_It is necessary to consider separately when it is earlier than _RGH and when it is later.

First, in case 1, when the rising time of the pulse PB1 is later than T _RGH of the pulse PA in the round, the round number data D1 is sent to the multiplexer 8.
Since this is selected as the lap count data, it must always be stable lap count data. Therefore, in order to realize this, the time during which the output of the counter output data CO is indefinite is set to T _F , and this T _F is first set to be smaller than T _RGH . If T _F is set in this way, the data latch timing T _R
However, if the pulse PA is later than T _RGH in the circulation, the counter output data CO is always stable, and therefore the circulation number data D output from the data latch circuit 3 is generated.
1 is always stable.

Next, in case 2, the pulse PB1 rises.
The rising time is T in the orbit of pulse PA._RGHYo
If it is faster, the cycle number data D2 is the multiplexer 8
This is always selected as
Must be stable lap data
Yes. In this case, T_FTo T_RGHCompared to
Since it is set to be small, the counter output data
There are times when the CO is indefinite and stable. First,
Data latch timing T_RBut the counter at that time
When the output data CO is in an indefinite state, that is, indefinite state
Time T_FData latch circuit 4 is in a stable state,
To latch the counter output data CO, the delay time
T12 is indefinite time T_FGreater than the steady state time T
_A(= T_RG-T _FSmaller than). Also, the day
Taratch timing T_RIs the counter output data at that time.
When the data CO is in a stable state, that is, stable from an indefinite state
Time to change to state T_FASlower than T_RGHFaster than
If the delay time T12 is T_RGHIt should be smaller than.

[0018] In summary, first, that time T _F as pulse circulating time T _RG or counter output data CO ring pulse delay circuit controls the time T _F is indefinite state is smaller than T _RGH To Also,
The delay time T12 between the data latch circuit 3 and the data latch circuit 4 is defined as the time T during which the counter output data CO is in an indefinite state.
_It should be longer than _{F and} shorter than _TRGH . The above two relations can be summarized as the following equation.

[0019]

## EQU1 ## T _F <T12 <T _RGH By setting the time relationship such as the delay time in this way, and considering the performance of the circuit elements, T12 should be as close as possible to T _RGH . By doing so, no matter what time the latch pulse PB1 is input, the multiplexer can always select stable and accurate lap count data with respect to the above-described selection method of the lap count data D1 and the lap count data D2.

Therefore, instead of the conventional configuration of providing two cycle counters, one cycle counter and two data latch circuits in which a delay circuit is provided in one data latch circuit as described above are provided. By providing the counter after the counter in parallel, the correct number of laps data can always be obtained when the condition of equation 1 is satisfied. (Second Embodiment) Next, FIG. 3 shows a pulse phase difference encoding circuit which corresponds to an embodiment according to the present invention.

Here, the lower bit generator of the pulse phase difference data has the same configuration as described above. Here, the configuration of the pulse phase difference data upper bit generator will be described.
A counter 2 for counting the edges of the clock CK which is an output pulse is set to 1 at the final stage of the ring delay pulse generation circuit 1.
The data latch circuit 14 corresponding to the first data latch means for inputting the counter output data CO (n bits: n = positive positive number) is connected to the counter 2, and the data latch circuit 14 is further connected. A data latch circuit 13 corresponding to the second data latch means is connected in series to the. Here, the output data D4 of the data latch circuit 14 is input to the data latch circuit 13 and is also used as the cycle number data D4, and the output data D3 of the data latch circuit 13 is set as the cycle number data D3. In addition, the data latch circuit 14
The pulse PBL corresponding to the fifth pulse that gives the data latch timings of 13 and 13 corresponds to the fourth pulse.
That a pulse PB1 1, generated by the exclusive OR circuit 10 the pulse PBD1 1 which has canceller is delayed by the delay circuit 9 PB1 1, is input to the data latch circuit 14 and 13. Further, the pulse PB1 1 is generated by the exclusive OR circuit 12 of the pulse PB 1 and the pulse PBD 1 obtained by delaying PB 1 by the delay circuit 11 similarly to the pulse PBL. The selection of the number-of-turns data D3 and D4 is the same as that in the above-described configuration example.

Next, FIG. 4 shows an operating state in the circuit configuration 2 of FIG. Also in this embodiment, the lower bit portion LB of the pulse phase difference data is the same as that of the first embodiment as described above, and therefore only the upper bit portion HB operates. Further, the operations of the clock CK and the output data CO of the counter 2 associated with the pulse PA are the same as those in the above-described embodiment. First, the measurement times T3 and T4 of the time chart 2 shown in FIG. 4 represent the phase difference from the rising point of the pulse PA to the rising point of the pulse PB1 1 as in the first embodiment.

Here, in this embodiment, the pulse PB
1 1, the operation of falls after a delay time TK after the pulse PB1 1 rises by the action of the delay circuit 11 and the exclusive OR circuit 12. Similarly, the pulse PBL also rises by the action of the delay circuit 9 and the exclusive OR circuit 10, and then falls after the delay time TW. Further, in the case of the pulse PBL, the pulse PB
The rise in response to 1 1 of rising and falling. However, in order to achieve the above-described operation, the delay time TK that determines the pulse width of the pulse PB1 1 is set to the pulse P
It must be longer than the delay time TW that determines the pulse width of BL. The pulse PBL serves as a common latch signal for the data latch circuits 14 and 13. for that reason,
The data latch circuits 14 and 13 connected in series operate similarly to the shift register. Therefore, the data latch circuit 14, 13 which rise of the pulse PBL is a data latch timing, the data latch circuit 14, the rise of the latch pulse PB1 1, and for a series of operations that fall, the counter output CO 2 times It will be latched, and in the data latch circuit 13,
The output of the data latch circuit 14 will be latched twice. That is, in the second data latch, the cycle number data D4 output from the data latch circuit 14 becomes the newly latched counter output data CO, but the cycle number data D3 output from the data latch circuit 13 is
The data latch circuit 14 at the time of the first data latch
The number of revolutions data D4 output from is shifted.

Here, also in this embodiment, as described above, the method of selecting the number of turns data is the same as in the first embodiment.
When MSB = 0, the lap count data D4 is selected and M
When SB = 1, the circulation number data D3 is selected. That is, when the data latch timing TR1 which is the input timing of the latch pulse PB1 1 is equal to or earlier than TRGH of the counter output at that time point, the number-of-times data D4 is selected and the data latch timing T
When R1 is later than TRGH of the counter output at that time, the circulation number data D3 is selected. Therefore, in the present embodiment as well, it is necessary to consider the data latch timing TR1 separately when the data latch timing TR1 is earlier and later than the TRGH in the circulation of the pulse PA.

First, as Case 1, when the data latch timing T _R1 is later than T _RGH of the pulse PA in the round, the round number data D3 is transferred to the multiplexer 8
Since this is selected as the lap count data, it must always be stable lap count data. In order to realize this, it is sufficient that the frequency data D4 outputted from the data latch circuit 14 at the first data latch timing T _R1 is stable. Then, in the second data latch, the stable frequency data D4 is shifted to the data latch circuit 13,
Circulation number data D3 output from the data latch circuit 13
Will always be stable. Therefore, as in the previous embodiment, the time T _F during which the counter output data CO is in an indefinite state is set to T
It should be smaller than _RGH .

Next, as case 2, the data latch timing TR1 is TRGH in the circulation of the pulse PA.
If it is earlier than this, the number of laps data D4 is selected as the number of laps data by the multiplexer 8. Therefore, this must be always stable number of laps data. In this case, the counter output data CO directly becomes the number-of-times data D4 selected by the multiplexer 8. Therefore, the second data latch timing TR2 must be set so that the counter output data CO is in a stable state. . For that purpose, the second latch pulse P
Rise The BL, i.e., the falling edge of the latch pulse PB1 1 may if during the stable state of the counter output data CO. Therefore, even in this case, the data latch timing TR1 may exist when the counter output data CO is in an indefinite state and when it is in a stable state. However, like the previous embodiment, the delay circuit that determines the falling edge of the latch pulse PB1 1 is present. The delay time TK of 11 is longer than the indefinite state time TF, and the time TRGH that is half the cycle time of the cycle pulse is
It should be shorter than this.

To summarize the above, first, the latch pulse PB
The delay time TW that determines the pulse width of L is the latch pulse PB.
To be smaller than the delay time TK determining a first pulse width. Then, the pulse circulation time TRG of the ring delay pulse generation circuit or the time TF during which the counter output data CO is in an indefinite state is controlled so that the time TF is T.
It should be smaller than RGH. Further, a delay time TK that determines the pulse width of the latch pulse PB1 1, longer than the indefinite time TF of the counter output data CO, and set to be shorter than half the time TRGH the pulse circulating time. The above three relationships are summarized as the following two expressions.

[0028]

[Equation 2] T _W <T _K

[0029]

TF <TK <TRGH In this way, the time relationship such as the delay time is set so that the TW becomes equal to TK / 2 in consideration of the stability of the element. By doing so, regardless of the time when the latch pulse PB1 1 is input, the multiplexer can always select accurate and accurate cycle number data with respect to the above-described method of selecting the cycle number data D3 and the cycle number data D4. .

Therefore, as described above, in the present embodiment, instead of providing two circulation counters, one circulation counter, a delay circuit for a latch pulse for measuring the measurement time, and an exclusive OR circuit are provided. By providing the two data latch circuits to which the newly generated latch pulse is input in series after the lap counter, if any of the formulas 2 and 3 is satisfied, in any case It is possible to obtain stable and accurate lap number data.

(Third Embodiment) Next, an embodiment particularly corresponding to claim 6 of the present invention will be described with reference to the drawings. The feature of this embodiment resides in the output portion of the pulse PB3 that determines the data latch timing for the data latch circuit 16 to latch the output of the counter 2. Similar to the above embodiment, the operation description of the ring delay pulse generation circuit 15, the pulse selector 7 and the encoder 8 which are the pulse phase difference data lower bit generation section will be omitted.
Here, the ring delay pulse generation circuit 15 shown in FIG.
Delay circuit 17 corresponding to the pulse output unit 6, the counter 2, the data latch 16, the sage circuit 18 corresponding to the seventh pulse output means, the description of the construction and operation.

In the ring delay pulse generating circuit 15, for example, as shown in FIG. 5, one NAND element and 63 inverter elements are connected in series, and the NA from the final stage of the inverter.
The connection is made so as to return to the ND element, and the pulse PA is input to the NAND element. The time adjustment circuit 18 is a D flip-flop (hereinafter referred to as DFF).
The pulse PB1 formed by the circuit and the output of the final stage inverter of the ring delay pulse generation circuit 15, that is, the output pulse RL of the ring delay pulse generation circuit 15 are input. The adjusting circuit 18 outputs a pulse PB3 corresponding to the seventh pulse when the pulse PA passes through the final stage of the inverter after the pulse PB1 is input. This pulse PB3 becomes the data latch timing of the data latch circuit 16 shown below. The delay circuit 17 receives the output pulse RL of the ring delay pulse generation circuit 15 and outputs a clock pulse CK with a delay time TD. And in the counter 2,
When the clock pulse CK corresponding to the sixth pulse is input, the counter output CO changes due to its rising edge. However, the output data CO is the clock pulse C
Immediately after the edge of K, it is indefinite and it takes some time to stabilize. Therefore, the output data CO has two states, a stable state and an unstable state. Then, the data latch circuit 16 latches and outputs this counter output CO by the input of the above-mentioned pulse PB3.

As described above, in this configuration, PB3 which is the data latch timing of the counter output CO is P
After the input of B1, the pulse PA is output when the pulse PA passes through the final stage of the inverter, that is, when the pulse number is increased by one round than the number of rounds to be actually detected. Therefore, the counter output CO at this timing is always
It must be the actual number of laps. Delay circuit 1
7 is for that purpose. With this delay circuit 17,
At the data latch timing of PB3, the counter output is always the actual number of cycles to be detected. Further, as can be seen from FIG. 6, PB3 rises at the rising edge of the output pulse RL of the ring delay pulse generation circuit 1. Therefore, at this time, in order for the counter output CO to always be a stable output, the delay time T _D from the time T _RG when the pulse PA goes around the ring delay pulse generating circuit 1 to the time T when the counter output CO is in the indefinite state _It should be smaller than the time when _F is subtracted. Further, it may be longer than the delay time T _P from the change of the output pulse RL of the ring delay pulse generating circuit 15 to the change of PB3.

In summary, in the configuration of this embodiment, the relationship between the delay time T _D , the circulation time T _RG of the pulse PA and the indefinite time T _F of the counter output CO is as follows.

[0035]

[Expression 4] T _P <T _D <T _RG −T _F. By doing so, a stable counter output CO can be obtained at all times even if the number of counters is one, and correct circulation number data can be obtained.

(Fourth Embodiment) Next, an embodiment corresponding to claim 7 of the present invention will be described with reference to FIGS. This embodiment is an improvement of the third embodiment,
In this embodiment, two arbitration circuits are prepared, an OR circuit for logically synthesizing the outputs of the arbitration circuits is provided, and a pulse for determining the data latch timing is output by this OR circuit. is there. This point will be briefly described.

For example, in the ring delay pulse circuit 15 as in the above embodiment, one NAND element and ( 2 ⁿ -1) inverter elements (63 in this case) are connected in series to form the final inverter. Connection is made so as to return from the stage to the NAND element, and the pulse PA is input to the NAND element. The time setting circuit 18 corresponding to the seventh pulse output means and the time setting circuit 19 corresponding to the eighth pulse output means are formed of DFF circuits. The time setting circuit 19 receives the pulse PB1 and the output pulse RM of the intermediate stage of the ring delay pulse generation circuit 1, that is, the output pulse RM of the 31st stage inverter, and outputs the pulse PB1.
When pulse PA passes through the 31st stage inverter after B1 is input, pulse PB2 corresponding to the eighth pulse
2 is output. Further, the time setting circuit 18 receives the pulse PB1 and the output pulse RL of the ring delay pulse generation circuit 1 as in the above-described embodiment, and the pulse PB1
When the pulse PA passes through the final stage of the inverter after 1 is input, the pulse PB3 corresponding to the seventh pulse is output. Therefore, the phases of the pulse RM and the pulse RL are inverted.

The operation state of the ring delay pulse generating circuit 15 shown in FIG. 7 is shown in the time chart 4 of FIG. Here, since the lower bit portion of the pulse phase difference data is similar to that of the previous application, only the upper bit portion is shown. First, the operation of the ring delay pulse generation circuit 15 is started by the rising edge of the pulse PA, the pulse RM is supplied to the time adjustment circuit 19, and the time adjustment circuit 18 and the delay circuit 17 are supplied.
The pulse RL is input to. Then, the fifth counter 5
The delay circuit 17 corresponding to the pulse output means of 6th has a phase difference of an arbitrary delay time TD with respect to the pulse RL .
A pulse CK corresponding to the pulse is input. Pulse CK
When is input, the counter 8
Of the output data CO changes. However, the output data CO is indefinite immediately after the edge of the pulse CK, and it takes some time to stabilize. Therefore, the output data C
O has two states, a stable state and an unstable state. Further, the rectifying circuit 19 outputs the pulse PB2 obtained by arranging the pulse PB1 by the pulse RM. Further, the timing circuit 18 outputs the pulse PB3 obtained by timing the pulse PB1 by the pulse RL. And the pulse P
The ninth pulse B2 and the pulse PB3 are logically synthesized by the logical sum circuit 20 and have a phase difference of the delay time TO.
The pulse CL corresponding to is output. Then, by the pulse CL that determines the latch timing, the data latch circuit 1
Reference numeral 6 latches the cycle number data from the counter 2 and outputs it.

Considering the pulse CL that determines the latch timing, the pulse CL is the pulse PB2.
Since it is a logical sum of the OR of 2 and the pulse PB3, the pulse CL becomes the LOW state when both the pulse PB22 and the pulse PB3 are in the LOW state, and the HIGH state when either one of the pulse PB22 and the pulse PB3 is in the HIGH state. Becomes Pulses PB22 and PB3 as described above
Pulse PA passes through the NAND element, and ( 2 ^n-1 −
1) The delay element of the third stage, that is, the delay element of the 31st stage in this embodiment, is shifted by the time _TRGH . This is, in other words, fast pulse PB22 same or than the T _RGH data latch timing at the lap of the pulse PA is selected, the pulse PB3 is selected to be slow. Therefore, it is necessary to separately consider the data latch timing when it is earlier than TRGH and later than TRGH in the circulation of the pulse PA.

Firstly, Ke - as scan 1, the rise of the pulse PB1 is earlier than TRGH in that circulation of the pulse PA is the pulse CL rises by the rise of the pulse PB2 2, this time, always laps counter output The data CO must be stable and accurate. As described above, the pulse CL as the data latch timing is the pulse PB2 that rises with the rise of the pulse RM after the rise of the pulse PB1.
By 2 , the delay time TO rises. Therefore,
The pulse CL always rises after a delay time TO from the rise of the pulse RM. Further, the counter output data CO is delayed by the delay time T due to the rise of the pulse RL.
It changes with D and is output with an indefinite time TF. Further, the pulse RM and the pulse RL are TR
There is a phase difference of only GH. Therefore, in order to achieve the above object, the indefinite state of the counter output CO is
It is necessary to avoid overlapping with the rising timing of. Referring to the time chart of FIG. 8, the pulse R
With reference to the rising time of L, the sum of the delay time TD and the indefinite time TF is the phase difference T between the pulse RL and the pulse RM.
It may be smaller than the sum of RGH and the delay time TO. Then, in this case 1, it is possible to obtain a stable counter output CO and to obtain accurate lap number data.

Further, considering the error of the element characteristics, the delay
Time T_DAnd indefinite time T_FAnd the pulse RL and the
Phase difference T with Russ RM_RGHBe smaller than
If so, a stable counter output CO can be reliably obtained.
Therefore, accurate lap number data can be obtained. Next,
As the second pulse, the rising edge of the pulse PB1 is the pulse P
T in A's lap_RGHPulse if slower than
The pulse CL rises when PB3 rises
Therefore, at this time, the lap counter output data CO is always low.
Must be fixed. In this case, the third implementation
Similar to the case of the example, the delay time T_DIs the circumference of pulse PA
Time T_RGFrom indefinite time T_FLess than the time
It should be. Furthermore, as you can see in Figure 8,
The rising edge of the chi-pulse CL is the number of times the ring delay pulse is generated.
Compared to the rising edge of the output pulse RL of the path 15, T_OIs
The delay time T is too long._DBecomes shorter,
The rising edge of the pulse CL that is the latch timing is
In some cases, the counter output data CO of
is there. To avoid this, the delay time T_OBut T_DTo
It may be set to be long. Thus T_DThe set
Data latch timing T _RBut of the pulse PA
T in that lap_RGHIf it's slower, be sure to lap
The counter output data CO becomes stable.

[0042] In summary, first, so as to control the delay time T _D by the delay circuit 7, the delay time T _{D
Is made} shorter than T _RGH minus T _F, and longer than the delay time T _O by the OR circuit 20. The above relationship is summarized as follows.

[0043]

[Formula 5] T _O <T _D , T _D + T _F <T _RGH + T _O. Further, when the omitted T _O of the second equation of the right side of equation (5), summarized equation (1) to one,

[0044]

The [6] _{T O <T D <T RGH} -T F. Further, considering the performance of the delay element, T _D is set to a value as close as possible to the middle of T _O and T _RGH −T _F. By doing so, no matter what time the latch pulse PB1 is input, the cycle number data can always be stable and accurate. In addition, in the present embodiment, the configuration of the third embodiment is increased by one to have two arbitration circuits, and the method of selecting the pulse for determining the data latch timing is the pulse circling of the pulse PA when the pulse PB rises. The position, that is, whether the pulse PA is located in the first half or the second half of the delay elements connected in series is determined. With such a configuration, for example, when the pulse PB1 is input many times with respect to one input of the pulse PA, the pulse PA determines the pulse for determining the data latch timing, and the pulse PA makes one round in the ring delay pulse generation circuit. Since the output is performed twice during this period, the sampling time can be made shorter than that of the third embodiment.

(Fifth Embodiment) Next, FIG. 9 shows an embodiment corresponding to claim 8 of the present invention. This embodiment is the first
A multiplexer corresponding to the output selecting means is used as in the second embodiment, but the difference from the above embodiment is that the counter output is latched by two data latch circuits in the above embodiment. Although the output is selected by the multiplexer, in the present embodiment, two pulses for determining the data latch timing of the data latch circuit are prepared, and these two pulses are selected by the multiplexer.

Similar to the above embodiment, the configuration and operation of the pulse phase difference data upper bit generator will be described here. After the ring delay pulse generation circuit 15, a delay circuit 1 corresponding to sixth pulse output means for outputting a pulse having a phase difference for this output pulse by an arbitrary delay time TD.
7 is connected, and the delay circuit 17 is connected to the counter 2 for counting output pulse edges. Then, the data latch circuit 16 which receives the counter output data CO is connected to the counter 2. Then, the delay circuit 21 corresponding to the eleventh pulse output means for generating the delay time TB is the pulse PB1 that determines the original latch timing.
And to the multiplexer 8. In addition, the delay circuit 2
Pulse PB4 corresponding to the 11th pulse which is the output of 1
Is input to the multiplexer 8. Here, the method of selecting the pulse PB1 and the pulse PB4 in the multiplexer 8 is determined by the output of the pulse selector 6. That is, the output pulse PO of the pulse selector 6 is LO
In the W state, the pulse PB1 is selected, and the pulse PO is H
If it is in the IGH state, the pulse PB4 is selected. This corresponds to the 12th pulse of the multiplexer 8 determined in this way .
The output pulse PB5 is input to the data latch circuit 16 as a pulse that determines the data latch timing. Then, the output data of the data latch circuit 16 is used as the upper bit part of the pulse phase difference data.

The pulse selector that outputs the pulse PO will be described in detail with reference to FIG. First, the pulse PB1 is in the LOW state, at this time, sw1 is connected and sw2 is disconnected. As can be seen from the figure, since the pulse PO is output via the inverter, the pulse PO has a delay time T _S with respect to the pulse RL. When the pulse PB1 changes from the LOW state to the HIGH state, sw1 becomes disconnected and sw2 becomes connected. As a result, the pulse PO remains unchanged in the state when the pulse PB1 changes. When the pulse PO is in the LOW state, the multiplexer 8 outputs the pulse PB1 as the pulse PB5, and when the pulse PO is in the HIGH state, the multiplexer 8 outputs the pulse PB4 as the pulse PB5. Further, since the pulse PO can be considered as the output pulse RL of the ring delay pulse generation circuit having the delay time T _S, as can be seen from the time chart, when the pulse PA is earlier than T _RGH in the circulation, , HI
When it is in the GH state and is larger than _TRGH , L
The OW state is set.

The operation state of the ring delay pulse generating circuit 15 shown in FIG. 9 is shown in the time chart 5 of FIG.
Shown in. Here, since the lower bit portion of the pulse phase difference data is similar to that of the previous application, only the upper bit portion is shown. First, the operation of the ring delay pulse generation circuit 15 is started by the rising edge of the pulse PA, and the pulse RL is input to the delay circuit 17. And counter 2
Then, the delay circuit 17 inputs a pulse CK having a phase difference with respect to the pulse RL by an arbitrary delay time TD. Sixth
When the pulse CK corresponding to the pulse is input, the output data CO of the counter 2 changes due to the edge thereof. However, the output data CO is indefinite immediately after the edge of the pulse CK, and it takes some time to stabilize. Therefore, the output data CO has two states, a stable state and an unstable state.

Here, the above-mentioned pulse PB1 and pulse PB
Considering the selection method of B4, first, the output pulse PO of the pulse selector 6 is a pulse having a delay time T _S with respect to the output of the final stage of the ring delay pulse generation circuit 1. When the pulse PB1 is input, the pulse PO has a characteristic that it is unchanged in the state at that time. Therefore, when the pulse PB1 rises, the pulse P
It is necessary to separately consider when O is in the LOW state and when it is in the HIGH state.

First, as the case 1, when the pulse PB1 rises and the pulse PO is in the HIGH state, the multiplexer 8 outputs the pulse PB4 as the pulse PB5. Therefore, the lap counter is not always stable at this time. must not. The delay time of the delay circuit 21 is T _B
In this case, if T _B becomes short, the latch timing may become when the counter output data CO is in an indefinite state. In order to avoid such a state, the delay time from the change of the pulse RL to the change of the pulse CK by the delay circuit 17 is defined as T _D, and the cycle number counter output data C
When the time in which the output of O is indefinite is T _F , the delay time T _B may be set to be longer than T _D plus T _F. If T _B becomes too long, the counter output data CO may have a value different from the original value. In order to avoid such a state, T _B is set to be shorter than the time T _RGH until the circulation pulse PA passes through the (2 ^n-1 -1) ^th delay element.
By setting T _B in this manner, when the pulse PB1 rises and the pulse PO is in the HIGH state, the lap counter output data is always stable, so the lap count data output from the data latch circuit 16 is also included. It will always be stable.

Next, in case 2, when the data latch timing T _R is input and the pulse PO is in the LOW state, the multiplexer 8 outputs the pulse PB1 as the pulse PB5. Must be stable. When the delay time T _S by the pulse selector 6 increases, the counter output data C
O may have a value different from the original value. In order to avoid such a state, the delay time T _D by the delay circuit 17 is set to be longer than the delay time T _S.
If T _D is set in this way, the data latch timing T
When the pulse PO is LOW when _R is input,
Since the cycle number counter output data is always stable, the cycle number data output from the data latch circuit 16 is always stable.

In summary, first, the delay time T _B is controlled by the delay circuit 21, and the delay time T _B is controlled.
_{Make B} longer than T _F plus T _D ,
Set to be shorter than T _{RG H.} Further, the delay circuit 17 controls the delay time T _D so that the delay time T _D is set shorter than the delay time T _S. The above two relations can be summarized as the following equation.

[0053]

[Equation 7] T _D + T _F <T _B <T _RGH

[0054]

[Equation 8] T_S<T_D In this way, the time relationship such as delay time is set to stabilize the element.
In consideration of sex_BTo T _RGHTo be approximately equal to
To do. By doing so, when the latch pulse PB1 is
Even if it is input to, the lap number data is always stable and accurate.
Becomes

[0055]

[0056]

As described above, according to the above-described numerous embodiments, it is possible to reduce the number of counters, which conventionally required two or more, to one. Therefore, there is an excellent effect that the circuit occupying area can be reduced by 20% to 30% when the pulse phase difference encoding circuit is formed into an LSI.

[0058]

As described above, according to the configuration of the present invention, it is possible to use only one counting means for counting the number of times of the first pulse, which circulates the ring delay pulse generation means with the circulation time T _RG . Therefore, when the pulse phase difference encoding circuit is formed into an LSI, there is an excellent effect that the circuit occupying area can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a pulse phase difference encoding circuit of a first embodiment.

FIG. 2 is a time chart showing an operation state in the first embodiment.

FIG. 3 is a configuration diagram showing a pulse phase difference encoding circuit according to a second embodiment.

FIG. 4 is a time chart showing an operation state in the second embodiment.

FIG. 5 is a configuration diagram showing a pulse phase difference encoding circuit according to a third embodiment.

FIG. 6 is a time chart showing an operation state in the third embodiment.

FIG. 7 is a configuration diagram showing a pulse phase difference encoding circuit according to a fourth embodiment.

FIG. 8 is a time chart showing an operating state in the fourth embodiment.

FIG. 9 is a configuration diagram showing a pulse phase difference encoding circuit according to a fifth embodiment.

FIG. 10 is a time chart showing an operation state in the fifth embodiment.

FIG. 11 is a configuration diagram of a pulse selector.

[Explanation of symbols]

1 Ring delay pulse generation circuit 2 counter 3 Data latch circuit 4 Data latch circuit 5 delay circuit 8 multiplexer

Front page continuation (56) Reference JP-A-3-220814 (JP, A) JP-A-1-164118 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 5 / 26

Claims (8)

(57) [Claims] 1. A ring delay pulse generation means for connecting a plurality of signal delay means to rotate a first pulse in a circulation time (TRG), and the first pulse circulates in the ring delay pulse generation means. Counting means for counting the number of rounds and outputting for an indefinite time ( _TF ); rounding position detecting means for detecting at which position the first pulse goes round the ring delay pulse generating means; When a second pulse having an arbitrary phase difference with respect to one pulse is input, the outputs of the counting means and the orbiting position detecting means are encoded into a binary number to obtain a digital signal of a plurality of bits. The first pulse and the second
A pulse phase difference encoding circuit for encoding the phase difference of the pulse, the timing deciding means for deciding the timing for latching the output of the counting means after the indefinite period of time by the input of the second pulse, A pulse phase difference encoding circuit comprising: at least two data latching means for latching the output of the counting means at timing. 2. The timing determining means includes a timing selecting means for selecting the timing according to an output of the orbital position detecting means which receives and outputs the second pulse. The pulse phase difference encoding circuit described. 3. The delay unit, wherein the plurality of signal delay units are connected in 2 ⁿ stages, and the timing determination unit outputs a third pulse having a phase difference with respect to the second pulse by a delay time (T12). The timing selection means includes a means for passing the ^first pulse through the signal delay element at the 2 ^{n−1 th} stage in the circulation of the first pulse when the second pulse rises. Before, the third pulse is selected, and the second pulse is selected after the first pulse has passed through the signal delay element of the 2 ^{n−1 th} stage. The pulse phase difference encoding circuit according to claim 2. 4. The plurality of signal delay means are connected in 2 ⁿ stages, and the timing determination means rises in response to a rise of a second pulse having an arbitrary phase difference with respect to the first pulse, Fourth pulse generating means for outputting a fourth pulse that falls after the first delay time (T _K ), a rising edge in response to rising and falling edges of the fourth pulse, and a second delay time (T _W )) and a fifth pulse generating means for outputting a fifth pulse which falls, and the timing selecting means, in the orbit of the first pulse at the rising of the second pulse, The fourth pulse is selected before the first pulse passes through the 2 ^n-1 -th stage signal delay element, and the first pulse is the 2 ^n-1 -th stage signal delay element. After passing through the A fifth pulse that rises in response to the falling edge of the counter, and the data latch means further includes first data latch means that directly latches the output of the counter when the fifth pulse is input. 3. The pulse phase difference according to claim 2, further comprising: second data latching means for latching the output of the counter through the first data latching means while receiving the fifth pulse. Encoding circuit. 5. The timing determining means sets a delay time (T) with respect to an output pulse of the ring delay pulse generating means.
A sixth pulse having a _D) by the phase difference has a sixth pulse generating means for outputting to said counter, characterized that you determine the timing with the sixth pulse and the second pulse The pulse phase difference encoding circuit according to claim 1. 6. The plurality of signal delay means are connected in 2 ⁿ stages, and the timing determination means receives a second pulse having an arbitrary phase difference from the first pulse,
It has a seventh pulse output means for outputting a seventh pulse when the output pulse of the final output stage of the ring delay pulse generating means is inputted, and has a delay time with respect to the output pulse of the ring delay pulse generating means. 6. The pulse phase difference encoding circuit according to claim 5, wherein the timing is determined by the sixth pulse and the seventh pulse having a phase difference of (T _D ). 7. The plurality of signal delay units are connected in 2 ⁿ stages, and the timing determination unit receives the second pulse having an arbitrary phase difference with respect to the first pulse, and then the ring. Eighth pulse output means for outputting an eighth pulse when an output pulse of an arbitrary output stage of the delay pulse generation means is inputted, and after the second pulse is inputted, the ring delay pulse generation means When the output pulse of the final output stage of is input,
Seventh pulse output means for outputting a seventh pulse and the outputs from the seventh and eighth pulse output means are logically combined to output a ninth pulse having a phase difference of a delay time (T _o ). And a ninth pulse output means for controlling the timing of the output pulse of the ring delay pulse generating means, and the sixth pulse having a delay time (T _D ) and the ninth pulse to determine the timing. Claim 5 characterized by the above-mentioned.
The pulse phase difference encoding circuit described. 8. The plurality of signal delay means are connected in 2 ⁿ stages, and the orbital position detection means has a phase difference of a delay time (T _S ) with respect to an output pulse of the final stage of the ring delay pulse generation means. When the second pulse having an arbitrary phase difference from the first pulse is input, the timing determining means outputs a tenth pulse having a delay time ( Eleventh with a phase difference of T _B ).
Pulse output means for outputting the pulse, and output selecting means for selecting the second and eleventh pulses by the tenth pulse and outputting the twelfth pulse, the ring delay pulse generation 6. The pulse phase difference encoding circuit according to claim 5, wherein the timing is determined by the sixth pulse and the twelfth pulse having a delay time (T _D ) with respect to the output pulse of the means.