JP3416276B2 - Interference wave removal device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interference wave removing device for removing an interference wave mixed in an echo reception signal.

[0002]

2. Description of the Related Art When a sonar or radar receives an echo for a pulse wave transmission, a transmission wave of another sonar or radar of the same frequency (hereinafter referred to as sonar) directly enters a receiver and becomes an interference wave. Often happens. The amplitude of such an interference wave is usually extremely large, but the ultrasonic wave emission time of the sonar and its repetition frequency are different for each sonar, so the interference wave is present at the same distance point on the sweep line of the indicator of my sonar. There are few opportunities to appear consecutively.

FIG. 4 shows a so-called A by converting a received echo of a sonar into a digital signal at a predetermined sampling period.
In the example shown in the figure, the echo intensity is quantized into 7 steps of 0 to 6 and is shown on the vertical axis. Time t is
Sampling point numbers 0, 1, 2, ... 16, 17,
・ ・ Indicated by. If it is known that there is no echo beyond the sampling point 17, the quantization is stopped beyond that point, and the next sampling is started with the time point when the next ultrasonic pulse is emitted as the sampling point 0.

The echo indicated by x0 in FIG. 4 is an echo for a pulse wave transmitted recently, the echo indicated by x1 is an echo for a pulse wave transmitted one transmission cycle before x0, and indicated by x2, x3, x4 and x5. Those shown are echoes for pulse waves transmitted 2, 3, 4, and 5 transmission cycles before x0, respectively. Considering x0, it is considered that the echo at the sampling point No. 1 is an echo from the sea directly around its own reception or from the nearby sea surface, and the echoes at the sampling points Nos. 13, 14 and 15 are from the sea floor. Is considered to be an echo of sampling point 3,
The 5th echo is considered to be an echo from the school of fish, while the high level echo at the 11th sampling point is considered to be an interference wave. When observing x1 and x2, there is no echo at the sampling point 11 and x0
Since it appears suddenly in, it can be determined that this is an interference wave. Other parts of FIG. 4 will be described later.

FIG. 5 is a block diagram showing the structure of a conventional interference wave removing device. An echo signal input from an echo signal input terminal 1 is an A / D (analog-digital converter).
At 2, it is converted to digital data. A clock signal input from the clock signal input terminal 7 is used for sampling of this conversion. The output of the A / D 2 is input to the line memory 3. The line memory 3 is composed of, for example, a shift register, and if the output of the A / D 2 is quantized into 7 stages of 0 to 6 as in the example shown in FIG. 4, each data has 3 bits. Since it can be represented by a binary number, there are 1 to 20 sampling points per line (in the example shown in FIG. 4, only data of 1 to 15 sampling points exist, but a shift register has a margin). In this case, three shift registers of 20 stages are operated in parallel as shift registers, and binary 3-bit data is input to each shift register separately for each bit.

Since the output of the A / D 2 shifts in the shift register 3 with the same clock signal as the sampling clock, when the shift of 20 stages is completed, the line memory 3
The data of the sampling point No. 1 is input to the last stage of the line, and the data of the sampling point No. 20 (not present in the example of FIG. 4) is input to the first stage of the line memory 4. ing. At this point, sampling and shifting of the shift register 3 are stopped, and sampling and shifting of the shift register are restarted when the arrival of the echo of the next line starts. The data shifted out from the line memory 3 are sequentially input to the line memory 4, and new line data are input to the line memory 3.

The data on the line indicated by x0 in FIG. 4 is A / D.
Considering the time when the data is output from 2, the line memory 3
From the line memory 4 outputs the data of the line indicated by x1, and the line memory 4 outputs the data of the line indicated by x2. Then, the three data having the same sampling number are simultaneously output. For example, when the data "2" at the fifth sampling point on the x0 line is output, x1
The data "3" at the 5th sampling point of the line is output, and the data "5" at the 5th sampling point of the x2 line is output.
3 "is output. These three data are R at the same time.
The address signal of the OM 50 is input, and the data y from which the interference wave is removed is output from the ROM 50.

By the way, in the conventional device, x0, x1,
x2 three inputs (generally x0, x1, x2, ... x
The data in the ROM 50 is determined so as to output the smallest one out of (n + 1 inputs of n). When one data is represented by a 3-bit bit pattern and this is used as an address of the ROM 50 and n + 1 data are simultaneously input, the address of the ROM 50 is a bit pattern of the n + 1 data, that is, 3 × (n + 1) bits. It is represented by a bit pattern, and the address signal has 3 × (n + 1) bits. The data to be stored at the position of each address is determined by the program step of the flowchart of FIG.

That is, in the initialization step 60, x
Data of line 0 is defined as output data y, and step 61
Then, it is determined whether or not the data of the x1 line is not smaller than y. If it is not smaller, the process proceeds to step 62 as it is, and if it is smaller, the small numerical value is set to y in step 65, and x1 is thus set. When the comparison of all the data up to the xn line is completed, the minimum value in x1 to xn is determined as y, and this y is written as the data in the ROM 50.

[0010]

In the above-mentioned conventional interference wave removing device, since the minimum value in the data of each line is to be output, the interference wave can be removed, but it should not be removed. Echoes can be removed at the same time. That is, y0, y1, y2, y3 in FIG.
0, x1, x2 set, x1, x2, x3 set, x2, x
5 shows the interference wave elimination results obtained by the conventional apparatus shown in FIG. 5 from the group of 3x4 and the group of x3, x4, and x5. The small echo of 3 is eliminated, and the echo of sampling number 5 whose amplitude fluctuates between 2 and 3, the echo that should not be removed such as being fixed to the amplitude 2 is removed, or There was the problem of becoming inaccurate.

The present invention has been made in order to solve the above problems, and interference waves can be reliably removed, minute echoes are not erased, and amplitude fluctuations of fluctuating echoes can be displayed as they are. An object is to provide an interference wave removing device.

[0012]

The interference wave removing apparatus according to the present invention is designed to remove only interference waves having a change of a predetermined threshold value or more as interference waves. That is, the interference wave elimination device according to the present invention is an A / D converter for sampling a received echo signal for pulse wave transmission with a clock signal of a predetermined cycle and converting it into a digital signal, and an output of this A / D converter. A first line memory that holds a digital signal output corresponding to one transmission pulse at 1 o'clock, and when the output of the A / D converter is written to the first line memory, the first line memory is first written to the first line memory. Means for sequentially reading the written data in the order of writing and writing the data in the second line memory, where n is an integer determined by design, the n-1th line memory is the n-2th line memory (n = 1. When the data from the A / D converter is written, the data previously written in the (n-1) th line memory is sequentially read in the writing order. Means for writing into the line memory of the n Te, the A
The output of the D / D converter and the bit pattern of each output at the same distance points of the outputs of the first to nth line memories are used as an address, and output to the address position as an interference wave elimination output of each output. A ROM for storing the data to be output, wherein the data to be output is the A / D converter when the output of a level lower than the level obtained by subtracting a predetermined threshold from the output level does not exist. If there is an output that is lower than the level obtained by subtracting a predetermined threshold value from the output level of the A / D converter as the output of the A / D converter, the output is the lowest level output of those outputs. An address formed by connecting the bit patterns of the ROM stored as described above, the output of the A / D converter, and the output of the first to nth line memories is input to the ROM, Characterized by comprising a means for reading data to be output as a serial interference canceler output.

[0013]

[Operation] As for the interference wave, the ultrasonic pulse from another transmitter directly enters the receiver, or the ultrasonic pulse reflected from the shallow seabed is short. As described above, the amplitude is sufficiently large, and the pulse repetition period is different from the reception pulse repetition period, so it is uncertain at what sampling point it appears, so a certain threshold value is set. If the interference wave having only a predetermined change and a change equal to or larger than the threshold value is removed, the fluctuation of the echo whose amplitude changes within the threshold value is not removed.

[0014]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
In FIG. 1, the same reference numerals as those in FIG. 5 indicate the same or corresponding portions, only the data in the ROM 5 is different from the data in the ROM 50, and the ROM 5 stores different data according to a threshold value, and a desired ROM among them is stored. The threshold switch 6 for selectively using is used. Further, FIG. 2 is a flow chart for determining the data in the ROM 5, and corresponds to the flow chart of FIG.

Next, the operation will be described. In step 20 of initialization, if x0 is assumed to be y and the threshold value is a, in step 21, it is determined whether or not there is xD smaller than ya, and if not, the process proceeds to steps 22 and 23, and At 24, y (that is, x0) is output. If there is an xD smaller than ya in step 21, the xD is set to y (step 25), and y is thereafter set.
If there is a smaller xD, it is set as a new y, and after the comparison with respect to all xDs is completed, the value of y is written as data in the ROM 5.

When a = 2, the echo y03 after the interference wave output by the apparatus of FIG. 1 is removed for x5 to x0 of FIG.
.About.y00 (corresponding to y3 to y0 in FIG. 4) is as shown in FIG. That is, although the interference wave has a difference of amplitude value 2 or more, it is removed, but the echoes of sampling numbers 3 and 5 remain as they have no difference of amplitude value 2 or more, and the interference wave of sampling number 9 is removed. At this position, an echo with an amplitude of 2 or an echo with an amplitude of 0 will remain, and the result will be that only the interference wave is erased. The same result is obtained even if a = 3.

A logic circuit can be used instead of the ROM 5. FIG. 3 is a logic circuit that determines y for inputs of three lines x0, x1 and x2. Threshold values are stored in registers 42, 43 and 44, respectively, and selected by a threshold switch 45. The adder 30 adds the threshold value to x1, the adder 31 adds the threshold value to x2, and the subtracters 33 and 34 compare with x0. If the comparison result corresponds to YES in step 21 of FIG. 2, the value of x0 is output as y via the gates 39 and 41. If either or both of the outputs of the subtracters 33 and 34 correspond to NO in step 21 of FIG. 2, x
0 is blocked by the gate 39, and one of x1 and x2 that is smaller in the comparison by the subtractor 32 is the gate 35, 36, 3
It is output via 7, 40, 41.

It goes without saying that the logic circuit of FIG. 3 can be constructed by program control by a computer.
The program step shown in FIG. 2 is a program step for executing offline and writing in the ROM 5, but if this program step is executed at extremely high speed, it is also possible to determine the value of the output y online. . In the embodiment shown in FIG. 1, the data x0 for one line at present is compared with the data x0 for two lines immediately before that.
Although the example using 1 and x2 has been described, this is not limited to two lines, and x1, x2, x3, ...
-Data for n lines of xn can be used. Further, although the present invention has been described with respect to the interference wave removal of ultrasonic echoes in the above embodiments, it is needless to say that the present invention can be applied to the interference wave removal of radar echoes as described above.

[0019]

As described above, according to the present invention, an interference wave can be reliably removed, and a minute echo whose amplitude is sometimes 0 is erroneously erased or an echo having an amplitude fluctuation. There is an effect that it is possible to obtain an interference wave removing device that does not erroneously fix the amplitude of the.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flow chart showing steps for determining data in the ROM of FIG.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a waveform diagram on an A scope showing one line of a reception echo.

FIG. 5 is a block diagram showing an example of a conventional device.

FIG. 6 is a flowchart showing steps for determining data in the ROM 50 of FIG.

FIG. 7 is a waveform diagram on the A scope showing the effect of the present invention.

[Explanation of symbols]

1 signal input terminal 2 analog-digital converter 3 line memory 4 line memory 5 ROM 6 threshold switch 7 Clock signal input terminal

Continuation of the front page (56) References JP 57-114872 (JP, A) JP 5-126940 (JP, A) JP 4-98182 (JP, A) JP 1-212381 (JP , A) JP 56-21078 (JP, A) JP 3-57983 (JP, A) JP 6-59035 (JP, A) JP 1-172789 (JP, A) 57-149475 (JP, U) Actual development Sho 55-100179 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) G01S 1/72-1/82 G01S 3/80-3 / 86 G01S 5/18-5/30 G01S 7/00-7/64 G01S 13/00-13/95 G01S 15/00-15/96

Claims (5)

(57) [Claims] 1. An A / D converter for sampling a received echo signal for pulse wave transmission with a clock signal of a predetermined cycle and converting it into a digital signal, which corresponds to one transmission pulse output from the A / D converter. A first line memory that holds a digital signal output at 1 o'clock, and when the output of the A / D converter is written in the first line memory, the previously written data is written in the first line memory. In turn, read sequentially
Writing means to the line memory of No., when n is an integer determined by design, the data from the n-2th line memory (the above A / D converter when n = 1) is written to the n-1th line memory. When written,
Means for sequentially reading the data previously written to the (n-1) th line memory in the order of writing and writing the data to the nth line memory, the output of the A / D converter, and the first to nth line memories. The concatenation of the bit patterns of the outputs at the same distance of the outputs is used as an address, and the data to be output as the interference wave elimination output of the outputs is stored at the address position R
In the case of OM, the data to be output is the A / D converter when there is no output having a level lower than the level obtained by subtracting a predetermined threshold value from the output level of the A / D converter.
If there is an output of the converter which is lower than the level obtained by subtracting a predetermined threshold value from the output level of the A / D converter, the output of the lowest level among those outputs is set. The stored ROM, the address of the output of the A / D converter, and the bit pattern of the output of the first to nth line memories are connected to the ROM to input the address, and the interference wave is removed from the ROM. An interference wave removing device comprising means for reading data to be output. 2. The ROM is made different for each of the predetermined threshold values, and these R are
The interference wave removing apparatus according to claim 1, further comprising a threshold switch for selectively using any one ROM of the OM. 3. An A / D converter for sampling a received echo signal for pulse wave transmission with a clock signal of a predetermined cycle and converting it into a digital signal, which corresponds to one transmission pulse of the output of this A / D converter. A first line memory that holds a digital signal output at 1 o'clock, and when the output of the A / D converter is written in the first line memory, the previously written data is written in the first line memory. In turn, read sequentially
Writing means to the line memory of No., when n is an integer determined by design, the data from the n-2th line memory (the above A / D converter when n = 1) is written to the n-1th line memory. When written,
Means for sequentially reading the data previously written to the (n-1) th line memory in the order of writing and writing the data to the nth line memory, the output of the A / D converter, and the first to nth line memories. When the outputs at the same distance are compared and there is no output having a level lower than the level obtained by subtracting a predetermined threshold value from the output level of the A / D converter, the A / D
When the output of the converter is used as the interference wave elimination output and there is an output of a level lower than the level obtained by subtracting a predetermined threshold value from the output level of the A / D converter, the lowest level of those outputs is detected. An interference wave elimination device comprising: a logic circuit whose output is the interference wave elimination output. 4. The logic circuit according to claim 3, wherein the logic circuit is configured by program control by a computer.
The interference wave removing device according to the item. 5. The logic circuit includes a plurality of registers in which different values of the predetermined threshold value are set, and a threshold value switch for selecting and using any one of the registers. The interference wave removing device according to claim 3 or 4, further comprising: