JP3412566B2 - Offset voltage detection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an offset voltage detecting circuit for detecting an offset voltage of a differential circuit having a differential structure.

[0002]

2. Description of the Related Art Conventionally, an offset voltage detecting circuit of a differential circuit having such a differential structure is disclosed in, for example, Japanese Patent Laid-Open No. 4-247.
As disclosed in Japanese Laid-Open Patent Publication No. 705, it is formed by using a plurality of switches that perform anti-reverse operation. For example, in order to reduce noise due to ON / OFF of a plurality of switches used for offset voltage detection with respect to the detected offset voltage, timings in which two switch groups provided respectively for differential inputs of a differential circuit conflict with each other The technology of turning on / off is used.

FIG. 6 is a circuit diagram of an offset voltage detection circuit showing an example of such a conventional technique. As shown in FIG. 6, the detection circuit 1 for detecting the offset voltage of the conventional differential circuit 3 is
Four switches SW1 to SW4 and inverting gate INV
1, the input signal VIN and the reference signal V to be processed
REF and control signal PLS are supplied. These VI
N and VREF are differential lines (nodes) N3 and N4 of the differential circuit 3 when the offset voltage is not detected.
Are input respectively.

First, the input signal VIN is input to the switch SW1 through the node N1, and the reference signal VREF is input to the switches SW2 to SW4 through the node N2.
The other ends of the switches SW1 and SW2 and one input of the differential input of the differential circuit 3 are connected to the node N3. Also,
The other ends of the switches SW3 and SW4 and the other input of the differential input of the differential circuit 3 are connected to the node N4. These switches SW1 and SW4 are turned ON / O by the control signal PLS.
The switches SW2 and SW3 are turned on / off by the output of the inversion gate INV1 which inverts the control signal PLS.

When the control signal PLS for controlling the operation of the switches SW1 to SW4 is at "H" level, the switches SW1 and SW4 are in the ON state, and the switches SW2 and S are in the ON state.
W3 is in the OFF state, and when PLS is at the "L" level, the operation state opposite to "H" is entered. In short, the switches SW1 and SW4 and the switches SW2 and SW3 are turned on / off at timings opposite to each other.

Specifically, since the control signal PLS is at "H" level during the period in which the offset voltage for the differential circuit 3 is not detected, the switch SW is in this state.
1, the input signal VIN is input to the differential circuit 3, and the reference voltage VREF is input to the differential circuit 3 via the switch SW4.

Further, since the control signal PLS is at "L" level during the offset voltage detection period, the switch SW
2, SW3 turns on, switches SW1, SW4 turn off
Becomes In this state, only the reference signal VREF is input to both differential inputs of the differential circuit 3 through the switches SW2 and SW3. That is, the input signal VIN is separated from the differential circuit 3, and regardless of the input signal VIN, a signal of equal potential is input to the differential input of the differential circuit 3, and the differential circuit 3 receives The offset voltage can be detected.

The differential input node N of the differential circuit 3
In order to equalize the noise generated by the switching of the switches with respect to 3 and N4, the number of switches through which the signal passes is the same. Moreover, these switches SW1 to SW
4 is an electrically equal switching characteristic. By doing so, noise of the same level appears in the differential input of the differential circuit 3 in the same phase, and at the output (not shown) of the differential circuit 3,
The influence of the noise is reduced, and the offset voltage can be detected with high accuracy.

[0009]

However, in the above-mentioned conventional offset voltage detection circuit, the symmetry in the differential line is lost and the impedance becomes unbalanced, which is an advantage of the differential configuration. There is a problem that the reduction of the influence of noise and power supply voltage fluctuation is weakened. Specifically, while the input signal VIN is input to one switch (only the switch SW1), the reference signal VR is input.
There are three switches to which EF is input (switches SW2 to S
W4). That is, since there is a difference in the number of connected switches having the same characteristics at both input terminals (VIN, VREF) of the offset voltage detection circuit, there is a disadvantage that the parasitic capacitances at both input terminals are different.

Further, even if in-phase noise is generated by the plurality of switches SW1 to SW4, it is not possible to reduce the noise more than the noise reduction determined by the in-phase signal rejection ratio (CMMR) of the differential circuit. There is a drawback that noise remains in the output of.

An object of the present invention is to provide an offset voltage detection circuit which realizes such an accurate detection of an offset voltage and eliminates noise due to a switch group for disconnecting an input signal from a circuit whose offset voltage is to be detected. To do.

[0012]

An offset voltage detection circuit according to the present invention is an offset voltage detection circuit for connecting a signal source and a comparison voltage source to a differential line of a differential circuit. First and second switches respectively connecting the comparison voltage source to one differential line of the differential circuit, the one signal source and the comparison voltage source are input, and the output is the other of the differential circuit. And an impedance adjusting circuit connected to the differential line, the first and second switches are operated in reverse, and the electrical characteristics of the differential line through which a signal to the differential circuit passes are made equal. Composed.

The impedance adjusting circuit is formed by third and fourth switches respectively connecting the one signal source and the comparison voltage source to the other differential line of the differential circuit. The four switches are formed so as to be always off and always on, respectively.

The offset voltage detection circuit of the present invention is the offset voltage detection circuit for connecting one signal source and a comparison voltage source to a differential line of a differential circuit, wherein the one signal source and the comparison voltage source. And a second switch for connecting each of them to one differential line of the differential circuit, the one signal source and the comparison voltage source, and outputs the other differential line of the differential circuit. An impedance adjustment circuit connected to the differential circuit and a clamp means connected between the differential lines of the differential circuit to reversely operate the first and second switches, and a signal to the differential circuit passes. The differential lines have the same electrical characteristics.

The impedance adjusting circuit is formed by third and fourth switches respectively connecting the one signal source and the comparison voltage source to the other differential line of the differential circuit, and also the third and fourth switches. The fourth switch is normally turned off and normally turned on, respectively, and the clamp means is formed by the fifth and sixth switches and supplies a constant voltage to the connection point thereof to turn on the first and second switches. The fifth and sixth switches are turned on at least once every switching between ON and OFF, and then the O
It is formed to control the FF state.

Further, the offset voltage detection circuit of the present invention is an offset voltage detection circuit for connecting one signal source and a comparison voltage source to a differential line of a differential circuit, wherein the one signal source and the comparison voltage source. And a second switch for connecting each of the differential circuits to one differential line of the differential circuit, and the one signal source and the comparison voltage source to one and the other differential lines of the differential circuit, respectively. And an impedance adjusting circuit for operating the first and second switches in an antithetical manner, and making the electrical characteristics of the differential lines through which signals to the differential circuit pass equal.

This impedance adjustment circuit connects the comparison voltage source to the other differential line of the differential circuit, and third and fourth switches that operate in a mutually opposite manner, and the one signal source, respectively. And a fifth switch and a sixth switch which are connected to one and the other differential lines of the differential circuit and are always turned off.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an offset voltage detection circuit for explaining an embodiment of the present invention. As shown in FIG. 1, this embodiment also shows an offset voltage detection circuit 1 and a differential circuit 3 which is an offset voltage detection target, and includes a first switch SW1 (connected to a node N1 supplied with an input signal VIN). ON at H level, OFF at L level,
The same applies hereinafter) and the node N supplied with the reference signal VREF.
The second switch SW2 connected to the input signal VI
N and the reference signal VREF are input terminals IN1 and I, respectively.
The impedance adjusting circuit 2 that is supplied to the N2 and is connected to the high voltage source VDD and controls the connection to the output terminal OUT, and the inverting gate I that inverts the control signal PLS.
NV1 and ON / OF of the first and second switches SW1 and SW2 depending on the control signal PLS and its inverted signal.
It controls F. Note that VIN, VREF, and PLS are the same as those described in the related art.

That is, the input signal VIN is input to the switch SW1 and the input IN1 of the impedance adjustment circuit 2 through the node N1, and the reference signal VREF is input to the switch SW2 and the input IN2 of the impedance adjustment circuit 2 through the node N2.

Since the switches SW1 and SW2 are driven by the control signal PLS and its inverted signal,
Turns ON / OFF at the opposite timing.

Further, the impedance adjusting circuit 2 is basically adapted to output the signal inputted to the input IN2, and the impedances of the nodes N3 and N4 and the impedances of the nodes N1 and N2 are basically set. They are designed to be equal.

In such an offset voltage detection circuit,
During the period when the offset voltage is not detected, the control signal P
LS is at "H" level, the switch SW1 is ON and the switch SW2 is OFF. In this state, the switch S
The input signal VIN is input through W1 and the reference signal VREF is input through the impedance adjustment circuit 2 to the differential lines (nodes) N3 and N4 of the differential circuit 3, respectively.

On the other hand, on the contrary, during the offset voltage detection period, the control signal PLS is at "L" level and the switch S
W2 turns on and switch SW1 turns off. In this state, the reference signal VREF is input to the differential line of the differential circuit 3 through the switch SW2 and the impedance adjusting circuit 2. That is, the input signal VIN is separated from the differential circuit 3, and regardless of the input signal VIN, signals of equal potential are input to the differential lines, and the differential circuit 3
The offset voltage of can be detected.

In short, this impedance adjusting circuit 2
Because the symmetry of the circuit is maintained by the differential line,
The reduction of the effects of common mode noise and power supply voltage fluctuation, which is an advantage of the differential configuration, is not impaired.

FIG. 2 is a circuit diagram of an offset voltage detection circuit showing a first embodiment of the present invention. As shown in FIG. 2, the present embodiment is an example in which the impedance adjusting circuit 2 in the offset voltage detecting circuit 1 is formed by the third switch SW3 and the fourth switch SW4.
W3 is connected between VIN and the differential line N4, and the fourth switch SW4 is connected between VREF and the differential line N4.
The switch SW3 has a high voltage source VDD and an inverting gate INV2.
ON / OFF of the switch SW4 is controlled via the reference signal VREF.

In the adjusting circuit 2, the high voltage source VD
Since D is logically at the H level, the switch SW4 is always on and the switch SW3 is always off.

However, during the period in which the offset voltage is not detected, the control signal PLS is at "H" level, the switch SW1 is turned on and the switch SW2 is turned off. Therefore, in this state, the input signal VI is passed through the switch SW1.
N and the reference voltage VREF are input to the differential circuit 3 through the switch SW4.

On the other hand, during the offset voltage detection period, the control signal PLS is at "L" level and the switch SW2 is O.
N, the switch SW1 is turned off, so in this state,
The reference signal VREF is input to the differential inputs N3 and N4 of the differential circuit 3 through the switches SW2 and SW4. That is, the input signal VIN is separated from the differential circuit 3, and a signal of equal potential is input to the differential input of the differential circuit 3 regardless of the input signal VIN, and the offset voltage of the differential circuit 3 is input. Can be detected.

When the switches SW1 to SW4 have the same characteristics, the number of switches connected to the input signal VIN is equal to the number of switches connected to the reference signal VREF, so that the node N1 to which the input signal VIN is connected. And the reference signal VREF are connected to each other, the node N2 has the same impedance. Similarly, the number of switches connected to the node N3 and the node N4 is equal, and the impedances of the nodes N3 and N4 are also equal. That is, the differential line N3
Since the circuit symmetry is maintained at N4, the reduction of the effects of common mode noise and power supply voltage fluctuation, which is an advantage of the differential configuration, is not impaired. Furthermore, by making the characteristics of the inverting gates INV1 and INV2 equal, the effect of the differential configuration can be further enhanced.

Here, as a specific example of the switches SW1 to SW4 used in the offset voltage detection circuit 1, a MOS transistor having a drain, a source and a gate electrode may be used. In such a MOS switch, the gate G controls ON / OFF of the switch, and the drain D and the source S serve as input / output terminals of the switch. Moreover, if the switches SW1 to SW4 are composed of MOSFETs having the same shape, it is possible to sufficiently reduce the effects of common-mode noise and power supply voltage fluctuations even with variations in MOSFETs in a general process.

FIG. 3 is a circuit diagram of an offset voltage detecting circuit showing a second embodiment of the present invention. As shown in FIG. 3, in the present embodiment, the impedance adjustment circuit 2 in the offset voltage detection circuit 1 is formed by the third switch SW3 and the fourth switch SW4, and the differential line N3.
The fifth and sixth switches SW5 and SW6 are provided as clamp means connected in series between N4 and supplied with the constant voltage V1 at the midpoint thereof. Moreover, the switches SW5 and SW6 are controlled to be turned on / off by the second control signal FCP different from the first control signal PLS.

This embodiment is a circuit applied to a correlated double sampling circuit (hereinafter abbreviated as a CDS circuit) having a differential structure. Compared with the first embodiment described above, the switches SW1 and SW2 are inverted. The same applies in that the gates INV1 and INV2 and the impedance adjusting circuit 2 are used. The capacitors C1 and C2 are clamp capacitors.

The difference between the two embodiments is that the switch SW1
And switch SW on node N3 to which the other ends of SW2 and SW2 are connected
5 is connected, the switch SW6 is connected to the node N4 to which the switches SW3 and SW4 are connected, and the other ends of these switches SW5 and SW6 are connected to the constant voltage source V1. It is turned on / off by the control signal FCP of 2. The node N3 is connected to the sample hold circuit SH1 forming the differential circuit 3, and the node N4 is connected to the sample hold circuit SH2. These sample and hold circuits SH1 and SH2 perform sampling and holding operations by another control signal SHP, and the sample and hold circuit SH1 outputs VOUT1 and the sample and hold circuit SH2 outputs the operation result as VOUT2.

The differential lines N1, N2 and N
The characteristics of the circuit elements facing each other are made equal by 3 and N4.
Specifically, capacitors C1 and C2 and switch SW5
And SW6 and the sample and hold circuits SH1 and SH2 have the same characteristics. As described in the first embodiment, the switches SW1 to SW4 have the same characteristics, and the inversion gates INV1 and INV2 have the same characteristics.

Also in this embodiment, since the high voltage source VDD is logically at the "H" level, the switch SW4 is always controlled at the "H" level, so the switch SW4 is always in the ON state. Further, since the switch SW3 is controlled by the output of the inverting gate INV2, the switch SW3 is always controlled at the "L" level and is always in the OFF state. Further, since the switches SW5 and SW6 are both controlled by the same second control signal FCP, they are turned on / off at the same timing.
Turn off. The sample hold circuits SH1 and SH
If the pulse signal SHP applied to H2 is at "H" level, the sample hold circuits SH1 and SH2 are in the sampling state, and if it is at "L" level, the hold state.

Next, the operation of the CDS circuit having the offset voltage detecting function will be described. First, during the period when the offset voltage is not detected, the control signal PLS is "
At the H "level, the switch SW1 is in the ON state and the switch SW2 is in the OFF state. When the second control signal FCP is applied to the CDS circuit in this state, the following CDS
The original operation of the circuit can be obtained.

In the initial state, the control signal FCP is "L".
At the level, the switches SW5 and SW6 are off, the pulse signal SHP is at the "L" level, and the sample hold circuits SH1 and SH2 are in the hold state. Then, when the control signal FCP is set to "H" level, the switches SW5 and SW6 are turned on, and the nodes N3 and N4 are clamped to the potential of the constant voltage source V1. Then, the control signal F
CP is set to "L" level, and switches SW5 and SW6 are turned off. Unless the signals VIN and VREF change, the potentials of the nodes N3 and N4 maintain the clamped potential. When the input signal VIN changes in this state, a potential change corresponding to the clamped potential of the input signal VIN appears at the node N3 through the switch SW1. Here, in the CDS circuit having the differential configuration, the normal reference signal VREF is a DC stable signal such as ground. Therefore, the reference voltage VREF, which is stable in terms of direct current and is transmitted through the switch SW4, causes the node N
The potential of 4 remains the clamped potential. afterwards,
By setting the pulse signal SHP to the “H” level, the sample hold circuits SH1 and SH2 are set to the nodes N3 and N4.
The potential appearing at is sampled. Subsequently, the pulse signal SHP is set to the “L” level, so that the sample hold circuits SH1 and SH2 enter the hold state. As a result, the potential difference between the output signals VOUT1 and VOUT2 is
Input signal VI from clamp period to sampling period
The amount of change in N is retained. The series of operations described above is the CDS
This is the original operation. Hereinafter, by repeating the above operation,
Input signal VI from clamp period to sampling period
A CDS circuit that outputs only the amount of change in N is realized.

Subsequently, during the offset voltage detection period, the control signal PLS is at "L" level, so that the switch SW1 is in the OFF state and the switch SW2 is in the ON state. In this state, even if the input signal VIN changes, since the switch SW1 is OFF, it does not affect the circuits after the switches SW1 to SW4 for detecting the offset voltage. Moreover, since the switches SW2 and SW4 are in the ON state, the nodes N3 and N4 are always at the same potential. When the original operation of the CDS circuit described above is performed in this state, only the offset voltage generated due to the characteristic variation of the elements constituting the circuits after the switches SW1 to SW4 for detecting the offset voltage does not depend on the change of the input signal VIN. Can be accurately detected.

Further, as in the first embodiment described above, by making the characteristics of all the switches the same, the number of switches connected to the node N1 and the node N2 is equal, and the node N is the same.
3 and the number of switches connected to the node N4 are equal, the nodes N1 and N2, and the nodes N3 and N
The impedance of 4 becomes equal. That is, since the circuit symmetry is maintained in both differential lines, it is effective in reducing the effects of common mode noise and power supply voltage fluctuation, which are advantages of the differential configuration.

Here, the switches SW1 and SW2 are used for switching between the offset voltage detection period and other periods.
As a result, noise is generated at the nodes N3 and N4. This noise is a control signal FCP in the original operation of the CDS circuit.
Switch to "H" level, switches SW5 and SW6
Is turned on and the nodes N3 and N4 are clamped to the potential of the constant voltage source V1 to be eliminated. That is, noise generated in the switches SW1 and SW2 can be eliminated by performing the original operation of the CDS circuit at least once in each of the offset voltage detection period and the other period, and the offset voltage can be detected with high accuracy.

In the offset voltage detection period, the switch CW1 is turned off to disconnect the capacitor C1 from the node N3. However, since the capacitor C2 is connected to the node N3 through the switch SW2, the switch C1 is generated from the switch SW5 by the clamp operation. The noise at node N3 is further reduced by capacitor C2. That is, simply by disconnecting the input signal VIN with the switch SW1, the node N3 indicating whether or not there is a capacitor connected to the node N3 during the offset voltage detection period and the period other than that is detected.
Due to the difference in the circuit connection state, the amount of noise generated at the node N3 by the switch SW5 varies. However, as described above, when the capacitor C2 is connected to the node N3 through the switch SW2, the node N3
Since the circuit connection state of is the same during the offset voltage detection period and other periods, the node N by the switch SW5 is
The noise generated in 3 is also equal, and the offset voltage can be detected with higher accuracy.

FIG. 4 is a circuit diagram of an offset voltage detecting circuit showing a third embodiment of the present invention. As shown in FIG. 4, this embodiment is different from the above-described first embodiment in that the impedance adjusting circuit 2 is composed of four switches SW3, SW4 and SW7, SW8, and its connection destination and ON state.
There is a difference in the ON / OFF control. That is, VI
Switch SW1 and VREF connecting N and node N3
SW3 that connects the node N4 to the node N4 is turned on by the control signal PLS
The switch SW2 connecting VREF and the node N3 and the switch SW4 connecting VREF and the node N4 are turned on / off by the output of the inverting gate INV1. The switch SW7 connecting VIN to the node N3 and SW8 connecting VREF to the node N4 are turned on / off by the output of the inverting gate INV2 whose input is fixed to the high voltage source VDD.

Here, the switches SW1 and SW3 and the switches SW2 and SW4 are turned on / off at opposite timings.
However, since the switches SW7 and SW8 are always controlled at the "L" level, they are always off.

First, while the offset voltage is not detected, the control signal PLS is at "H" level, the switches SW1 and SW3 are turned on, and the switches SW2 and SW are turned on.
4 is off, the input signal VIN passes through the switch SW1 and the reference voltage V passes through the switch SW3.
REF is input to the differential circuit 3.

On the other hand, during the offset voltage detection period, the control signal PLS is at "L" level, the switches SW2 and SW4 are ON, and the switches SW1 and SW3 are OFF. Therefore, the differential circuit 3 is passed through the switches SW2 and SW4. The reference signal VREF is input to the differential inputs N3 and N4. That is, the input signal VIN is separated from the differential circuit 3, and regardless of the input signal VIN, a signal of equal potential is input to the differential input of the differential circuit 3, and the differential circuit 3 receives The offset voltage can be detected.

In addition, the differential input node N of the differential circuit 3
In order to equalize the noise caused by the switching of the switches in 3 and N4, the number of switches through which the signal passes is the same. Specifically, during the offset voltage control period, a signal is input to the node N3 through the switch SW2 and a signal is input to the node N4 through the switch SW4. In the other periods, signals are input to the node N3 through the switch SW1 and the node N4 through the switch SW3. And these switches SW1
~ SW4 have equal characteristics. By doing so, noise of the same level appears in the differential input of the differential circuit 3 in the same phase, so that the influence of the noise is reduced in the output of the differential circuit 3 and an accurate offset voltage can be detected. it can.

Further, the switch SW which is always off
7 and SW8 have the same characteristics as the switches SW1 to SW4. By making the characteristics of all the switches the same, the number of switches connected to the node N1 and the node N2
The number of switches connected to each other becomes equal, and the impedances of the node N1 and the node N2 to which the reference signal VREF is supplied become equal. Similarly, the number of switches connected to the node N3 and the node N4 is equal, and the nodes N3 and N4 are the same.
The impedances of are also equal. That is, since the symmetry of the circuit is maintained in the differential line, the reduction of the influence of common-mode noise and power supply voltage fluctuation, which is an advantage of the differential configuration, is not impaired. Further, by making the characteristics of the inverting gates INV1 and INV2 equal, it is possible to obtain a large effect of the differential configuration.

Here, the switches SW1 to SW4 and SW
If 7 and SW8 are composed of MOSFETs of the same shape, it is possible to sufficiently reduce the effects of common-mode noise and power supply voltage fluctuations even with variations in MOSFETs in a general process.

FIG. 5 is a circuit diagram of an offset voltage detecting circuit showing a fourth embodiment of the present invention. As shown in FIG. 5, this embodiment is the same as the second embodiment shown in FIG. 3 and the third embodiment shown in FIG.
The present invention is applied to a CDS circuit having a differential structure in combination with the embodiment of FIG.

Also in this embodiment, the characteristics of the circuit elements facing each other on the differential line are made equal. Specifically, similarly to the above-described embodiment, the capacitors C1 and C2, the switches SW5 and SW6 as the clamp means, and the sample hold circuits SH1 and SH2 have the same characteristics. Further, the switches SW1 to SW6 have the same characteristics, and the inversion gates INV1 and INV2 also have the same characteristics.

Here, the switches SW1 and SW
Since 3 is controlled by the same control signal PLS, they are turned on / off at the same timing, and switches SW2 and SW4
Are both controlled by the output of the inversion gate INV1, so they are turned on / off at the same timing. Similarly, the high voltage source V
DD is logically at "H" level, and the switch SW7
And SW8 are controlled by the output of the inverting gate INV2, these switches SW7 and SW8 are always "L".
It is controlled by level. That is, it is always off. Further, since the switches SW5 and SW6 are both controlled by the same control signal FCP, they are turned ON / O at the same timing.
FF.

Further, if the pulse signals applied to the sample hold circuits SH1 and SH2 are "H" level, the sample hold circuits SH1 and SH2 are in sampling state, and if the pulse signals are "L" level, they are in hold state.

First, in the period in which the offset voltage is not detected, that is, in the initial state, the first control signal FCP is set.
Is "L" level, switches SW5 and SW6 are OFF,
The second control signal SHP is at "L" level and the sample hold circuits SH1 and SH2 are in the hold state. Then, by setting the control signal FCP to the “H” level,
Switches SW5 and SW6 are turned on, and nodes N3 and N
4 is clamped to the potential output by the constant voltage source V1. Then, the pulse signal FCP is set to "L" level, and the switches SW5 and SW6 are turned off. Therefore, the input signal V
If IN and the reference signal VREF do not change, the node N
The potentials of 3 and N4 maintain the clamped potential. When the input signal VIN changes in this state, the switch SW1
Through, the potential of the node N3 changes by the amount corresponding to the change of the input signal VIN with respect to the clamped potential. Here, in the CDS circuit having the differential configuration, the reference signal VREF is usually a DC stable signal such as ground. Therefore, the potential of the node N4 continues to be the clamped potential due to the DC-stabilized reference voltage VREF transmitted through the switch SW3. After that, by setting the pulse signal SHP to the “H” level, the sample hold circuits SH1 and SH2 sample the potentials appearing at the nodes N3 and N4. Then, the pulse signal SHP
To the "L" level, the sample hold circuit S
H1 and SH2 are in the hold state. As a result, the potential difference between the output signals VOUT1 and VOUT2 holds the amount of change in the input signal VIN from the clamp period to the sampling period. Although the series of operations described above is the original operation of CDS, by repeating this operation, it is possible to realize a CDS circuit that outputs only the change amount of the input signal VIN from the clamp period to the sampling period.

On the other hand, during the offset voltage detection period, the control signal PLS is at "L" level, and therefore the switch S
W1 and SW3 are in OFF state, switches SW2 and SW
4 is an ON state. In this state, even if the input signal VIN changes, the change is that the input signal VIN changes to the capacitor C.
Switch SW1, SW7 and SW8 input through 1
Are OFF, the offset voltage detection switches SW1 to SW4 and SW7 and SW8 do not affect the subsequent circuits, and the switches SW2 and SW4 are not affected.
Is on, the nodes N3 and N4 are always at the same potential. In this state, by performing the original operation of the CDS circuit described above, the switches SW1 to SW4 for detecting the offset voltage are irrespective of the change of the input signal VIN.
Also, it is possible to accurately detect only the offset voltage generated due to the characteristic variation of the elements that form the circuits after SW7 and SW8.

Further, as in the third embodiment described above, by making the characteristics of all the switches the same, the number of switches connected to the nodes N1 and N2 is equal, and the switches are connected to the nodes N3 and N4. Since the number of switches is the same, node N1 and node N2 and node N3 and node N
The impedance of 4 becomes equal. That is, since the symmetry of the circuit is maintained in the differential line, the reduction of the influence of common-mode noise and power supply voltage fluctuation, which is an advantage of the differential configuration, is not impaired.

Then, the switches SW1 to SW4 and S
If W7 and SW8 and the switches SW5 to SW6 are MOSFETs of the same shape, it is possible to sufficiently reduce the effects of common-mode noise and power supply voltage fluctuations even if the MOSFETs vary in a general process.

Here, at the time of switching between the offset voltage detection period and other periods, noise is generated in the nodes N3 and N4 by the switches SW1 to SW4. This noise causes the control signal FCP in the original operation of the CDS circuit
The switches SW5 and SW6 are turned to O by setting the H "level.
It is eliminated by the operation of setting the node N and clamping the nodes N3 and N4 to the potential of the constant voltage source V1. In other words, the switch SW is operated by performing the original operation of the CDS at least once in each of the offset voltage detection period and the other period.
The noise generated in 1 to SW4 can be eliminated, and the offset voltage can be detected with high accuracy.

In the offset voltage detection period, the switch CW1 is turned off to disconnect the capacitor C1 from the node N3. However, since the capacitor C2 is connected to the node N3 through the switch SW2, the clamp operation causes the switch C5 to occur. The noise at the node N3 is reduced by the capacitor C2. That is, if the input signal VIN is separated by the switch SW1,
During the offset voltage detection period and other periods, the node N3
Since there is a difference in the circuit connection state of the node N3 depending on the presence or absence of a capacitor connected to the node N3, the amount of noise generated at the node N3 by the switch SW5 is different. However, when the capacitor C2 is connected to the node N3 through the switch SW2 as described above, the circuit connection state of the node N3 becomes the same during the offset voltage detection period and the other period, and therefore occurs at the node N3 by the switch SW5. Noise is also equalized, and more accurate offset voltage detection can be performed.

Although the embodiments and examples of the present invention have been described with reference to the drawings, the present invention is not limited to the illustrated embodiments and the like, and various modifications can be made by those skilled in the art without departing from the scope of the present invention. It goes without saying that it can be modified.

[0061]

As described above, the offset voltage detection circuit according to the present invention is designed so that the characteristic of the differential line input to the differential circuit of the offset voltage detection target is always symmetrical so that the offset voltage detection target of the offset voltage detection target is detected. There is an effect that the reduction of the influence of common mode noise and power supply voltage fluctuation, which is an advantage of the differential circuit, is not lost.

Further, according to the present invention, a clamp circuit is provided in a stage subsequent to a switch group for disconnecting an input signal and a switch group for short-circuiting a differential input from a differential circuit for an offset voltage detection, and an offset voltage detection period and a period other than that. By providing the means for performing the clamp operation at least once, it is possible to eliminate the noise of the switch that operates at the time of switching between the offset detection period and other periods, and it is possible to detect a highly accurate offset voltage.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an offset voltage detection circuit for explaining an embodiment of the present invention.

FIG. 2 is a circuit diagram of an offset voltage detection circuit showing a first embodiment of the present invention.

FIG. 3 is a circuit diagram of an offset voltage detection circuit showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram of an offset voltage detection circuit showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram of an offset voltage detection circuit showing a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram of an offset voltage detection circuit showing a conventional example.

[Explanation of symbols]

1 Offset voltage detection circuit 2 Impedance adjustment circuit 3 differential circuit N1 to N4 nodes SW1 to SW8 switches C1, C2 capacitors SH1, SH2 sample and hold circuit INV1, INV2 Inversion gate VDD high voltage source V1 constant voltage source

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03F 3/34 H03K 5/08

Claims (6)

(57) [Claims] 1. An offset voltage detection circuit for connecting one signal source and a comparison voltage source to a differential line of a differential circuit, wherein the one signal source and the comparison voltage source are respectively connected to one of the differential circuits. A first and a second switch connected to the differential line; and an impedance adjustment circuit for inputting the one signal source and the comparison voltage source and connecting an output to the other differential line of the differential circuit. Then, the first and second switches are operated in the opposite direction,
An offset voltage detection circuit, wherein the electrical characteristics of the differential lines through which signals to the differential circuit pass are made equal. 2. The impedance adjusting circuit comprises:
One signal source and the comparison voltage source are formed by third and fourth switches respectively connected to the other differential line of the differential circuit, and the third and fourth switches are normally turned off and always turned on, respectively. The offset voltage detection circuit according to claim 1. 3. An offset voltage detection circuit for connecting one signal source and a comparison voltage source to a differential line of a differential circuit, wherein the one signal source and the comparison voltage source are respectively connected to one of the differential circuits. A first and a second switch connected to a differential line; an impedance adjustment circuit for inputting the one signal source and the comparison voltage source and connecting an output to the other differential line of the differential circuit; Clamping means connected between the differential lines of the differential circuit to reversely operate the first and second switches, and to detect electrical characteristics of the differential line through which a signal to the differential circuit passes. An offset voltage detection circuit characterized by equalization. 4. The impedance adjustment circuit comprises:
One signal source and the comparison voltage source are formed by third and fourth switches respectively connected to the other differential line of the differential circuit, and the third and fourth switches are always OFF and always ON, respectively. The clamp means is formed by the fifth and sixth switches, and supplies a constant voltage to the connection point thereof, and at least one switch is provided at each ON / OFF switching of the first and second switches.
4. The offset voltage detection circuit according to claim 3, wherein the fifth and sixth switches are turned on during a turn, and then controlled to be turned off. 5. An offset voltage detection circuit connecting one signal source and a comparison voltage source to a differential line of a differential circuit, wherein the one signal source and the comparison voltage source are respectively connected to one of the differential circuits. A first and a second switch connected to a differential line; and an impedance adjustment circuit that connects the one signal source and the comparison voltage source to one and the other differential lines of the differential circuit, respectively.
An offset voltage detection circuit, characterized in that the first and second switches are operated in an antithetical manner and the electrical characteristics of the differential lines through which signals to the differential circuit pass are made equal. 6. The third and fourth switches, wherein the impedance adjusting circuit connects both of the comparison voltage sources to the other differential line of the differential circuit, and operates in opposite directions to each other,
The offset voltage detection circuit according to claim 5, wherein the one signal source is formed of a fifth switch and a sixth switch which are respectively connected to one and the other differential lines of the differential circuit and are always turned off.