JP3403278B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] The present invention relates to a semiconductor device.Place ofManufacture
Regarding the method, more specifically, the contact resistance is small.
Semiconductor device with high and reliable wiring structurePlace ofManufacturing method
It is about the law. [0002] 2. Description of the Related Art In recent years, high integration and miniaturization of semiconductor devices have been realized.
Demands are increasing. Such high integration and fine
Due to the demand for thinning, wiring layers and electrode dimensions have been reduced,
Measures such as the structure are taken. Thus, the wiring layer,
As the dimensions of electrodes etc. are reduced, these electrical resistances
The resistance rises. Therefore, this electrode and wiring layer
Is required to have low resistance. In general, the electrical resistance in a semiconductor device
The main components that make up the
Contact resistance and wiring resistance
You. This diffusion resistance should increase the concentration of the impurity region.
Thereby, the resistance value can be reduced. Con
Tact resistance is determined by the state of the interface between the semiconductor substrate and the wiring layer.
To increase the effective contact area.
Therefore, the resistance value can be reduced. Wiring resistance
Therefore, the dimensions of the wiring layer are determined in advance by design.
Therefore, use of a material having a lower resistance has been studied. [0004] As described above, the electrical
Various measures have been taken to reduce electrical resistance.
You. Among them, especially for reducing the wiring resistance,
It has been traditional practice to use metal silicide as a part.
Has been done. As this metal silicide, high melting point metal
Is often used, and this refractory metal
By using silicide, low resistance and high heat resistance
Heat expansion with silicon or silicon oxide film
Various characteristics such as good consistency of tension coefficient
Will be done. A refractory metal silicide and a polycrystalline silicide
DRAM (Dynami) using stacked wiring with
c Random Access Memory) as a conventional semiconductor device
I will tell. FIG. 20 to FIG. 23 show the fabrication of a conventional semiconductor device.
It is an outline sectional view showing a fabrication method in order of a process. First, FIG.
For reference, a normal LO is placed on the surface of p-type silicon substrate 1.
Fee by COS (Local Oxidation of Silicon) method
An oxide film 2 is formed at a predetermined position. Also, with this
In both cases, p⁺Channel cut
Region 3 is formed. Thereafter, the field oxide film 2
The gate oxide film 5 and the conductive layer 6 on the substrate surface separated by
Is formed. This conductive layer 6 is formed by a usual photoengraving technique.
Patterning to desired shape by etching and etching technology
Thus, the gate electrode layer 6 is formed. Gate electrode layer 6
Ion implantation, etc., using the
As a result, p is sandwiched immediately below the gate electrode layer 6.
A pair of n-type source / drain on the surface of the silicon substrate 1
Region 4 is formed. The pair of n-type source / drain regions 4
, Gate oxide film 5 and gate electrode layer 6 to form a MOS
(Metal Oxide Semiconductor) Transistor 7 is composed
Is done. Referring to FIG. 21, this MOS transistor
An interlayer insulating layer 9 is formed so as to cover capacitor 7. This layer
A desired position is formed on the insulating layer 9 by a normal photoengraving technique.
A resist pattern 22 having a hole pattern is formed
Is done. Using this resist pattern 22 as a mask, C
F_Four, CHF_Three, C_FourF₈Carbon-based gas containing
Anisotropic etching is performed. This enables interlayer insulation
Partial surface of n-type source / drain region 4 penetrating layer 9
Hole 9a for bit line contact reaching
Is formed. Thereafter, the resist pattern 22 is removed.
It is. Referring to FIG. 22, contact hole 9a
Insulating layer so as to be in contact with n-type source / drain 4 through
9 on which polycrystalline silicon doped with impurities, for example,
(Hereinafter referred to as doped polysilicon) 10 and titanium
Silicide layers 11 are sequentially deposited. After this,
Doped polysilicon layer 10 and titanium silicide layer 11
However, by the usual photoengraving technology and etching technology,
A patterned bit line 12 having a desired shape is formed.
It is formed. Thereby, the doped polysilicon layer 10 is formed.
And a two-layer structure of titanium silicide layer 11
N-type source / drain region 4 through tact hole 9a
The bit line 12 electrically connected to the bit line 12 is formed. Referring to FIG. 23, this bit line 12 is covered.
The interlayer insulating layer 301 is formed on the interlayer insulating layer 9 as shown in FIG.
Is done. Normal photoengraving technology is used for the interlayer insulating layers 9 and 301.
N-type source / drain
A capacitor contact for reaching the partial surface of region 4
A contact hole 301a is formed. Through this contact hole 301a, n
Layer so as to be electrically connected to the source / drain region 4
Storage node (lower electrode) 3
02 is formed. On this storage node 302,
The cell plate is so covered as to cover the capacitor insulating layer 303.
A gate (upper electrode) 304 is formed. The storage node 302 and the capacitor
A capacitor is formed by the insulating layer 303 and the cell plate 304.
305 is constituted. An interlayer insulating layer covers the capacitor 305
306 is formed. On this interlayer insulating layer 306, desired
(Al) alloy wiring layer 307 having the following shape
Is formed. Thus, the MOS transistor 7 and
One transistor and one capacitor consisting of a capacitor 305
A DRAM memory cell having a data structure is completed. [0015] SUMMARY OF THE INVENTION Conventional semiconductor device manufacturing
In the fabrication method, the n-type source / drain region 4 and the bit line 1
2 has a problem of high contact resistance. Less than
The details will be described below. (1) Concrete caused by carbon-based deposits
Increase in tact resistance FIG. 21 shows a conventional method of manufacturing a semiconductor device.
Form contact holes 9a for bit lines by process
In this case, a carbon-based gas is used. others
The n-type source / dose exposed from the contact hole 9a.
On the surface of the rain region 4, an insulating carbon-based deposit is formed.
It is formed. FIG. 24 shows that a carbon-based deposit was formed.
FIG. 3 is a cross-sectional view showing a state where a bit line is formed in a state.
You. Referring to FIG. 24, the thus formed insulating
The carbon-based deposit 310 is H_TwoSO
_Four/ H_TwoO_TwoIt does not dissolve in cleaning solutions such as HF and HF. this
Therefore, when the bit line 12 is formed, the carbon-based deposit
310 denotes an n-type source / drain region 4 and a bit line 12
Will survive. Insulating carbs like this
The bit line 12 and the n-type
The contact resistance with the source / drain region 4 is large.
It becomes The bit line 12 and the gate electrode layer 6 are connected to each other.
Side of the contact hole to increase the print margin
A sidewall may be formed on the wall. in this case
First, as shown in FIG.
Silicon oxide film 35b is formed to cover the inner wall.
Thereafter, a carbon-based gas is applied to the silicon oxide film 35b.
The used anisotropic etching is performed. Referring to FIG.
The contact hole 9 is formed by the anisotropic etching.
Sidewall oxide film 35 remains so as to cover the side wall a. As described above, the side wall oxide film 35 shown in FIG.
If formed, a table of n-type source / drain regions 4
The carbon-based deposit is formed again on the surface (region S).
I will. Therefore, the n-type source / drain region 4 and the bit
Between the line 12 and each of the etches shown in FIGS.
Double carbon deposits formed during the
Will exist. Therefore, a sidewall oxide film 35 is formed.
If so, the n-type source / drain region 4 and the bit line
The contact resistance with 12 has become even greater
I will. (2) Condensation caused by aggregation of silicide
Increase in tact resistance The bit line 12 is ideally formed in the shape shown in FIG.
It is. However, the titanium silicide layer 11 is not
In the case of forming by the lettering method, a cap as shown in FIG.
The titanium silicide layer 11 is formed in the barrier. sand
That is, doped polysilicon in the contact hole 9a
Titanium silicide layer 1 on the side and bottom walls of layer 10
1 is formed so that its film thickness becomes thin. This chita
When the silicide layer 11 becomes thin, the heat resistance deteriorates.
If the heat treatment later causes aggregation as shown in FIG.
There is a case. Such agglomeration results in high resistance.
Therefore, the bit line 12 and the n-type source / drain region 4
The contact resistance becomes high. In view of the above (1) and (2), the present invention
Typically, semiconductor devices with low contact resistancePlace ofManufacturing method
Is to provide the law. [0022] Means for Solving the Problems The present inventionHalf ofManufacture of conductor equipment
The fabrication method includes the following steps. First, a conductive region is formed on the main surface of the semiconductor substrate.
Is done. And cover the conductive region on the main surface of the semiconductor substrate
Thus, an insulating layer is formed. And the insulating layer is made of carbon
Etching with gas to remove conductive areas from the upper surface of the insulating layer
Contact hole is formed to reach a part of the surface. So
Surface of the conductive region exposed from the contact hole
The carbon-based deposits attached to the surface are etched away,
A groove is formed on a part of the surface of the conductive region.And shape the groove
After the formation, nitrogen is injected into the groove surface.AndOf nitrogen
After injection,In contact with the conductive area through the contact hole,
And the conductive layer epitaxially grown at the bottom of the groove
It is formed. The present inventionHalf ofIn the method of manufacturing conductor devices, insulation
Conductive carbon-based deposits are removed and
Contact resistance with the electric layer is carbonsystemSediment remains
Can be lower than the case. The conductive layer is provided in a region in contact with the conductive region.
And growing epitaxially, the conductive region and conductive
The contact resistance with the layer can be further reduced. [0026]Also, Formed a groove in part of the surface of the conductive region
After that, a step of injecting nitrogen into the groove surface is further provided.
You. The conductive layer is formed after nitrogen implantation. Nitrogen is implanted into the conductive region on the trench surface.
Therefore, the conductive layer is easily grown epitaxially. others
The contact resistance between the conductive region and the conductive layer
Can be done. Further, by injecting nitrogen, the
Defects are introduced near the contact between the region and the conductive layer.
You. This defect becomes a gettering point for impurities.
The leakage current at the junction between the conductive region and the conductive layer.
It can be lower. [0029] [0030] [0031] [0032] [0033] [0034] [0035] [0036] [0037] [0038] [0039] [0040] [0041] [0042] [0043] [0044] [0045] [0046] [0047] [0048] [0049] [0050] BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described.
Will be explained. [0051]Embodiment 1 FIG. 1 shows a structure of a semiconductor device according to the first embodiment of the present invention.
It is sectional drawing which shows a structure schematically. FIG. 2 is a view similar to FIG.
Enlarged contact between source / drain region and bit line
FIG. Referring mainly to FIG. 1, p-type silicon substrate 1
The surface has a field to electrically isolate each area.
Oxide film 2 is formed. Also this field oxidation
Immediately below the membrane 2 is p⁺Channel cut region 3 is formed
I have. The p-type silicon substrate 1 thus separated
Is formed with a MOS transistor 7 on the surface thereof. This
MOS transistor 7 has a pair of n-type source / drain
Region 4, a gate oxide film 5, and a gate electrode layer 6.
are doing. The pair of n-type source / drain regions 4 are p-type
Formed at a predetermined distance on the surface of the silicon substrate 1
I have. The gate electrode layer 6 has a pair of n-type source / drain
A gate oxide film 5 is interposed on a region sandwiched between
It is formed. A layer covering MOS transistor 7
An interlayer insulating layer 9 is formed. The interlayer insulating layer 9 has an n-type
Contact hole 9a reaching source / drain region 4
Is provided. Immediately below this contact hole 9a
A trench 8 is formed in the n-type source / drain region 4 in FIG.
ing. Through the contact hole 9a, an n-type saw
On the interlayer insulating layer 9 so as to be in contact with the source / drain region 4.
Has a bit line 12 formed therein. This bit line 12
Are doped polysilicon layer 10 and titanium silicide layer
11 has a two-layer structure. Referring mainly to FIG.
The recon layer 10 is formed on the side and bottom of the groove 8 by n-type silicon.
Contact with the source / drain region 4 and at the bottom of the groove 8
Has a portion 10a that has been epitaxially grown.
You. The doped polysilicon layer 10 is located at the bottom of the groove 8.
Is actually doped
Between polysilicon layer 10 and n-type source / drain region 4
The interface is in an unknown state. The doped polysilicon layer 10 and the n-type
Near the contact portion with the source / drain region 4,
Depression 21 exists. Next, the semiconductor device according to the present embodiment will be described.
The manufacturing method will be described. 3 to 6 show examples of the present invention.
A method for manufacturing a semiconductor device according to the first embodiment is shown in the order of steps.
FIG. First, referring to FIG.
On the surface of the substrate 1 by the usual LOCOS method.
A second oxide film 2 is formed. In addition, the fee
P just below the oxide film 2⁺Channel cut area 3 is formed
Is done. This field oxide film 2 and p⁺Channel
P-type silicon electrically separated by a cut region 3
A gate oxide film 5 is formed on the surface of the substrate 1 by a thermal oxidation method.
Is done. On this gate oxide film 5, a conductive layer 6 is formed.
It is. The conductive layer 6 is formed by a usual photoengraving technique and etching.
Patterning into a desired shape by
It becomes the gate electrode layer 6. The gate electrode layer 6, the field
Ion implantation or the like is performed using the oxide film 2 or the like as a mask.
As a result, the region 1 immediately below the gate electrode 6 is sandwiched.
A pair of n-type source / drain regions 4 are formed. The pair of n-type source / drain regions 4 and
MOS transistor is formed by gate oxide film 5 and gate electrode layer 6.
The register 7 is configured. Referring to FIG. 4, MOS transistor 7 is
Interlayer insulating layer made of, for example, a silicon oxide film to cover
9 is formed. On this interlayer insulating layer 9, a normal photo
The plate technology has a hole pattern at a predetermined position.
A distant pattern 22 is formed. This resist putter
CF using the mask 22 as a mask_Four, CHF_Three, C_FourF₈What
Anisotropic etching on interlayer insulating layer 9 with carbon-based gas containing
Is performed. With this etching, the n-type source
Hole reaching a part of the surface of the drain / drain region 4
9 a is formed on the interlayer insulating layer 9. After this, the resist
Turn 22 is removed. Incidentally, when the contact hole 9a is formed,
Exposed from contact hole 9a by etching
An insulating carbohydrate is provided on the surface of the n-type source / drain region 4.
Deposit 4 adheres. Referring to FIG. 5, for example, CF_Four+ O_Twoof
N-type source / drain by anisotropic plasma etching
To remove carbon-based deposits attached to the surface of the
And the surface of n-type source / drain region 4 is etched.
You. Thus, immediately below the contact hole 9a,
Groove 8 is formed in the surface of n-type source / drain region 4.
You. After this, H_TwoSO_Four/ H_TwoO_TwoOr HF solution
Cleaning process is performed. Referring to FIG. 6, contact hole 9a is formed.
Through the interlayer so as to be in contact with the n-type source / drain region 4
Polysilicon or amorphous silicon on insulating layer 9
A conductive layer 10b made of a conductive material is formed. This conductive layer 10
b is deposited by CVD (Chemical Vapor Deposition)
If the process is performed in an optimized atmosphere and temperature,
The groove of the conductive layer 10 is formed by the heat treatment at the time of
Epitaxial growth of the part located at the bottom of
Can be. Before the formation of the conductive layer 10b, nitrogen is added.
If implanted into the surface of n-type source / drain region 4,
Pitaxial growth is promoted. When injecting this nitrogen
Then, a defect is found near the trench 8 of the n-type source / drain region 4.
Is entered. Thereafter, a titanium silicide is formed on the conductive layer 10b.
After depositing the nitride layer 11, the conductive layer 10b is
Photolithography technology and etching technology with the reside layer 11
The semiconductor shown in FIG. 1 is patterned by
The device is completed. Further, the process will be described with reference to FIG.
Through these steps, the DRAM memory cells are completed.
To achieve. In the method of manufacturing a semiconductor device according to the present embodiment,
Is the n-type source / drain region 4 in the process shown in FIG.
The insulating carbon-based deposits attached to the surface of the
You. For this reason, in the process of FIG.
Even if formed, conductive layer 10b and n-type source / drain
Insulating carbon-based deposits remain between the
Not in. Therefore, the bit line 12 shown in FIG.
The contact resistance with the source / drain region 4 is reduced. Further, in the process shown in FIG.
Is to be grown epitaxially at the bottom of the trench 8
It is formed. Therefore, in FIG. 1, the n-type source /
The contact resistance between the drain region 4 and the bit line 12 is
It can be further reduced. In the process shown in FIG.
0b before forming the n-type source / drain regions 4
Nitrogen is injected into the surface. When nitrogen is implanted, the conductive layer 1
0b facilitates epitaxial growth at the bottom of the groove 8
Become. Therefore, the n-type source / drain regions shown in FIG.
4 and the bit line 12 have a further reduced contact resistance.
Can be Further, by implanting nitrogen, FIG.
The n-type source / drain region 4 and the bit line 1
Defect 21 is introduced near the contact portion with
Become. This defect 21 has a gettering point of the impurity.
Become. Therefore, the n-type source / drain region 4 and the bit
Low leakage current at the junction with line 12
it can. [0072]Embodiment 2 FIG. 7 shows a structure of a semiconductor device according to the second embodiment of the present invention.
It is sectional drawing which shows a structure schematically. Referring to FIG.
The configuration of the semiconductor device of the present embodiment is different from that of the first embodiment.
The sidewall oxide film35Is different. Sidewall acid
Chemical film35Is to cover the side wall of the contact hole 9a.
Is formed. The trench 38 is formed by the sidewall oxide film.35By
Aperture specified35aIt is located directly below. For other configurations, the first embodiment
Is the same as
Numbers are attached and their explanation is omitted. Next, the semiconductor device according to the present embodiment will be described.
The manufacturing method will be described. FIG. 8 shows an embodiment of the present invention.
FIG. 9 is a process chart showing a method for manufacturing a semiconductor device in state 2;
You. First, the manufacturing method according to the present embodiment is shown in FIGS.
The same steps as in the first embodiment are performed. Then, as shown in FIG.
After the distaste pattern 22 is removed, FIGS.
The same steps as in the conventional example shown are performed. And the layers shown in FIG.
Insulation layer 9 and sidewall oxide film35And CF as a mask_Four+
O_TwoIs performed. to this
The opening as shown in FIG.35aThe groove 38 is formed just below
Is done. The subsequent steps are substantially the same as in the first embodiment.
Therefore, the description is omitted. In the present embodiment,
The same effect as that described in the first embodiment can be obtained.
You. In addition, the side of the contact hole 9a
Wall oxide film35Provided, the bit line 12 and the gate
The short margin with the gate electrode layer 6 is increased. this
Contact hole due to mask overlay error
Even if the position of 9a is shifted, the bit line 12 and the gate
A short circuit with the pole layer 6 is prevented. [0077]Embodiment 3 FIG. 9 shows a structure of a semiconductor device according to the third embodiment of the present invention.
It is sectional drawing which shows a structure schematically. Referring to FIG.
The configuration of the semiconductor device according to the present embodiment corresponds to the configuration shown in FIG.
Compared to the conventional configuration, the titanium silicon
It differs in the configuration of the side layer. Titanium silicide layer 3
1 is on the interlayer insulating layer 9 of the doped polysilicon layer 30
It is formed only on the extending part. FIG. 22 shows another structure.
It is almost the same as the conventional example.
The same reference numerals are given and the description is omitted. Next, the semiconductor device according to the present embodiment will be described.
The manufacturing method will be described. Manufacturing method of the present embodiment
First, the same steps as those of the first embodiment shown in FIGS.
Go through. Then, the resist pattern 22 shown in FIG. 4 is removed.
After that, the same steps as in Embodiment 1 shown in FIG.
The conductive layer 10b is formed. After that, sputtering at high pressure
Or shorten the distance between the target and the substrate.
And vertical incident component by sputtering method
By cutting, a titanium silicide layer 31 is formed. H
The tan silicide layer 31 has a vertical incidence
Since the part is cut off, the conductivity in the contact hole 9a is reduced.
The conductive layer 10b is not formed on the side wall and the bottom wall of the layer 10b.
Formed only on the portion extending on interlayer insulating layer 9 of
You. Thereafter, ordinary photoengraving techniques and etching
The titanium silicide layer 3 and the conductive layer 30 are
Are patterned to complete the semiconductor device shown in FIG.
You. In this embodiment, the titanium silicide layer 3
1 extends over the interlayer insulating layer 9 of the doped polysilicon layer 30
It is formed only on the existing part. In other words, titanium
The reside layer 31 is formed by a doped layer in the contact hole 9a.
Formed on the side and bottom walls of the polysilicon layer 30
Absent. Therefore, in the contact hole 9a,
The thickness of the silicide layer 31 is not reduced.
No. Therefore, the titanium silicide layer 31 is subjected to a heat treatment in a later process.
Agglomeration is prevented by the
Contact resistance between line 32 and n-type source / drain region 4
An increase in drag is prevented. The doped polysilicon layer 30 has an n-type
In the portion in contact with the source / drain region 4, the above-described actual
As in the first embodiment, the doped polysilicon layer 30
Tax growth may be performed. [0084]Embodiment 4 FIG. 10 shows a semiconductor device according to the fourth embodiment of the present invention.
It is sectional drawing which shows a structure schematically. Referring to FIG.
The structure of the semiconductor device in this embodiment is shown in FIG.
The shape of the contact hole is different from that in the third embodiment.
Become. The contact hole 49a is located above the interlayer insulating layer 9.
The opening diameter increases from the surface toward the p-type silicon substrate 1 side.
Shape, that is, a reverse tapered shape.
Has been established. The contact hole 49a has an inverted tapered shape.
To do this, rotate the board diagonally or etch
For example, there is a method such as increasing the pressure of the printing. In the present embodiment, contact hole 49
Since a is formed in a so-called reverse tapered shape,
Doped polysilicon in contact hole 49a
The titanium silicide layer 41 is formed on the side wall and the bottom wall of the layer 40.
Nothing is done. Therefore, the contact hole 49
The thickness of the titanium silicide layer 41 is formed thin within a
It will not be done. Therefore, the titanium silicide layer 41
Aggregation is prevented by the heat treatment in the post-process,
Therefore, the bit line 42 and the n-type source / drain region 4
An increase in contact resistance is also prevented. The features of Embodiment 1 and Embodiment 3
Configuration or embodiment shown in FIG.
FIG. 12 shows a combination of the features of Embodiment 2 and Embodiment 3.
The configuration further reduces contact resistance
Semiconductor device can be obtained. FIG. 13 and FIG.
14, the configuration of the first embodiment shown in FIG.
Each of the configurations shown in the second embodiment shown in FIG.
A configuration in which the pure material regions 54 and 64 are added may be adopted. this
The n-type impurity regions 54 and 64 have n-type source / drain regions.
A region overlapping with region 4, and an n-type source / drain
It extends to a position deeper than the region 4. In addition, this n-type
The pure region removes impurities from the doped polysilicon layer 30.
By diffusion or by forming bit lines 12
Before ion implantation. Normally, impurity of n-type source / drain region 4
The substance concentration is higher as it is closer to the substrate surface. So, for example,
When the grooves 8 and 38 are provided as shown in FIGS. 1 and 7,
N-type source / drain regions near the bottom surfaces of trenches 8 and 38
There is a possibility that the impurity concentration in the region 4 becomes low. in this way
Near the bottom surfaces of the grooves 8, 38, that is, n-type source / drain
Low impurity concentration near the interface between region 4 and bit line 12
Then, the contact resistance increases. Here, it is necessary to add impurity regions 54 and 64.
As a result, the n-type source / drain region 4 and the bit line
To increase the impurity concentration near the interface with
it can. Thereby, the n-type source / drain region 4 and the via
The contact resistance with the cut line 12 and the source /
The increase in the diffusion resistance of the drain region will be suppressed.
You. [0090]Embodiment 5 FIG. 15 shows a semiconductor device according to the fifth embodiment of the present invention.
It is sectional drawing which shows a structure schematically. Referring to FIG.
The structure of the semiconductor device in this embodiment is shown in FIG.
And n-type impurity region surrounding the trench
The difference is that the region is formed deeply. Groove 78
Is the inner diameter W of the groove 78_FiveDepth D than_FiveIs bigger
It is formed so that. The n-type impurity region 74 is
having a portion overlapping with the n-type source / drain region 4;
The groove 78 is formed along the side wall. The other points are the same as those shown in FIG.
Is the same as
Numbers are attached and their explanation is omitted. Next, the semiconductor device according to the present embodiment will be described.
The manufacturing method will be described. FIG. 16 shows an embodiment of the present invention.
FIG. 32 is a process chart showing the method for manufacturing the semiconductor device in the fifth embodiment.
You. First, the manufacturing method of the present embodiment is shown in FIGS.
The same steps as in the first embodiment are performed. And in FIG.
25 and 26 after the resist pattern 22 is removed.
The sidewall oxide film 35 is formed by the process shown in FIG. And
In the state shown in FIG._Four+ O_TwoAnisotropic plastic
As shown in FIG.
Groove 78 penetrates n-type source / drain region 4 as shown in FIG.
It is formed as follows. Thereafter, the doped polysilicon layer 10 and the
A bit line 12 made of a tan silicide layer 11 is formed.
Thus, the semiconductor device shown in FIG. 15 is completed. Note that the n-type impurity region 74 is
Diffusing impurities from the silicon layer 10;
Performs ion implantation or the like before the bit line 12 is formed.
Formed. In this embodiment, the groove 78 has an inner diameter W
_FiveMore depth D_FiveIs larger. Thus, the groove 78 is deep
The n-type source / drain regions 4
And n-type impurity region 74 is in contact with bit line 12
The area increases. Therefore, the n-type source / drain regions 4
And the contact resistance with the bit line 12 is further reduced.
can do. Further, as shown in FIG.
Layer 31 is an interlayer insulating layer of doped polysilicon layer 30.
9 may be formed only in the portion extending above. Bit
By configuring the line 32 in this manner,
As described above, the titanium silicide layer 3
1 can be prevented from agglomeration and the contact
Resistance can be suppressed from increasing. [0097]Embodiment 6 FIG. 18 shows a semiconductor device according to the sixth embodiment of the present invention.
It is sectional drawing which shows a structure schematically. Referring to FIG.
The structure of the semiconductor device in this embodiment is shown in FIG.
The shape of the groove is different from that of the configuration. Groove 88 is isotropic
Formed by the reactive etching, the side wall oxide film 35
It has a shape that goes around to the lower region. This groove 88
The dimension that goes under the side wall oxide film 35 is the depth of the groove 88.
It is almost the same as The other configuration is almost the same as the configuration shown in FIG.
Therefore, the same reference numerals are used for the same members.
And description thereof is omitted. Next, the semiconductor device according to the present embodiment will be described.
The manufacturing method will be described. FIG. 19 shows an embodiment of the present invention.
FIG. 29 is a process chart showing the method for manufacturing the semiconductor device in the sixth embodiment.
You. Referring to FIG. 19, first, the same as in the fifth embodiment,
Through the steps, sidewall oxide film 35 is formed. After this,
N-type saw exposed from sidewall oxide film 35 and interlayer insulating layer 9
CF on the surface of the drain / drain region 4_Four+ O_TwoIsotropic
Plasma etching is performed. This allows for insulation
The carbon-based deposit is removed, and the sidewall insulating layer 3 is removed.
5, a groove 88 having a shape extending to the lower side is formed.
It is. Thereafter, the doped polysilicon layer 10 and the titanium
And a bit line 12 composed of a silicide layer 11 is formed.
Then, the semiconductor device shown in FIG. 18 is completed. Note that the n-type impurity region 84 is
Diffusing impurities from the silicon layer 10;
Is performed before the bit line 12 is formed.
It is formed by being done. In this embodiment, isotropic etching is used.
By forming the groove 88, the groove 88 becomes anisotropic edge.
Wider than in the case of forming by
Shape. As much as the groove is expanded in the horizontal direction, the bit
Line 12 is n-type source / drain region 4 and n-type impurity
The area in contact with the region 84 increases. Therefore, the n-type saw
Contact between the source / drain region 4 and the bit line 12
Resistance can be further reduced. The above implementation
In the embodiment, the titanium silicide layers 11 and 31 are
A silicide layer, especially a high melting point metal silicide.
Layer is preferred. [0102] The embodiment disclosed this time is in all respects.
It should be considered as illustrative and not restrictive
is there. The scope of the present invention is not described above, but is defined by the claims.
, And the meaning equivalent to the scope of the claims.
And is intended to include all changes within the scope.
You.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is an enlarged schematic cross-sectional view showing a contact portion between a source / drain region and a bit line in FIG. 1; FIG. 3 is a schematic cross-sectional view showing a first step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 4 is a schematic sectional view showing a second step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a schematic cross-sectional view showing a third step of the method for manufacturing a semiconductor device in the first embodiment of the present invention. FIG. 6 is a schematic sectional view showing a fourth step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention; FIG. 7 is a sectional view schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention; FIG. 8 is a process chart illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. FIG. 9 is a cross sectional view schematically showing a configuration of a semiconductor device according to a third embodiment of the present invention. FIG. 10 is a cross sectional view schematically showing a configuration of a semiconductor device according to a fourth embodiment of the present invention. FIG. 11 is a cross sectional view schematically showing a configuration of a semiconductor device in which features of the first and third embodiments of the present invention are combined. FIG. 12 is a cross sectional view schematically showing a configuration of a semiconductor device in which features of the second and third embodiments of the present invention are combined. FIG. 13 is a schematic sectional view showing a state where an n-type impurity region is added to the semiconductor device according to the first embodiment of the present invention; FIG. 14 is a schematic sectional view showing a state where an n-type impurity region is added to the semiconductor device according to the second embodiment of the present invention; FIG. 15 is a cross sectional view schematically showing a configuration of a semiconductor device according to a fifth embodiment of the present invention. FIG. 16 is a process chart showing a method for manufacturing a semiconductor device in a fifth embodiment of the present invention. FIG. 17 is a cross sectional view schematically showing a configuration of a semiconductor device in which features of Embodiments 3 and 5 of the present invention are combined. FIG. 18 is a cross sectional view schematically showing a configuration of a semiconductor device according to a sixth embodiment of the present invention. FIG. 19 is a process chart illustrating a method for manufacturing a semiconductor device in a sixth embodiment of the present invention. FIG. 20 is a schematic cross-sectional view showing a first step of a conventional method for manufacturing a semiconductor device. FIG. 21 is a schematic cross-sectional view showing a second step of the conventional method for manufacturing a semiconductor device. FIG. 22 is a schematic cross-sectional view showing a third step of the conventional method of manufacturing a semiconductor device. FIG. 23 is a schematic cross-sectional view showing a fourth step of the conventional method for manufacturing a semiconductor device. FIG. 24 is a schematic sectional view showing a state where an insulating carbon-based deposit is formed between a source / drain region and a bit line. FIG. 25 is a first process chart showing a method of forming a sidewall oxide film. FIG. 26 is a second process diagram illustrating a method of forming a sidewall oxide film. FIG. 27 is a schematic sectional view for explaining coverage when a titanium silicide layer is formed by a sputtering method. FIG. 28 is a schematic cross-sectional view showing a state in which a titanium silicide layer has aggregated. [Description of Signs] 1 p-type silicon substrate, 4 n-type source / drain regions, 8, 78, 88 grooves, 9 interlayer insulating layers, 9 a, 49
a contact hole, 10,30 doped polysilicon layer, 11,31 titanium silicide layer, 12,32
Bit line, 35 sidewall oxide film, 54, 64, 74, 84
n-type impurity region.

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/768 H01L 21/28 H01L 21/3205 H01L 21/321 H01L 21/3213

Claims (1)

(57) Claims 1. A step of forming a conductive region on a main surface of a semiconductor substrate, and a step of forming an insulating layer on the main surface of the semiconductor substrate so as to cover the conductive region. Etching the insulating layer with a carbon-based gas to form a contact hole extending from an upper surface of the insulating layer to a partial surface of the conductive region; and a partial surface of the conductive region exposed from the contact hole. Forming a groove on a partial surface of the conductive region by etching and removing a carbon-based deposit attached to the substrate ; and implanting nitrogen into the groove surface after forming the groove.
If, after injection of the nitrogen, the contact in contact with said conductive region via hole, and comprising a step of forming a conductive layer epitaxially grown at the bottom of the groove, a method of manufacturing a semiconductor device.