JP3403117B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a high breakdown voltage MOS transistor structure and a technique for improving the method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 7 is a sectional view for explaining the basic structure of a conventional semiconductor device.

Reference numeral 51 is a semiconductor substrate of one conductivity type, for example, P type, on which an element isolation film (not shown) and first and second gate insulating films 52 and 53 are formed, and 54 is From the first gate insulating film 52 to the second gate insulating film 5
3 is a gate electrode formed by patterning so as to extend over a part of 3. Further, 55 is a low concentration source / drain region, 56 is a high concentration source / drain region, and LD
It has a D (Lightly Doped Drain) structure. For convenience, only the drain region side is shown. Further, 57 is a source / drain electrode which is contact-connected to the source / drain region 56.

[0004]

Here, the inventor of the present invention has found the location of the electric field concentration at each voltage Vgs in the semiconductor device by device simulation. As a result, it was found that different breakdown voltage characteristics were exhibited depending on the setting situation of the concentration distribution of the low concentration source / drain regions 55. That is, as shown in FIGS. 8A and 8B, when the surface concentration of the source / drain region 55 is lower (for example, about 5 × 10 ¹⁶ / cm ³ ), the substrate current Is
ub has two peaks (do) as the voltage Vgs increases.
uble hump structure) (see FIG. 8 (a)). 8A is a characteristic diagram (Vds = 60 V) showing the substrate current Isub with respect to the voltage Vgs at the above concentration.
(B) is a characteristic diagram showing the current Ids with respect to the voltage Vds.

First, the first peak (1) of the substrate current Isub shown in FIG. 8A occurs when an electric field is generated from the drain region 55 toward the gate electrode 54 when the voltage Vgs <the voltage Vds. The electric field concentration area is shown in Fig. 7.
It is the first region (1) shown in FIG.

When voltage Vgs = voltage Vds, the potential difference between drain region 55 and gate electrode 54 disappears, and substrate current Isub becomes minimum.

Further, when the voltage Vgs> the voltage Vds, the first induction shown in FIG. 7 is caused by the induction of carriers by the voltage Vgs.
The resistance of the region (1) becomes smaller, the voltage applied to the depletion layer in the second region (2) shown in FIG. 7 becomes larger due to the resistance division, and the electric field of the second region (2) shown in FIG. Will be dominant. Therefore, at this time, the substrate current Isub again rises and reaches the second peak (2) of the substrate current Isub shown in FIG.

When the concentration distribution of the low-concentration source / drain region 55 is lower, the first peak (1) of the substrate current Isub is low and the drain breakdown voltage in the region where the voltage Vgs is low is low. Effective, but substrate current I
Since the second peak (2) of sub becomes relatively high, there is a problem that the breakdown voltage does not exist in the region where the voltage Vgs is high.

The surface concentration of the source / drain region 55 is relatively high (eg, 1 × 10 ¹⁷ / cm 2).
³ )), the substrate current Isub has one peak with a certain voltage Vgs as a peak as shown in FIG. 9A, but the drain withstand voltage does not exist in a region where the voltage Vgs is low. was there. 9A is a characteristic diagram (Vds = 60V) showing the substrate current Isub with respect to the voltage Vgs at the above concentration, and FIG. 9B is a characteristic diagram showing the current Ids with respect to the voltage Vds. When the low-concentration source / drain region 55 has a lower concentration as described above, the low-concentration source does not have a withstand voltage in a region where the voltage Vgs is high (see region (I) in FIG. 8B). When the drain region 55 has a relatively high concentration, it has no withstand voltage in the region where the voltage Vgs is low (FIG. 9).
Area (II) in (b)).

Therefore, it is an object of the present invention to provide a semiconductor device and a manufacturing method thereof for optimizing the concentration distribution of a low concentration source / drain region corresponding to the electric field concentration location at each of the above voltages Vgs. .

[0011]

Therefore, in the semiconductor device of the present invention, as shown in FIG. 6, the gate oxide film 10 formed on the semiconductor substrate 1 and a film thickness thicker than the gate oxide film 10 are selected. An oxide film 9, a gate electrode 11 formed on the gate oxide film 10 and partially over the selective oxide film 9, and formed on the surface layer of the substrate so as to be adjacent to the gate electrode 11. Low concentration source / drain regions 13, 14 and high concentration source / drain regions 15,
16 of the first impurity region 1 in which the low-concentration source / drain regions 13 and 14 are formed at the substrate surface layer position receding from the end of the selective oxide film 9.
3A and 14A, the gate oxide film 10 and the selective oxide film 9
The second impurity regions 13B and 14B are formed so as to be adjacent to each other in the vicinity of the boundary line between and and have a lower concentration than the first impurity regions 13A and 14A.

As shown in FIG. 1, the manufacturing method is as follows. As shown in FIG. 1, the first resist film 3 is used as a mask to ion-implant the first impurities into the surface layer of the semiconductor substrate, and as shown in FIG. The second impurity is ion-implanted and diffused into the surface layer of the substrate using 5 as a mask. Next, as shown in FIG. 3, the surface of the substrate is thermally oxidized by using the silicon nitride film 8 having the opening formed on the substrate 1 as a mask to form a selective oxide film 9 on the substrate 1, and then, as shown in FIG. As shown in FIG. 3, the gate oxide film 1 is formed on the substrate region other than the selective oxide film 9 by thermally oxidizing the substrate surface.
Form 0. Then, after forming a conductive film on the entire surface,
This conductive film is patterned so that the gate electrode 11 extends from the gate oxide film 10 to a part of the selective oxide film 9.
To form. Further, the selective oxide film 9 and the gate electrode 1
After the third impurity is ion-implanted into the surface layer of the substrate by using 1 as a mask, the first, second and third impurities ion-implanted into the surface layer of the substrate are annealed as shown in FIG. The low concentration source / drain regions 13A, 14A and 13B, 14B having the first and second impurity concentration distributions and the high concentration source / drain regions 15, 16 having the third impurity concentration distribution are diffused. And a step of forming.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.

In FIG. 6, reference numeral 1 is a semiconductor substrate of one conductivity type, for example, P type (concentration: about 3 × 10 ¹⁴ / cm ³ ), and an element isolation film (selective oxide film, not shown) is formed on the substrate 1. 9) and a gate oxide film 10 are formed, and 11 is a gate electrode patterned on the gate oxide film 10. Further, 13 and 14 are low-concentration source / drain regions, and 15 and 16 are high-concentration source / drain regions, which constitute a semiconductor device (MOS transistor) having an LDD (Lightly Doped Drain) structure.

The feature of the present invention is that the low-concentration source / drain regions 13 and 14 are formed in first substrate impurity regions 13A and 14A formed at the substrate surface layer positions receding from the end portions of the selective oxide film 9. And second impurity regions 13B and 14B which are formed so as to be adjacent to the boundary between the gate oxide film 10 and the selective oxide film 9 and have a lower concentration than the first impurity regions 13A and 14A. By being configured, since the low-concentration source / drain regions are formed corresponding to the electric field concentration locations at each voltage Vgs, various withstand voltages can be supported. That is, the first region (1) of the prior art (FIG. 7) is formed by the low concentration second impurity regions 13B and 14B (surface concentration: about 5 × 10 ¹⁶ / cm ³ ), and low Vg
s withstand voltage and the second region (2) has a lower concentration of the first impurity region 1 than the second impurity regions 13B and 14B.
3A, 14A (surface concentration: approximately 1 × 10 ¹⁷ / cm ³ )
And formed to have a high Vgs breakdown voltage.

Furthermore, the first impurity regions 13A, 1
The diffusion depth Xj of 4A is about 1.5 μm, and
The diffusion depth Xj of the impurity regions 13B and 14B of the second impurity region 13B is set to about 0.5 μm.
A surface relaxation type (resurf) structure of B and 14B can be realized, and high withstand voltage characteristics can be provided. Such a resurf technique is disclosed in Japanese Patent Laid-Open No. 9-139438.

A method of manufacturing the above semiconductor device will be described below.

First, referring to FIG. 1, the substrate 1 (concentration:
After the dummy oxide film 2 is formed on about 3 × 10 ¹⁴ / cm ³ , the first resist film (first impurity region 13) is formed.
A first impurity (for example, phosphorus ions or arsenic ions may be used) is ion-implanted using A. 3 (for forming A and 14A) 3 as a mask to form the first ion-implanted layer 4. In this step, for example, phosphorus ions are ion-implanted at an acceleration voltage of about 100 KeV and an implantation amount of 5 × 10 ¹² / cm ² .

Further, as shown in FIG. 2, the second resist film 5 (for forming the second impurity regions 13B and 14B) is used as a mask to form a second impurity (for example, arsenic ion, etc.) on the surface layer of the substrate.
Phosphorus ion may also be used. 2) is ion-implanted to form the second ion-implanted layer 6. In this step, for example, arsenic ions are accelerated to an acceleration voltage of about 160 KeV and 2 × 10 ¹² / cm 2.
Ion implantation is performed with a dose of ² .

Next, as shown in FIG. 3, the surface of the substrate is thermally oxidized by using the silicon nitride film 8 having an opening formed on the pad oxide film 7 on the substrate 1 as a mask to selectively oxidize the substrate 1. The film 9 and the element isolation film are formed. Before the heat treatment, a diffusion process for forming a low concentration layer is performed, and the first and second ion implantation layers 4 and 6 are diffused in the substrate to
And second ion implantation layers 4A and 6A (low-concentration source / drain regions 13 and 14 described later).

Further, as shown in FIG. 4, the gate oxide film 1 is formed on the substrate region other than the selective oxide film 9 by thermally oxidizing the substrate surface.
Form 0. Subsequently, after forming a conductive film (for example, a phosphorus-doped polysilicon film or a laminated film including the polysilicon film and a tungsten silicide film) on the entire surface, the conductive film is patterned to form the gate oxide film 10. A gate electrode 11 is formed so as to extend over part of the selective oxide film 9. Further, using the selective oxide film 9 and the gate electrode 11 as a mask, a third impurity (for example, arsenic ion or phosphorus ion may be used) is ion-implanted into the surface layer of the substrate to form a third ion-implanted layer 12. In this step, for example, arsenic ions are ion-implanted at an acceleration voltage of about 80 KeV and an implantation amount of 6 × 10 ¹⁵ / cm ² .

Thereafter, as shown in FIG. 5, an annealing process is performed to perform the ion implantation on the surface layer of the substrate.
Low-concentration source / drain regions 13 having the first and second impurity concentration distributions by diffusing the second and third impurities
A, 14A (surface concentration: about 1 × 10 ¹⁷ cm ³ ) and 13B, 14B (surface concentration: about 5 × 10 ¹⁶ / c)
m ³ ) and the high-concentration source / drain regions 15 and 16 (concentration: about 5 × 10 ²⁰ ) having the third impurity concentration distribution.
/ Cm ³ ).

Then, as shown in FIG. 6, source / drain electrodes 17 and 18 contacting the high-concentration source / drain regions 15 and 16 are formed through an interlayer insulating film (not shown) formed on the entire surface to form semiconductors. The device is completed.

As described above, in the present invention, each voltage V
A low concentration source corresponding to the location where the electric field is concentrated.
By forming the drain regions 13 and 14, it is possible to cope with various breakdown voltages. The breakdown voltage, which was about 80 V in the conventional configuration, could be increased to about 95 V in the configuration of the present invention.

In the description of this embodiment, an N-channel MOS is formed on the P-type semiconductor layer (substrate or well region).
An example of forming a transistor has been introduced, but the same applies to the case of forming a P-channel MOS transistor on an N-type semiconductor layer (substrate or well region) substrate.

Further, in the description of this embodiment, the gate electrode 1 is formed on both sides of the source / drain region with the selective oxide film 9 interposed therebetween.
1 is formed, but one side (for example, the drain region side)
Alternatively, the gate electrode 11 may be formed only through the selective oxide film 9.

[0027]

According to the present invention, since the low-concentration source / drain regions are composed of the first impurity region and the second impurity region corresponding to the electric field concentration location at each voltage Vgs, various breakdown voltages can be obtained. Can handle. Furthermore, by adopting it in the resurf structure, it is possible to further increase the breakdown voltage.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device of the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device of the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the method for manufacturing the semiconductor device of the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the method for manufacturing the semiconductor device of the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device of the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a conventional semiconductor device.

FIG. 8 is a diagram for explaining a conventional problem.

FIG. 9 is a diagram for explaining a conventional problem.

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (3)

(57) [Claims] 1. A first resist film is formed on the surface of a semiconductor substrate.
And a step of ion-implanting the first impurity with the mask, and using the second resist film as a mask to form a second impurity on the surface layer of the substrate.
This is done after the step of ion-implanting the material and after forming the oxidation resistant film having openings on the substrate.
The surface of the substrate is thermally oxidized using the oxidation resistant film of
A step of forming a selective oxide film on the substrate surface, and thermally oxidizing the substrate surface to form a substrate area other than the selective oxide film.
Step of forming a gate oxide film, and patterning this conductive film after forming a conductive film on the entire surface
And extends from the gate oxide film to a part of the selective oxide film.
Forming the gate electrode, and using the selective oxide film and the gate electrode as a mask, the substrate surface layer
Ion implantation of a third impurity into the substrate , and by performing an annealing treatment, the surface of the substrate is ion-implanted.
The first, second and third impurities which have been
Low concentration source having first and second impurity concentration distributions
.High concentration having a drain region and a third impurity concentration distribution
A source / drain region, and
A method for manufacturing a semiconductor device, comprising: 2. The low-concentration source / drain regions are
A shape is formed at the substrate surface position receding from the end of the second insulating film.
The formed first impurity region, the first insulating film, and the second
Is formed so as to be adjacent to the boundary with the insulating film of
A second impurity region having a concentration lower than that of the first impurity region and
2. The method according to claim 1, wherein
Manufacturing method of semiconductor device. 3. The front formed under the second insulating film
The second impurity region is shallower than the first impurity region.
1. The contract or the contract as claimed in claim 1, wherein
The method for manufacturing a semiconductor device according to claim 2.