JP3400082B2 - Liquid crystal display - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly to a technique which is effective when used in a TFT (thin film transistor) active matrix type liquid crystal display panel. It is. 2. Description of the Related Art A color liquid crystal display device having an active matrix structure with a TFT mounted thereon is described in, for example, Nikkei McGraw-Hill Company, “Nikkei Electronics”, page 211, September 10, 1984. TFT liquid crystal display devices
As a small and low power consumption display device, it is mainly used for a monitor or the like in a microcomputer system, but there is a strong demand for multi-gradation and multi-color display as a display device in office automation equipment. As such a driver for multi-color display,
Some use a CMOS switch that outputs a gray scale voltage. An example of such a driver is “Hitachi LCD Driver Data Book” published in March 1990 by Hitachi, Ltd. [0003] In a TFT active matrix type liquid crystal display device, a horizontal smear phenomenon occurs when a window pattern is displayed. For this reason, in the conventional liquid crystal display device, in order to stabilize the potential of the common electrode, measures are taken to reduce the resistance value of the power supply section to the common electrode. However, even if this countermeasure is taken, not only is it not completely eliminated, but also another countermeasure is required because the capacity of the common electrode increases due to the high definition and large screen of the liquid crystal display panel. In the present inventor, the cause of the horizontal smear phenomenon is that the parasitic capacitance existing between the signal line and the common electrode causes a change in the signal voltage transmitted to the signal line to change the potential of the common electrode. Paying attention to the fact that a voltage different from the voltage that should be originally applied between the pixel electrode and the common electrode is applied when writing the signal line voltage to
It has been considered that the noise transmitted from the signal line to the common electrode is canceled by using the inevitable parasitic capacitance. An object of the present invention is to provide a liquid crystal display device capable of performing stable display even in high definition and large screen. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Means for Solving the Problems The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, at the intersection of the signal line and the scanning line, T
A pixel substrate composed of an FT and a pixel electrode is arranged in a matrix, and a second substrate provided with a common electrode is provided so as to sandwich a liquid crystal on a first substrate formed by separating the signal lines at a central portion. A display panel is formed, and pixel signals having opposite polarities are supplied to the separated signal lines of the liquid crystal display panel. According to the above-mentioned means, since the pixel signals of opposite polarities are supplied to the signal lines separated at the center, noise components at the common electrode cancel each other out to stabilize the potential. As a result, stable display is possible even in high definition and large screen where the parasitic capacitance between the signal line and the common electrode increases. FIG. 1 is a schematic block diagram showing one embodiment of a liquid crystal display device according to the present invention. In the figure, a liquid crystal display panel in which some signal lines and scanning lines are exemplarily shown, a gate driver for forming a selection signal of the scanning line, and a drain driver for transmitting a pixel signal to the signal line are provided. It is shown. In the liquid crystal display panel of this embodiment, scanning line electrodes G1 to GM are arranged in a horizontal direction, and signal lines DU are arranged in a vertical direction.
1 to DU6 and DL1 to DL6 are arranged. As shown in the figure, the signal lines are separated at the center, and the upper signal lines DU1 to DU6 and the lower signal lines D
They are divided as L1 to DL6. The scanning lines G1 to GM and the signal lines DU1 to DU6 and DL1 to
A pixel cell is provided at the intersection of DL6. As shown in the equivalent circuit diagram of FIG. 2, the pixel cell includes, but is not limited to, a TFT having a double gate structure, a capacitor CLC composed of a pixel electrode, and an additional capacitance Cadd. The gate of the TFT is connected to, for example, the scanning line G1, and the drain is, for example, the signal line DU.
Connected to 1. The source of the TFT is connected to the capacitor CLC comprising the pixel electrode and an additional capacitance Cadd. The capacitor CLC is a capacitor using liquid crystal as a dielectric between a pixel electrode and a common electrode (not shown). The additional capacitance Cadd is for increasing the capacitance value of the pixel electrode to improve the retention characteristics of the pixel signal, and is formed between the additional scanning electrode G2 and the next scanning line G2. In FIG. 1, the pixel cell is also connected to the lower scanning line, which indicates that the above-described additional capacitance Cadd is provided. In FIG. 1, when viewed from the separated signal lines, the liquid crystal display panel is vertically separated. The upper panel is composed of a plurality of scanning lines G1 to GN, and the lower panel is composed of a plurality of scanning lines GN + 1 to GM. Although not particularly limited, both panels have the same number. As described above, in the liquid crystal display panel, although the signal lines are divided into upper and lower parts, the scanning line driver forms a selection signal for selecting, for example, the scanning lines G1 to the scanning lines GM in order regardless of the signal lines. . On the other hand, the upper and lower drain drivers output pixel signals having phases opposite to each other in parallel. For example, as shown in the timing chart of FIG. 3, when the scanning lines G1 to G4 of the upper panel are sequentially selected, the pixel signal corresponding to the scanning lines G1 to G4 is changed to the signal line DU corresponding to the upper panel.
The pixel signals are sequentially written to the selected pixels and sequentially written to the selected pixels. At this time, a signal whose phase is opposite to that of the pixel signal is also supplied to the signal line DL1 of the lower panel. However, as described above, the scanning lines G1 to G4 of the upper panel are selected, and the scanning lines G of the lower panel are selected.
N + 1 to GM are all in a non-selected state. That is, at this time, the signal line DL1 on the lower panel and the lower drain driver for supplying pixel signals of the opposite phase perform a dummy operation. When writing pixel signals to the upper panel as described above, since the lower panel performs a dummy operation, the noise component transmitted from the signal line DU1 of the upper panel when viewed from the common electrode of the liquid crystal display panel. And the noise component transmitted from the signal line DL1 by the dummy operation in the lower panel becomes a common mode, so that it can be canceled. Thereby, the potential of the common electrode is stabilized, and the pixel signal written to the pixel of the upper panel is
It becomes an original pixel signal transmitted from the signal line DU1. Conversely, although omitted in the figure, when writing pixel signals to the lower panel, the upper panel performs a dummy operation. Of the signal line DU due to the noise component transmitted from the signal line DL1 of FIG.
Since the noise component transmitted from No. 1 becomes a common mode, it can be canceled. As a result, the potential of the common electrode is stabilized, and the pixel signal written to the pixel of the upper panel becomes an original pixel signal transmitted from the signal line DL1. FIG. 5 is a block diagram showing one embodiment of the liquid crystal display device according to the present invention. FIG. 2 also shows a host system as a signal source. TF
The T liquid panel is large and is not particularly limited. However, three primary color pixels of RGB enable multicolor display. TFT
The signal lines of the liquid crystal panel are vertically separated as shown by the dotted lines in the figure, and a plurality of upper drain drivers are provided on the upper side corresponding to the separated signal lines, and a plurality of lower drain drivers are provided on the lower side. A drain driver is provided. The plurality of drain drivers which are separately provided above and below as described above are commonly connected to the data bus DB, and include the clock pulse CL2 and the line synchronization signal LS.
The YNC and the AC signal M are transmitted. Each of the drain drivers provided separately at the top and bottom is provided with a clock pulse C for serial input in the first stage drain driver.
When the data capture is completed by L2, the apparatus immediately enters a low power consumption mode in which the captured data is only held and no operation is performed. Although not shown in the figure, the output signal is set to low level to activate the drain driver of the next stage, and data is taken in by the subsequent clock pulse CL2. Hereinafter, similarly, when the capture of the pixel signal serially input from the data bus DB to the drain driver of the last stage is completed, the latch data captured by the clock pulse CL1 (not shown) formed by the line synchronization signal LSYNC is converted to the latch data. The signal is transferred to the line data latch circuit, and the pixel signal is supplied in parallel to the signal line of the TFT liquid crystal panel to start taking in the serial data corresponding to the next line. The scanning line electrodes are driven by a plurality of gate drivers. Each of the plurality of gate drivers has a plurality of output terminals, and receives a line synchronization signal LSYNC to switch sequentially selected scanning lines. The timing controller has at least one
It has an image memory for storing display data for the screen, and a host system (microcomputer or the like) inputs display data to the image memory. The timing controller sequentially reads out the data of the image memory in synchronization with the scanning timing of the liquid crystal display panel and generates serial data to be transmitted to the data bus DB, CL1, LSYNC and M signals. In this embodiment, the AC signal M is inverted by the inverter circuit and supplied to the lower drain driver provided corresponding to the lower panel. As a result, the same pixel data is input to the upper drain driver and the lower drain driver via the data bus DB as described above. However, since the alternating signals M have opposite phases as described above, for example, When the upper drain driver outputs a pixel signal with a positive polarity, the lower drain driver outputs a pixel signal with a negative polarity. By controlling the upper drain driver and the lower drain driver using the alternating signal M as in this embodiment, the same timing controller as that of the conventional liquid crystal display device can be used. In other words, a liquid crystal display panel having a signal line divided into two is used, and an inverter circuit for forming alternating signals having phases opposite to each other is provided. Since the drain driver, gate driver, and timing controller that have been used can be used as they are, a high-quality liquid crystal display device with a simple configuration can be obtained. FIG. 4 is a timing chart for explaining the operation of the liquid crystal display device of FIG. The pixel signal serially input to the data bus is a clock pulse C
The data is taken into the drain driver in synchronization with L2. When the line synchronization signal LSYNC is set to a high level, the gate driver performs a shift operation and switches the selected scanning line to the next scanning line. The line synchronization signal L
In response to a clock pulse CL1 (not shown) generated based on the SYNC signal and generated in the latter half thereof, the pixel signal captured by the sicil is transferred to the line data latch circuit in parallel. Then, the pixel signal corresponding to the next scanning line is fetched serially according to the low level of the line synchronization signal LSYNC. The alternating signal is set to a high level and a low level for each of a plurality of scanning lines. In this way, by making it possible to switch the polarity of the AC signal M during one frame, the AC frequency is made higher than the frame frequency to prevent flicker due to AC. The operation and effect obtained from the above embodiment are as follows. That is, (1) a pixel cell including a TFT and a pixel electrode is arranged in a matrix at an intersection of a signal line and a scanning line, and a liquid crystal is sandwiched between a first substrate in which the signal line is separated at a center portion so as to sandwich a liquid crystal. A liquid crystal display panel is formed by providing a second substrate provided with electrodes, and by supplying pixel signals having polarities opposite to each other to the separated signal lines of the liquid crystal display panel, common signals are supplied from the signal lines. Noise components on the electrodes are canceled out, and the potential can be stabilized, so that the parasitic capacitance between the signal line and the common electrode increases, so that stable display can be achieved even in high definition and large screen. The effect is obtained. (2) The same pixel signal is serially input to a signal line driving circuit for driving the separated signal lines of the liquid crystal display panel, and alternating signals are supplied in opposite phases to each other. Are sequentially selected, the drain driver, gate driver, and timing controller used in the conventional liquid crystal display device can be used as they are, so that a high-quality liquid crystal display device with a simple configuration can be obtained. Can be Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the upper and lower scanning lines may be selected at the same time. In this case, in the embodiment shown in FIG. 5, the upper drain driver and the lower drain driver are serially supplied with the pixel signals corresponding to the two scanning lines simultaneously selected by the data buses provided correspondingly. Is done.
In this case, strictly speaking, a symmetrical pixel signal is not supplied to the upper signal line and the lower signal line, but when a pixel signal having a positive polarity is supplied to the upper signal line as a whole, the lower signal line is not supplied. Is supplied with a pixel signal having a negative polarity, the noises acting on the common electrode can be canceled each other, so that a stable display operation can be performed. In this case, even when the number of pixels is increased due to the enlargement of the screen and the definition of the liquid crystal display panel, the time required for rewriting the pixel signal can be halved, and the frame frequency can be increased. Can be displayed. The present invention can be widely used as a liquid crystal display device using a TFT liquid crystal display panel in a display terminal such as a microcomputer or an electronic organizer, as well as in a television receiver. The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows. That is, at the intersection of the signal line and the scanning line, T
A pixel substrate composed of an FT and a pixel electrode is arranged in a matrix, and a second substrate provided with a common electrode is provided so as to sandwich a liquid crystal on a first substrate formed by separating the signal lines at a central portion. By configuring a display panel and supplying pixel signals having opposite polarities to the separated signal lines of the liquid crystal display panel, noise components from the signal lines to the common electrode are canceled out, and the potential of the noise component is reduced. Since the stabilization can be achieved, a stable display can be achieved even in high definition and a large screen in which the parasitic capacitance between the signal line and the common electrode increases. The same pixel signals are serially input to the signal line driving circuit for driving the separated signal lines of the liquid crystal display panel, and alternating signals having phases opposite to each other are supplied to sequentially scan the scanning lines. By making the selection, the drain driver, gate driver, and timing controller used in the conventional liquid crystal display device can be used as they are, so that a high-quality liquid crystal display device with a simple configuration can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram showing one embodiment of a liquid crystal display device according to the present invention. FIG. 2 is an equivalent circuit diagram showing one embodiment of a pixel cell in the liquid crystal display device. FIG. 3 is a waveform chart for explaining an example of the operation of the liquid crystal display device according to the present invention. FIG. 4 is a timing chart for explaining an example of the operation of the liquid crystal display device according to the present invention. FIG. 5 is a block diagram showing one embodiment of a liquid crystal display device according to the present invention. [Description of References] G1 to GM: scanning line, DU1 to DU6: upper signal line, D
L1 to DL6: lower signal line, DB: data bus, CL2
... Clock pulse, LSYNC ... Line synchronization signal, M ...
Alternating signal.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-249925 (JP, A) JP-A-62-269121 (JP, A) JP-A-4-70625 (JP, A) 93921 (JP, A) JP-A-2-161493 (JP, A) JP-A-4-186281 (JP, A) JP-A-7-44139 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 505-580 H04N 5/66 102

Claims (1)

(57) A first substrate in which pixel cells each composed of a TFT and a pixel electrode are arranged in a matrix at intersections of signal lines and scanning lines, and the signal lines are separated at a central portion. And a liquid crystal display panel including a second substrate provided with a common electrode with the liquid crystal interposed between the first substrate and a pixel signal having a polarity opposite to each other is supplied to the separated signal lines. and a signal line driver circuit, a signal for driving the separated signal lines of the liquid crystal display panel
The same pixel signal is serially input to the line drive circuit.
In the opposite direction corresponding to the alternating signal
Polarized pixel signals output simultaneously in parallel
And the scanning lines of the liquid crystal display panel are supplied from the signal line driving circuit.
1 line by scanning line drive circuit in synchronization with parallel output
Each pixel is sequentially scanned, and the pixel electrode connected to the scanning line via the TFT includes:
A signal having a polarity in any one of the pixel signals is written.
A liquid crystal display device characterized by being embedded therein .