JP3495562B2 - Clock recovery circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit for recovering a clock signal for data demodulation of a digital modulation signal from an AM data multiplex modulation signal in which an AM modulation signal is multiplexed with a digital modulation signal .

[0002]

2. Description of the Related Art A conventional data multiplex system is a time-division multiplex system as used in character multiplex broadcasting of television broadcasting,
It is roughly classified into the frequency multiplex system used in the character multiplex broadcast of FM broadcasting. However, in AM broadcasting, the occupied frequency band is narrow and frequency multiplexing and time division multiplexing cannot be used.
There is no AM data multiplex modulation device that multiplexes a digital modulation signal with an AM modulation signal, unlike the data multiplex broadcasting currently performed in television broadcasting and FM broadcasting.

The applicant of the present patent application is
There has been proposed an AM data multiplex modulation device that multiplexes a digital modulation signal with an AM modulation signal so as not to affect the M synchronous detection output (Japanese Patent Application No. 8-166636).

[0004]

DISCLOSURE OF THE INVENTION The present invention provides a digital modulation signal from an AM data multiplex modulation signal in which a digital modulation signal is multiplexed in the same frequency band and at the same time as the AM modulation signal.
And to provide a clock recovery circuit for reproducing a clock signal for data demodulation.

[0005]

The clock recovery circuit according to the present invention is for data demodulation of a digital modulation signal from an AM data multiplex modulation signal in which the digital modulation signal is multiplexed in the same frequency band and at the same time as the AM modulation signal. And a carrier wave extracting means for extracting a carrier wave of the AM modulated signal from the AM data multiplex modulated signal, and a phase comparator having one input of the carrier wave extracted by the carrier wave extracting means. , A loop filter that receives the output of the phase comparator, a voltage-controlled oscillator whose oscillation frequency is controlled by the output of the loop filter, and a frequency-controlled oscillator that divides the oscillation frequency of the voltage-controlled oscillator. And a frequency divider supplied as the other input.

According to the clock recovery circuit of the present invention, the carrier of the AM modulated signal is extracted from the AM data multiplex modulated signal by the carrier extracting means, and the extracted carrier and the output of the frequency divider are phased in the phase comparator. By comparison, the oscillation frequency of the voltage controlled oscillator is controlled based on the phase comparison output. As a result, the oscillation output of the voltage controlled oscillator is synchronized with the carrier wave of the AM modulation signal, and the oscillation output of the voltage controlled oscillator can be used as a clock signal for digital modulation signal demodulation separated from the AM data multiplex modulation signal.

Instead of the frequency divider, a direct digital synthesizer may be used which receives the oscillation output of the voltage controlled oscillator as an input and supplies the output as the other input of the phase comparator.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock recovery circuit according to the present invention will be described with reference to an embodiment. FIG. 1 is a block diagram showing the configuration of a clock recovery circuit according to an embodiment of the present invention.

Prior to the description of the clock recovery circuit according to the present invention, first, an AM data multiplex modulator will be described with reference to FIG.
It will be explained based on.

The AM data multiplex modulation device AM-modulates an A / D converter 111 for A / D converting an analog signal wave (hereinafter, also simply referred to as a signal) such as a voice signal and an output of the A / D converter 111. AM modulator 1 including AM modulator 112
1 and the carrier wave of the frequency fc generated by the frequency divider 122 described later is AM-modulated with a signal wave.

The AM data multiplexing modulator is, for example, 32M
2 MHz by dividing the oscillation frequency of the master clock oscillator 121 that oscillates at
z and a frequency divider 122 that generates an output of 6 kHz, and a frequency of 2 MHz from the frequency divider 122, and receives a carrier wave of frequency fc, two signals of orthogonal frequencies (fc + fα), and orthogonal frequencies (fc-fα). ), A direct digital synthesizer 123 for generating two signals, and 6 kb
Serial / parallel converter 1 for converting ps serial digital data I, Q into parallel digital data I, Q
24, and the output from the serial / parallel converter 124 is a QPSK baseband digital signal.
2M with K baseband digital signal generator 12
The output of Hz is used as a clock signal for the A / D converter 111,
The carrier wave of the frequency fc is used as a carrier wave in the AM modulator 112,
The 6 kHz output is sent to the serial / parallel converter 124 as a conversion clock signal.

The QPSK baseband digital signals I and Q output from the QPSK baseband digital signal generator 12 are supplied to the quadrature modulator 13 composed of the multipliers 131 and 132 and the adder 133, and the multiplier 131. The I data is multiplied by cos (ωc + ωα) t, the Q data is multiplied by sin (ωc + ωα) t by the multiplier 132, and both multiplication outputs are added by the adder 133 to obtain the carrier wave of the frequency (fc + fα). Are quadrature-modulated with a QPSK baseband digital signal. Where frequency (fc + fα)
And (fc-fα) are selected as the frequencies in the upper and lower sidebands by AM modulation.

On the other hand, the QPSK baseband digital signals I and Q output from the QPSK baseband digital signal generator 12 are supplied to a complex conjugator 14 which inverts the sign and takes the complex conjugate of the inversion output to be converted. In this case, the complex conjugator 14 can be configured by an inverter 141 that inverts the I signal.

QPSK output from the complex conjugator 14
The baseband digital signals I and Q are output to the multipliers 161, 1
62 and the quadrature modulator 16 including the adder 163, the multiplier 161 multiplies the I data by cos (ωc−ωα) t, and the multiplier 162 multiplies the Q data by sin (ωc−ω).
α) t is multiplied, and both multiplication outputs are added by the adder 163 to orthogonally modulate the carrier of the frequency (fc−fα) with the QPSK baseband digital signals I and Q output from the complex conjugator 14. To do. The output signal from the quadrature modulator 13 and the output signal from the quadrature modulator 16 are added by an adder 1
A, which is output from the adder 17, that is, the digital modulation signal and the AM modulator 11
The M-modulated signal is supplied to the adder 18 for addition, and the adder 1
The signal added in 8 is supplied to the D / A converter 20, converted into an analog signal, and sent out as an AM data multiplex modulated signal.

FIG. 3 schematically shows an AM data multiplex modulation process in the AM data multiplex modulation device shown in FIG. 2 configured as described above. In FIG. 3, the AM modulation signal output from the AM modulator 1 is shown as a in FIG. The output signal from the quadrature modulator 16, that is, the digital modulation signal is shown as b in FIG. 3, and the output signal from the quadrature modulator 13, that is, the digital modulation signal is shown as c in FIG. The digital modulation signal output from the adder 17 is the sum of b in FIG. 3 and c in FIG.
The multiple modulation signal is shown as d in FIG.

The AM data multiplex modulation process by the AM data multiplex modulation device shown in FIG. 2 will be described.

The AM modulation signal νAM (t) output from the AM modulator 11 has a carrier amplitude of 1, a carrier angular frequency of ωc (rad / s), a modulation degree of κ, and a signal wave of νm (t). Then, it is expressed as the following formula (1).

[0018]   νAM (t) = {1 + κνm (t)} cos ωct ... Formula (1)

The I and Q digital signal sequences generated by the QPSK baseband digital signal generator 12 are represented by In and Qn. The digital signal sequence of In and Qn is also referred to as a dibit. Here, it is assumed that In = ± 1 Qn = ± 1.

The output signal from the QPSK baseband digital signal generator 2 is branched into two parts, one of which is supplied with a carrier of frequency (fc + fα) and the quadrature modulator 3 is supplied.
To the angular frequency (ωc + ωα) (r
Quadrature modulates a carrier wave of ad / s). The output signal νDH (t) from the quadrature modulator 3 is as shown in the following equation (2).

[0021]   νDH (t) = In cos (ωc + ωα) t + Qn sin (ωc + ωα) t Equation (2)

The other output signal from the QPSK baseband digital signal generator 12 is supplied to the complex conjugator 14, and the signs of the output signals In and Qn are (-In) and (Qn) by the complex conjugator 14. Is converted to. This complex signal sequence is input to the quadrature modulator 16 to which a carrier having a frequency (fc−fα) is supplied, and the complex signal sequence has an angular frequency (ω
Quadrature-modulate a carrier of c−ωα) (rad / s). The output signal νDL (t) from the quadrature modulator 16 is as shown in the following equation (3).

[0023]   νDL (t) = − In cos (ωc−ωα) t + Qn sin (ωc−ωα) t (3)

Output signal νDH of equations (2) and (3)
(t) and νDL (t) are input to the adder 17 and added, and the digital output signal νD (t), which is the addition output, is as shown in the following equation (4).

[0025]   νD (t) ＝ νDH (t) ＋ νDL (t)         = In cos (ωc + ωα) t + Qn sin (ωc + ωα) t         −In cos (ωc−ωα) t + Qn sin (ωc−ωα) t (4)

The AM modulation signal νAM (t) and the digital modulation signal νD (t) are input to the adder 18 and added, and the AM data multiplex modulation signal ν (t) is expressed by the following equations (1) and (4). It becomes as shown in the equation (5).

[0027]   ν (t) ＝ νAM (t) ＋ νD (t)       = {1 + κνm (t)} cos ωct         + In cos (ωc + ωα) t + Qn sin (ωc + ωα) t         −In cos (ωc−ωα) t + Qn sin (ωc−ωα) t (5)

The case of AM synchronous detection of the AM data multiplex modulated signal modulated as described above will be described.

For coherent detection, the carrier wave cos ωc t is multiplied by the equation (5) to obtain the following equation.

[0030]   2 {ν (t) cos ωct}   = {1 + κνm (t)} + In cos ωαt + Qn sin ωαt     −In cos (−ωα) t + Qn sin (−ωα) t     + {1 + κνm (t)} cos2ωc t + In cos (2ωc + ωα) t     + Qn sin (2ωc + ωα) t−In cos (2ωc−ωα) t     + Qn sin (2ωc−ωα) t

Here, a low-pass filter is inserted in the AM synchronous detector to remove high frequency components. As a result, the following equation (6) is obtained.

[0032]   2 {ν (t) cos ωct} = {1 + κνm (t)} + In cos ωαt + Qn sin ωαt   −In cos (−ωα) t + Qn sin (−ωα) t = {1 + κνm (t)} + In cos ωαt + Qn sin ωαt   -In cos ωαt-Qn sin ωαt = 1 + κνm (t) ・ ・ ・ Equation (6)

As is clear from the above equation (6), since the digital modulation signal component is canceled, the rest of the equation (6)
By cutting the DC component of the signal and passing it through an amplifier, the signal wave νm (t) before being modulated by the AM data multiplexing modulator according to the embodiment of the present invention can be taken out. Therefore, it can be seen that the AM synchronous detection output is not affected when the AM synchronous modulation detection is performed on the AM data multiplexed modulated signal modulated by the AM multiplexing modulator shown in FIG.

In FIG. 2, the QPSK baseband digital signal generator 12 has another modulation system, for example, another PS.
It may be replaced with K, ASK, QAM, FSK, MSK, or the like. At present, two digital modulation carriers (frequency (fc + fα), frequency (fc−fα)) are used, but a plurality of digital modulation carriers are further used, for example, a plurality of multicarriers, frequency hopping, and OFDM. Etc. can also be used.

The AM data multiplex modulated signal modulated as described above has a modulation method of time division multiplex method or frequency multiplex method because the digital modulated signal is multiplexed in the same frequency band and same time as the AM modulated signal. Unlike the above case, the clock signal cannot be reproduced by selecting the time or frequency band in which the data is multiplexed to extract the desired digital modulation signal.

As shown in FIG. 1, a clock recovery circuit according to an embodiment of the present invention supplies an AM data multiplex modulated signal to a bandpass filter 1 having a narrower band than the bandwidth of the AM data multiplex modulated signal. The carrier wave of the AM-modulated signal is extracted, and the extracted carrier wave is supplied to the limiter 2 to remove the AM-modulated component that cannot be removed by the bandpass filter 1.
The output from the limiter 2 is supplied to the phase comparator 3.

The output of the phase comparator 3 is supplied to a loop filter 4 consisting of a low pass filter, smoothed and supplied to a voltage controlled oscillator 5 as a frequency control voltage. The free-running oscillation frequency of the oscillation output of the voltage controlled oscillator 5 is set to 32 MHz. The oscillation output of the voltage controlled oscillator 5 is sent as a reproduction clock signal and is also supplied to the direct digital synthesizer 6.

The direct digital synthesizer 6 supplies a frequency divider 61 for dividing the oscillation frequency of the voltage controlled oscillator 5 to 2 MHz and a frequency division output of the frequency divider 61 to a counter 62 for counting and counting the count value of the counter 62. Is supplied to the waveform data ROM 63 in which the waveform data is stored to read the waveform data. The waveform data read from the waveform data ROM is supplied to the D / A converter 64 and converted into an analog signal. After being supplied to the low-pass filter 7 to remove the aliasing component, it is supplied to the phase comparator 3. here,
The output from the frequency divider 61 is supplied to the D / A converter 64 as a conversion clock signal.

According to the clock recovery circuit of the embodiment of the present invention configured as above, the carrier of the AM modulation signal is extracted from the AM data multiplex modulation signal by the bandpass filter 1, and the extracted carrier wave is extracted. Then, the limiter 2 removes the AM modulation component that cannot be removed by the bandpass filter 1 and supplies it to the phase comparator 3 as a reference signal.

The output from the phase comparator 3 is smoothed by the loop filter 4, and the oscillation frequency of the voltage controlled oscillator 5 is controlled based on the output of the loop filter 4. The free-running oscillation frequency of the oscillation output of the voltage controlled oscillator 5 is set to 32 MHz. The oscillation output of the voltage controlled oscillator 5 is frequency-divided by the direct digital synthesizer 6, the waveform data is read from the waveform data ROM 63 by the count value of the counter 62 that counts the frequency-divided output, and the analog data is converted by the D / A converter 64. The signal is converted into a signal, supplied to the phase comparator 3 through the low-pass filter 7, and compared in phase with the carrier wave of the AM modulation signal.

Here, when the frequency of the output signal from the D / A converter 64 is different from the carrier frequency of the AM modulation signal, the beat based on the difference frequency is superimposed on the output from the loop filter 4. , The oscillation frequency of the voltage controlled oscillator 5 is changed. As a result, the carrier frequency of the AM modulated signal and the D / A converter 6 through the low pass filter
The output signal from 4 is synchronized with the carrier of the AM modulated signal.

Therefore, the oscillation output of the voltage controlled oscillator 5 becomes a clock signal which is synchronized with the carrier wave of the AM modulation signal, and the digital modulation signal obtained by separating the oscillation output of the voltage control oscillator 5 from the AM data multiplex modulation signal is demodulated. Can be used as a clock signal for.

Although the case where the direct digital synthesizer 6 is used in the clock recovery circuit according to the above-described embodiment of the present invention has been illustrated, a frequency divider may be used instead of the direct digital synthesizer 6. Also,
Although the case where the digital modulation method is QPSK in the clock recovery circuit according to the embodiment of the present invention described above is shown, the same applies to the case of other PSK, ASK, QAM, FSK, and MSK.

[0044]

As described above, according to the clock recovery circuit of the present invention, a digital modulation signal is converted from an AM data multiplex modulation signal in which the digital modulation signal is multiplexed in the same frequency band and at the same time as the AM modulation signal. A clock signal for data demodulation can be regenerated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a clock recovery circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an AM data multiplexing modulation apparatus for explaining a clock recovery circuit according to an embodiment of the present invention.

FIG. 3 is a schematic diagram for explaining the operation of the AM data multiplexing modulation apparatus shown in FIG.

[Explanation of symbols]

1 bandpass filter 2 limiter 3 Phase comparator 4 loop filter 5 Voltage controlled oscillator 6 Direct Digital Synthesizer 7 Low-pass filter 11 AM modulator 12 QPSK baseband digital signal generator 13 and 16 quadrature modulator 14 Complex conjugator 17 and 18 adder 121 Master clock oscillator

Continuation of front page (56) Reference JP-A-9-102775 (JP, A) JP-A-7-58636 (JP, A) JP-A-5-29981 (JP, A) JP-A-3-278633 (JP , A) JP-A-3-247037 (JP, A) JP-A-3-268525 (JP, A) JP-A-5-145498 (JP, A) Patent 3118419 (JP, B2) Patent 3088291 (JP, B2) Patent 3088292 (JP, B2) Patent 3088315 (JP, B2) Patent 3115251 (JP, B2) Patent 2929925 (JP, B2) Patent 2861542 (JP, B2) (58) Fields investigated (Int.Cl. ⁷ , DB name) ) H04J 9/00 H04J 15/00 H04L 27/00-27/38

Claims (2)

(57) [Claims] 1. A clock regeneration circuit for regenerating a clock signal for data demodulation of a digital modulated signal from an AM data multiplexed modulated signal multiplexed in the same frequency band and at the same time as the AM modulated signal, Carrier wave extracting means for extracting the carrier wave of the AM modulated signal from the AM data multiplex modulated signal, a phase comparator having the carrier wave extracted by the carrier wave extracting means as one input, and a loop filter having the output of the phase comparator as the input And a voltage-controlled oscillator whose oscillation frequency is controlled by the output of the loop filter, and a frequency divider which divides the oscillation frequency of the voltage-controlled oscillator and supplies the divided output as the other input of the phase comparator. A clock recovery circuit characterized by the above. 2. A clock regeneration circuit for regenerating a clock signal for data demodulation of a digital modulated signal from an AM data multiplexed modulated signal multiplexed in the same frequency band and at the same time as the AM modulated signal, Carrier wave extracting means for extracting the carrier wave of the AM modulated signal from the AM data multiplex modulated signal, a phase comparator having the carrier wave extracted by the carrier wave extracting means as one input, and a loop filter having the output of the phase comparator as the input And a voltage controlled oscillator whose oscillation frequency is controlled by the output of the loop filter, and a direct digital synthesizer which receives the oscillation output of the voltage controlled oscillator as an input and supplies the output as the other input of the phase comparator. Clock recovery circuit.