JP3473634B2 - Image processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus suitable for a monitor-mounted video camera, for example.

[0002]

2. Description of the Related Art Conventionally, there has been known a video camera equipped with an angular velocity sensor for detecting a motion and a microcomputer so as to prevent a shake of an optical axis during hand-held image pickup, that is, a so-called hand shake, on a memory. .

First, an example of a conventional image stabilization type video camera will be described with reference to FIGS. In FIG. 11, 10 is an imaging system, 20 is a control system, 3
Reference numeral 0 is an output system and 40 is a memory system.

In the image pickup system 10, the image pickup light passing through the lens 11 is converted into an analog video signal by the CCD type solid-state image pickup element 12. The output of the image pickup device 12 is passed through the sample and hold / AGC circuit 13 and the A / D converter 1
4 and is converted into, for example, an 8-bit digital video signal. The digital video signal is subjected to signal processing such as gamma correction and white balance in the image pickup signal processing circuit 15, and is supplied to the memory system 40.

On the other hand, in the control system 20, the angular velocity sensor 21
Is supplied to a microcomputer 24 for motion vector calculation through a high-pass filter 22, an amplifier (not shown), and an AD converter 23. In the microcomputer 24, the angle information of the azimuth angle φ and the elevation angle θ is obtained by the integral calculation, and this angle information is further processed and supplied to the memory system 40 as motion vector information. Further, a control signal from the zoom key 25 is sent via the microcomputer 24 to the memory system 4
Supplied to zero.

The memory system 40 includes a field memory 41 and a field memory 4 as shown in FIG.
Address control circuits 42 and 43 for controlling the write address and the read address of 1 are included.

In the memory system 40, the input image data is written in the field memory 41, and the reading of the image data from the field memory 41 is controlled based on the motion vector information, so that the camera shake is corrected. .

Electronic zoom (enlargement) is performed based on a control signal from the zoom key 25. In this electronic zooming, the video data in the memory 41 is appropriately enlarged and read according to the enlargement ratio.

The output signal from the memory system 40 is the output system 3
In the video signal processing circuit 31 of 0, it is shaped as a composite video signal, converted into an analog video signal by the DA converter 32, and supplied to the display element 33.
Then, the image of the subject is displayed on the screen of the display element 33.

When the recording mode is switched by the mode switching signal Smd, the recording signal processing unit 31r performs necessary signal processing such as emphasis, frequency modulation and low frequency conversion, and the DA converter. A recording amplifier (not shown), which is converted into an analog video signal by 34.
Is supplied to the video head 35 through the magnetic tape M
Recorded in T.

In FIG. 12, the address control circuit 42 for writing has an initial value V supplied to its load terminal LD.
The video data is sequentially written in the memory space of the memory 41 by controlling the address of the field memory 41 to be sequentially increased from st. Similarly, the read address control circuit 43 also controls so that the address of the field memory 41 is sequentially increased from the initial value Vst supplied to the load terminal LD, so that the video data in the memory space of the memory 41 is It is read out sequentially.

Therefore, the vertical synchronizing signal W of the input video signal
VD is directly supplied to the control terminal CT of the address control circuit 42 to be used as a reference for the writing timing of the field memory 41, and the control terminal CT of the address control circuit 43 has a delay time slightly shorter than 1V. Through the delay circuit 44, it is supplied as a delayed synchronization signal RVD, which apparently slightly precedes the vertical synchronization signal WVD, and is used as a reference for read timing. The initial value Vst of the address of the memory 41 is the zero line of the head address.

During normal photographing, the input / output of the memory system 40 is delayed by one field period (1 V). On the field memory 41, as shown by a solid line W and a dotted line R in FIG. In accordance with the vertical synchronizing signal WVD, for example, the writing W of the video data of the Nth field is performed.
When (N) starts from the leading zero line and the writing of up to 250 lines at the end of the effective line ends, the read R (N) of the video data of the same N-th field is read according to the delay synchronization signal RVD. Start from the start address. Then, a little later than this reading, the subsequent N
Writing W (N + 1) of the + 1st field starts.

Similarly, the video data of each field are sequentially written and read out, and a normal image of the subject is displayed on the screen 33sc of the display element.

Further, in the case of the electronic zoom, as shown in FIG. 14, when simple writing / reading is performed, the reading of the preceding field overtakes the writing of the following field, which is displayed on the screen of the display element. The image becomes discontinuous.

Therefore, in the case of the electronic zoom, as shown in FIG. 15, the end of the write address of the memory is controlled to be the end of the enlarged read address, and the enlarged read is performed while avoiding overtaking.

For example, the write W (N + 1) of the N + 1th field is the read end address RVE (N) of the enlarged area indicated by the thick line in the write W (N) of the preceding Nth field, and the following. The write start address WADS (N +) so that the write end address WADE (N + 1) of the N + 1th field matches.
You can start from 1).

The write address control in the case of the enlargement processing as described above is expressed by a mathematical expression: WADS (N + 1) = WADS (N) + RVE (N)-
It becomes Vmax. However, when WADS> Amax, WADS '= WADS-Amax, and when WADS <0, WADS' = WADS + Amax. That is, the write start address WADS takes a value in the range of 0 ≦ WADS ≦ Amax.

Here, WADS: Write start address of memory WADE: Write end address of memory Amax: Maximum value of memory address Vmax: Number of video signal lines written in memory RVE: Read end address of enlarged area (Spatial reading end position) Is.

In the current 525/60 system, the number of lines Vmax written in the memory is set to the number of effective lines of the video signal in one field period, for example, 250 lines.
Further, when the camera shake is corrected, the maximum value Amax of the address of the memory is slightly larger than the above-mentioned number of effective lines, for example, 300 lines. Further, in the case of the electronic zoom of FIG. 15, the enlargement magnification is set to 2.

[0021]

By the way, recently, in a camera-shake preventing type video camera as shown in FIG. 11, the horizontal axis perpendicular to the optical axis of the lens 11 is used as a center.
A so-called face-to-face photographing is commercially available in which the display element 33 is rotated by 180 ° and the lens 11 and the screen of the display element 33 are opposed to the photographer himself as a subject. In the case of this face-to-face shooting, it is necessary to display an image in which the vertical and horizontal directions are reversed on the screen of the display element 33 as compared with the case of the normal shooting.

In order to realize the above-mentioned vertical inversion function, the video sequentially written from the head address on the field memory is read sequentially from the tail address, contrary to the writing.

However, as shown by the solid line W and the dotted line R in FIG. 16, for example, the writing W (N) of the video data of the Nth field is performed in ascending order from the start address to the end address of the field memory. After that, when the read R (N) of the video data of the same N-th field starts in descending order from the end address of the memory, this read R
In the middle of (N), the writing W (N + 1) of the subsequent N + 1th field is crossed, and thereafter, reading R (N + 1) of the N + 1th field is performed.

That is, the reading of the video data of the preceding field overtakes the writing of the video data of the subsequent field, and as shown in FIG. 16, the video displayed on the screen 33sc of the display element is before and after the passing. There was a problem of being discontinuous.

Further, in order to realize the horizontal inversion function of displaying the image on the memory by reversing the left and right, the start address is set on the line memory so that it can be easily understood by analogy to the above-mentioned vertical inversion. The video written in ascending order is read from the end address in descending order, which is the reverse of the writing. However, there is a problem that the video displayed on the screen of the display element becomes discontinuous before and after passing the writing of the video data.

In view of the above point, the present invention is such that the reading of the video data of the preceding field (or line) overtakes the writing of the video data of the following field (or line) during the inversion processing of the moving image on the memory. An object is to provide an image processing device that can be avoided.

[0027]

In order to solve the above-mentioned problems, an image processing apparatus according to the invention of claim 1 has a field memory in which video data is sequentially written and read, and a write and read address of this field memory are set vertically. In an image processing device including a write control unit and a read control unit that respectively control based on a synchronization signal, in the reverse order of writing the video data of the preceding field, the video data of the succeeding field after the preceding field is stored in the field. Controlling the write control means so as to be written in the memory, and controlling the read control means so that the video data written in the field memory is read out in the reverse order of the writing of the video data; , Reading the video data of the preceding field However, the writing of the video data of the subsequent field is performed in the same order, and the writing of the video data of the subsequent field is delayed by a predetermined time with respect to the reading of the video data of the preceding field. It is characterized in that it is provided with a control unit for controlling as described above. Further, in the image processing apparatus according to the invention of claim 2, a line memory to which video data is sequentially written and read, and a write control means and a read control for respectively controlling the write and read addresses of the line memory based on the horizontal synchronizing signal. An image processing device including means for controlling the write control means so that video data of a subsequent line subsequent to the preceding line is written in the line memory in the reverse order of writing the video data of the preceding line, and The read control means is controlled so that the video data written in the line memory is read in the reverse order of the writing of the video data, and the video data of the preceding line and the video data of the subsequent line are read. The same order as the writing of The read image data of a line, the writing of the video data of the subsequent line, a predetermined time, characterized in that it comprises a control unit for controlling to delay.

[0028]

According to the invention of claim 1 or claim 2 having the above-mentioned structure
According to the control unit, the field memory or line
Video data is read from the memory in the reverse order of writing, and the video image is inverted in the field memory or line memory , and the preceding field or preceding
And reading of the image data of a line, succeeding field also
The predetermined time difference is held, leading field or preceding line <br/> read is avoided overtake writing of the video data of the subsequent field or subsequent line between the writing of the video data of the subsequent line .

[0029]

【Example】

[First Embodiment] A first embodiment of the image processing apparatus according to the present invention will be described below with reference to FIGS. The configuration of the first embodiment of the present invention is shown in FIG. In FIG. 1, parts corresponding to those in FIG. 12 described above are denoted by the same reference numerals, and redundant description will be omitted.

In FIG. 1, reference numeral 40A denotes a memory system. In addition to the memory system 40 shown in FIG.
A pair of toggle circuits 45 and 46 and a pair of changeover switch 4
7, 48 are provided.

The vertical synchronizing signal WVD and the delayed synchronizing signal RVD are supplied to the toggle circuits 45 and 46, respectively, and control signals WVALT and RV are inverted every V cycle as shown in FIG.
VALT is generated. The control signals WVALT and RVALT are supplied to the control terminals CT of the address control circuits 42 and 43, respectively, and the switches 47 and 47 are used as switching control signals.
48 respectively.

The movable contacts of both switches 47 and 48 are respectively connected to the load terminals LD of the address control circuits 42 and 43, and the microcomputer 24 (see FIG. 11) is used as the L-side fixed contact and the H-side fixed contact. From, the initial values Vstup and Vstdn of the address of the memory 41 are respectively supplied. The rest of the configuration is similar to that shown in FIG.

When the image processing apparatus of this embodiment is mounted on the video camera shown in FIG. 11, the image processing apparatus shown in FIG.
The control signal from the inversion control switch 26 indicated by the broken line in FIG. 1 and the rotation detection sensor (not shown) of the video camera is
It is supplied to the memory system 40A via the microcomputer 24.

[Vertical Inversion Processing] Next, the vertical inversion processing of the embodiment shown in FIG. 1 will be described with reference to FIG.

In the embodiment shown in FIG. 1, in the case of the vertical inversion processing,
Switch 4 when control signals WVALT and RVALT are "L"
7, 48 are connected to the L contact side as shown, and addition control is performed in the address control circuits 42, 43 so as to sequentially increase the address of the field memory 41.

Further, when the control signals WVALT and RVALT are "H", the switches 47 and 48 are switched to the states opposite to those shown in the drawing so as to be connected to the H contact side and the address control circuits 42 and 43. , Subtraction control is performed so as to sequentially decrease the address of the field memory 41.

In the case of the vertical inversion processing of the embodiment shown in FIG. 1, the initial values Vstup and Vstdn of the addresses are the initial and final lines Vmin (= 0 line) and Vmax (= of the effective video signal to be written in the memory 41, respectively. 250 lines).

As a result, as shown by the solid line W and the dotted line R in FIG. 2, for example, the writing W (N) of the video data of the Nth field is performed in ascending order from the address Vmin of the field memory 41 to the address Vmax. Then, in the next field period, the read R (N) of the video data of the same N-th field starts in the descending order from the address Vmax of the memory 41, and after a slight delay from this read R (N), The write W (N + 1) of the N + 1th field is the same as the address Vm of the memory 41.
Starting from ax in descending order. In the same manner, writing and reading of video data of each field are sequentially performed.

As described above, in the vertical inversion processing of this embodiment, the video data of the succeeding field is written in the memory in the reverse order of the preceding field, and the video data of the preceding field is written slightly before this writing. Since the reading from the memory is performed in the reverse order to the above, the reading of the preceding field and the writing of the succeeding field become the same order, and a predetermined time difference is maintained between them, and the reading of the preceding field overtakes the writing of the succeeding field. Never.

Therefore, the moving image can be vertically inverted without causing the discontinuity as described above.

[Enlarged Vertical Inversion Processing] Next, the enlarged vertical inversion processing of the first embodiment of FIG. 1 will be described with reference to FIG.

In the embodiment of FIG. 1, also in the case of the enlarged vertical inversion processing, as in the case of the above-described vertical inversion processing, the field memory according to "L" or "H" of both control signals WVALT, RVALT. The addition control or the subtraction control of the address of 41 is performed, and the switching control of the switches 47 and 48 is performed.

Further, as in the case of the electronic zoom described above,
The initial address values Vstup and Vst are set so that the beginning of the memory write address is the end of the enlarged read address.
dn is controlled.

Thus, as shown by the solid line W and the dotted line R in FIG. 3, for example, the writing W (N) of the video data of the Nth field is the address V of the field memory 41.
From min (= 0 line) to address Vmax (= 250
Line)) in ascending order and then in the next field period, the read R (N) of the video data of the enlarged area shown by the thick line in this write W (N) starts in descending order, and this read R (N) ), A subsequent write W (N + 1) of the N + 1th field also starts in descending order.

The writing of the N + 1th field is performed in the following manner so that the writing end address WADE (N + 1) of the N + 1th field and the enlarged read end address RVE (N) of the Nth field match. It is started from the write start address WADS (N + 1) obtained by a mathematical expression. And so on
The video data of each field is sequentially written and enlarged read.

In the case of the enlargement upside-down process of FIG.
Although the enlargement ratio is illustrated as being set to 2, the enlargement ratio is not limited to this.

In the case of the enlarged vertical inversion processing in this embodiment, the write start address WADS (N + 1) is WV.
When ALT is “H”, WADS (N + 1) = WADS (N) + RVE (N) +
When Vmax is reached and WVALT is "L", WADS (N + 1) = WADS (N) -RVE (N)-
It becomes Vmax.

However, when WADS> Amax WADS '= WADS-n · Amax And when WADS <0, WADS '= WADS + n · Amax Becomes That is, n is an integer, 0 ≦ WADS ≦ Amax Takes a value such that

Where WADS: memory write start address WADE: memory write end address Amax: maximum memory address Vmax: number of video signal lines to be written in memory RVE: memory read end address (spatial read End position).

As described above, in the enlargement upside-down inversion processing of this embodiment, the video data of the succeeding field is written in the memory from a predetermined address in the reverse order of the preceding field. Since the video data in the predetermined range of the field is read out from the memory in the reverse order of the writing, the reading of the preceding field and the writing of the succeeding field are in the same order, and a predetermined time difference is ensured between them, and the preceding field is secured. Reading does not overtake writing in subsequent fields.

Therefore, the moving image can be enlarged and vertically inverted without causing the discontinuity as described above.

[Second Embodiment] Next, a second embodiment of the image processing apparatus according to the present invention will be described with reference to FIGS.

The structure of another embodiment of the present invention is shown in FIG. In FIG. 4, portions corresponding to those in FIGS. 1 and 12 described above are denoted by the same reference numerals, and redundant description will be omitted.

In FIG. 4, reference numeral 40B denotes a memory system, which corresponds to odd / even fields of input video data, instead of the single field memory 41 of the memory system 40A as shown in FIG. A pair of field memories 41o and 41e are provided, and a pair of switches corresponding to the write enable signal and the read enable signal on the input side and the output side of the field memories 41o and 41e, respectively, for convenience of explanation. Switch 49
w, 49r are provided.

As shown in FIG. 5, the field identification signal FLD, which is inverted every V cycle, is directly supplied to one of the changeover switches 49w as a changeover control signal.
The other changeover switch 49r is supplied through the delay circuit 49d. The delay time of the delay circuit 49d is set to be slightly shorter than 1V, like the delay circuit 44 described above. The control signals from the address control circuits 42 and 43 are commonly supplied to the field memories 41o and 41e, respectively. The rest of the configuration is the same as in FIG.

[Vertical Inversion Process with Frame Delay] Next, the vertical inversion process with frame delay of the embodiment of FIG. 4 will be described with reference to FIG.

In the vertical inversion process accompanied by the frame delay, the input / output of the memory system 40B is delayed by one frame period (2V), and the pair of changeover switches 49w and 49r are set for every 1V. , The connection state shown in the figure and the connection state opposite to that shown in the figure are switched.

Further, as shown in FIG. 5, the toggle circuit 45
The control signal WVALT from the toggle circuit 46 is also inverted every 2V period, and the control signal RVALT (not shown) from the toggle circuit 46 is also inverted every 2V period.
When LT is “L”, the address control circuits 42 and 43
Addition control is performed so as to sequentially increase the addresses of both field memories 41e and 41o, and when the control signals WVALT and RVALT are "H", the address control circuits 42 and 43 cause both field memories 41e and 41o.
The subtraction control is performed so as to sequentially decrease the addresses of.

Then, the initial values of the addresses Vstup and Vstdn
Are the lines Vmin (= 0 line) and Vmax (= 250 line) at the beginning and end of the effective video signal to be written in the field memories 41e and 41o, respectively, as in the case of the vertical inversion processing of the embodiment of FIG. .

As a result, on one memory 41e,
As shown by the solid line W and the dotted line R in FIG. 5A, for example, the writing W (2N) of the video data of the 2Nth field is written in the address Vm of the memory 41e for each even field.
1 is performed after ascending order from in to address Vmax.
After the V period elapses, the read R (2N) of the video data of the same 2Nth field starts in descending order from the address Vmax of the memory 41e, and slightly later than this read R (2N), the subsequent 2N + 2nd Field writing W (2N + 2) also starts in descending order from address Vmax of memory 41.

On the other memory 41o, as shown in FIG.
As indicated by a solid line W and a dotted line R, for example, the reading R (2N-1) of the video data of the preceding 2N-1th field is in ascending order from the address Vmin of the memory 41o to the address Vmax for each odd field. Then, after a slight delay, the writing W (2N + 1) of the video data of the subsequent 2N + 1th field is performed by the memory 41.
It starts in ascending order from the address Vmin of o. In the same manner, writing and reading of video data of each field are sequentially performed.

As described above, in the vertical inversion processing of FIG.
In each of the field memories 41o and 41e, the video data of the succeeding field is written in the memory in the reverse order of the preceding field for each corresponding odd / even field. Since the video data is read from the memory in the reverse order of the writing, the reading of the preceding field and the writing of the succeeding field are in the same order, and a predetermined time difference is maintained between them, and the reading of the preceding field is performed in the succeeding field. Never overtakes writing.

Therefore, the image can be vertically inverted without causing the discontinuity as described above.

[Enlarged Vertical Inversion Process with Frame Delay]
Next, referring also to FIG. 6, the enlarged vertical inversion process with frame delay of the embodiment of FIG. 4 will be described.

In the enlarged vertical inversion process with the frame delay, as in the case of the vertical inversion process shown in FIG.
One frame period (2 times between the input and output of the memory system 40B)
V), and the changeover switch 49
Each of w and 49r is switched between the connected state shown in the drawing and the connected state opposite to that shown in the drawing every 1V.

Further, as shown in FIG. 6, the toggle circuit 45
Control signal WVALT from the toggle circuit 46 is also inverted every 2V period, and a control signal RVALT (not shown) from the toggle circuit 46 is also inverted every 2V period.
Both field memories 4 depending on "L" or "H" of
The addition or subtraction control of the addresses 1e and 41o is performed, and the switching control of the switches 47 and 48 is performed. Further, similarly to the case of the enlarged vertical inversion processing shown in FIG. 3, the end of the write address of the memory is controlled to be the end of the enlarged read address.

As a result, on one memory 41e,
As shown by the solid line W and the dotted line R in FIG. 6A, for example, the writing W (2N) of the video data of the 2Nth field is written in the address Vm of the memory 41e for each even field.
1V period elapses after in ascending order from in (= 0 line) to address Vmax (= 250 line),
The reading R (2N) of the video data of the enlarged area shown by the thick line in the writing W (2N) starts in descending order, and after a slight delay from the reading R (2N), the subsequent 2N +
The second field write W (2N + 2) also begins in descending order.

On the other memory 41o, as shown in FIG.
As indicated by the solid line W and the dotted line R, for example, the reading R (2N-1) of the video data of the expansion region of the preceding 2N-1th field starts in descending order for each odd field, and this reading R ( 2N + 1), slightly later than the write W (2N +) of the subsequent 2N + 1th field.
1) also starts in descending order. In the same manner, writing and enlargement reading of the video data of each field are sequentially performed.

In the case of the enlargement upside-down process of FIG.
Although the enlargement ratio is illustrated as being set to 2, the enlargement ratio is not limited to this.

As described above, in the enlarged vertical inversion processing of FIG. 6, the video data of the succeeding field is written into the memory from a predetermined address in the reverse order of the preceding field for each odd / even field. Just before the writing, the video data in the predetermined range of the preceding field is read out from the memory in the reverse order of the writing, so that the reading of the preceding field and the writing of the succeeding field are in the same order, and a predetermined time difference occurs between them. Is ensured so that the reading of the preceding field does not overtake the writing of the following field.

Therefore, the moving image can be enlarged and vertically inverted without causing the discontinuity as described above.

[Third Embodiment] Next, a third embodiment of the image processing apparatus according to the present invention will be described with reference to FIGS. 7 and 8.

The configuration of the third embodiment of the present invention is shown in FIG. In FIG. 7, parts corresponding to those in FIG. 4 described above are denoted by the same reference numerals, and description thereof will be partially omitted.

In FIG. 7, reference numeral 40C designates a memory system, which corresponds to the odd and even fields of the input video data, as in the memory system 40B shown in FIG.
A pair of field memories 41o and 41e are provided, and a pair of changeover switches 49w for convenience of description corresponding to the write enable signal and the read enable signal on the input side and the output side of the field memories 41o and 41e, respectively. , 49r are provided.

As a switching control signal, a field identification signal FLD which is inverted every V cycle as shown in FIG.
The delay circuit 4 is supplied to one of the switches 49w.
It is supplied to the other switch 49r via 9d. The delay time of the delay circuit 49d is set to approximately 1V.

At the control terminals CT of the address control circuits 42 and 43, the vertical synchronizing signal WVD as shown in FIG. 8 and the delayed synchronizing signal RVD obtained by delaying the synchronizing signal WVD by the delay circuit 44 are respectively provided. Supplied.

The load terminal LD of the address control circuit 42 has an initial value V of the addresses of the memories 41o and 41e.
The stup is directly supplied from the microcomputer 24 (see FIG. 11), and the load terminal LD of the address control circuit 43 is supplied with the initial address values Vstup and Vstdn through the changeover switch 48. This switch 4
A switching control signal UP / DN from the microcomputer 24 is supplied to 8. The other structure is the same as that shown in FIG.

[Vertical Inversion Process with Field Delay] Next, the vertical inversion process with field delay of the embodiment shown in FIG. 7 will be described with reference to FIG.

In the vertical inversion process with the field delay, the input / output of the memory system 40C is delayed by one field period (1V), and the changeover switches 49w and 49r are set to different connection states. ,
The connection state shown in the drawing and the connection state opposite to that shown in the drawing are switched for each 1V.

Further, the switching control signal UP / DN is "H".
Then, the switch 48 is switched to the connection state shown in the figure, and at the time of writing, the field memories 41o, 41
The address addition of e is controlled, and at the time of reading, the address subtraction of the field memories 41o and 41e is controlled.

Then, the initial values of the addresses Vstup and Vstdn
Are the lines Vmin (= 0 line) and Vmax (= 250 line) at the beginning and end of the effective video signal to be written in the field memories 41e and 41o, respectively, as in the case of the vertical inversion processing of the embodiment of FIG. .

As a result, one of the field memories 41
8e, as shown by a solid line W and a dotted line R in FIG. 8A, for example, the writing W (2N) of the video data of the 2Nth field is incremented from the address Vmin to the address Vmax of the field memory 41e for each even field. After the ascending order is performed, the reading R (2N) of the video data of the same 2Nth field is performed in the next field period.
Starting from the address Vmax of the memory 41e in descending order.

Further, on the other field memory 41o, as shown by the solid line W and the dotted line R in FIG. 8B, for example, the writing W (2N + 1) of the video data of the 2N + 1th field is written in every field. After the address 41 from the address Vmin to the address Vmax of the memory 41o is processed in ascending order, in the next field period, the same 2N
Read out video data of + 1st field R (2N
+1) starts from the address Vmax of the memory 41o in descending order. In the same manner, writing and reading of video data of each field are sequentially performed.

As described above, in the vertical inversion processing of FIG.
In both field memories 41o and 41e, writing and reading are not performed within the same field period for each corresponding odd / even field, so that reading of the preceding field does not overtake writing of the following field. . Therefore, the video can be vertically inverted without causing the discontinuity as described above.

In the embodiment of FIG. 7, even in the case of the enlarged vertical inversion process involving the field delay, the writing and the reading are not performed in the same field period, so that the reading of the preceding field follows. You can enlarge and flip the image upside down without overtaking the writing in the field.

[Embodiment for Left-Right Reversal Processing] Next, a fourth embodiment of the image processing apparatus according to the present invention will be described with reference to FIGS. 9 and 10.

The configuration of the fourth embodiment of the present invention is shown in FIG. In FIG. 9, the parts corresponding to FIG.
The last one digit is given the same reference numeral, and the description is partially omitted.

In FIG. 9, reference numeral 50 denotes a left-right inversion processing system, which is the field memory 4 of the memory system 40A shown in FIG.
Instead of 1, the line memory 51 is provided, and the write address and the read address of the line memory 51 are controlled by the address control circuits 52 and 53.

The horizontal synchronizing signal WHD of the input video signal is directly supplied to the control terminal CT of the address control circuit 52 to be used as a reference for the write timing of the line memory 51 and the control terminal CT of the address control circuit 53. For 1H
It is supplied as a delayed sync signal RHD, which is slightly ahead of the horizontal sync signal WHD, through the delay circuit 54 having a delay time slightly shorter than that, and is used as a reference for the read timing.

The horizontal synchronizing signal WHD and the delayed synchronizing signal RHD are supplied to the toggle circuits 55 and 56, respectively.
A control signal W that is inverted every H period as shown in FIG.
HALT and RHALT are generated. This control signal WHALT, RHA
LT is supplied to the control terminals CT of the address control circuits 52 and 53, respectively, and is also supplied to the switches 57 and 58 as a switching control signal.

The movable contacts of both switches 57 and 58 are respectively connected to the load terminals LD of the address control circuits 52 and 53, and the L side fixed contact and the H side fixed contact respectively have the initial value of the address of the memory 51. Hstup and Hstdn are supplied.

Next, the horizontal inversion processing of the embodiment of FIG. 9 will be described with reference to FIG.

In the fourth embodiment, the first example shown in FIG.
As can be understood by analogy with the case of the vertical inversion processing of the embodiment of FIG. 5, when the control signals WHALT and RHALT are “L”, the switches 57 and 58 are connected to the L contact side as shown in the drawing. In the address control circuits 52 and 53, addition control is performed so as to sequentially increase the address of the line memory 51.

Further, when the control signals WHALT and RHALT are "H", the switches 57 and 58 are switched to the states opposite to those shown in the drawing so as to be connected to the H contact side and the address control circuits 52 and 53. The subtraction control is performed so as to sequentially decrease the address of the line memory 51.

In the case of the horizontal inversion processing of the embodiment shown in FIG. 9, the initial address values Hstup and Hstdn are the addresses Hmin (= 0 dot) and Hmax of the memory 51, respectively.
(= 910 dots).

As a result, as shown by the solid line W and the dotted line R in FIG. 10, for example, the writing W (N) of the video data of the Nth line is Hm at the address of the line memory 51.
After in ascending order from in to Hmax of address,
During the next line period, the read R (N) of the video data of the same N-th line starts in descending order from the address Hmax of the memory 51, and slightly after this read R (N), the subsequent N + 1-th line. Writing W (N + 1)
Similarly starts from the address Hmax of the memory 51 in descending order. In the same manner, writing and reading of video data of each line are sequentially performed.

As described above, in the horizontal inversion processing of this embodiment, the video data of the succeeding line is written in the memory in the reverse order of the preceding line, and the video data of the preceding line is written slightly before this writing. Since the data is read from the memory in the reverse order of, the reading of the preceding line and the writing of the succeeding line are in the same order, and a predetermined time difference is maintained between them, and the reading of the preceding line overtakes the writing of the succeeding line. Never.

Therefore, the moving image can be horizontally reversed without causing the discontinuity as described above.

Incidentally, in the case of performing the enlarged horizontal reversal process corresponding to the above-described enlarged vertical reversal process, for example, as shown in FIG.
Similar to the case of the enlargement upside-down reversal process of No. 1, it can be appropriately performed.

[0100]

As described above, according to the present invention, the reading order control means is provided, and the reading control means is controlled so as to read the moving image data for a predetermined period in the reverse order of the writing. At the same time, since the time difference holding means is provided and the writing control means is controlled so as to hold a predetermined time difference between the reading of the preceding predetermined period and the writing of the following predetermined period, the field memory (or It is possible to prevent the reading of the preceding field (or line) from overwriting the writing of the following field (or line) during the inversion processing of the moving image on the (line memory), and the read moving image may not be reproduced by overtaking the reading. An image processing device in which continuity does not occur can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment of FIG.

FIG. 3 is a timing chart for explaining another operation of the embodiment of FIG.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention.

5 is a timing chart for explaining another operation of the embodiment of FIG.

FIG. 6 is a timing chart for explaining the operation of the embodiment of FIG.

FIG. 7 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 8 is a timing chart for explaining the operation of the embodiment of FIG.

FIG. 9 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 10 is a timing chart for explaining the operation of the embodiment of FIG.

FIG. 11 is a block diagram for explaining the present invention.

FIG. 12 is a block diagram showing a configuration example of a conventional image processing apparatus.

FIG. 13 is a timing chart for explaining the operation of the conventional example.

FIG. 14 is a timing chart for explaining another operation of the conventional example.

FIG. 15 is a timing chart for explaining another operation of the conventional example.

FIG. 16 is a timing chart for explaining the present invention.

[Explanation of symbols]

10 Imaging system 20 control system 30 output system 40, 40A-40C memory system 41, 41e, 41o Field memory 42, 43, 52, 53 Address control circuit 44,54 Delay circuit 45,46,55,56 toggle circuit 50 Left-right inversion processing system 51 line memory

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/222-5/257 H04N 5/907 H04N 5/937 H04N 7/18

Claims (4)

(57) [Claims] 1. An image processing apparatus comprising: a field memory into which video data is sequentially written and read; and write control means and read control means for controlling write and read addresses of the field memory based on a vertical synchronizing signal. Controlling the write control means so that the video data of the succeeding field after the preceding field is written in the field memory in the reverse order of the writing of the video data of the preceding field. The read control means is controlled so that the video data is read in the reverse order of the writing of the video data, and the reading of the video data of the preceding field and the writing of the video data of the subsequent field are in the same order. So that An image processing apparatus, comprising: a control unit that controls the writing of the video data of the succeeding field to be delayed for a predetermined time with respect to the reading of the video data of the preceding field. 2. An image processing apparatus comprising: a line memory into which video data is sequentially written and read; and write control means and read control means for controlling write and read addresses of the line memory based on a horizontal synchronizing signal. The write control means is controlled so that the video data of the succeeding line following the preceding line is written in the line memory in the reverse order of the writing of the video data of the preceding line, and the video data written in the line memory. The reading control means is controlled so that the reading is performed in the reverse order of the writing of the video data, and the reading of the video data of the preceding line and the writing of the video data of the subsequent line are in the same order. And read out the video data of the preceding line. On the other hand,
An image processing apparatus comprising: a control unit that controls the writing of the video data of the subsequent line to be delayed for a predetermined time. 3. The control unit, the control signal generating means for generating a control signal which is inverted in a vertical cycle or a horizontal cycle based on the vertical synchronization signal or the horizontal synchronization signal, and the field controlled by the control signal. 3. The image processing apparatus according to claim 1, further comprising a selection unit that selects an initial value of a read address of the memory or the line memory. 4. A control signal generating means for generating a control signal which is inverted every vertical cycle or horizontal cycle based on the vertical synchronizing signal or the horizontal synchronizing signal, and the control section being controlled by the control signal. 3. The image processing apparatus according to claim 1, further comprising a selecting unit that selects an initial value of a write address of the field memory or the line memory.