JP3465386B2 - Frame synchronization circuit and encoding / decoding processing circuit using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit and a decoding processing circuit having the same circuit.

In recent years, the processing speed in computer systems, exchanges, or transmission processing terminal stations has been increasing day by day, and the signal interface speed between boards and devices has been increasing day by day, and the transmission distance has also been increased by the arrangement of the devices. To respond flexibly to, there is a tendency to increase. Therefore, it is necessary to realize an interface capable of transmitting a large number of signals in parallel over a long distance.

[0003]

2. Description of the Related Art FIG. 15 is an explanatory view of a conventional example, (a) is a configuration diagram, and (b) is an operation explanation diagram. As described above, as the interface speed between the board and the device is increased day by day, a coding / decoding processing circuit capable of efficiently transmitting parallel high-speed digital signals over a relatively long distance is provided. Realization is an important issue. In particular, when the information to be transmitted is an image signal, a data signal, or the like, a slight deterioration in the transmission quality of the transmission / reception circuit including the encoding / decoding processing circuit is perceived by the user as a clear error. An extremely low error rate is required for the entire circuit.

In order to solve such problems and realize a highly reliable and economical encoding / decoding processing circuit, efficient encoding should be performed in the encoding processing circuit, and in the decoding processing circuit. It is necessary to realize a frame synchronization circuit that has a fast synchronization recovery time and does not cause pseudo synchronization or loss of synchronization.

For example, when transmitting parallel data in a lump, the data obtained by multiplexing the parallel data is exchanged for each channel for encoding, and the transmission line mark ratio during burst data transmission is halved. Therefore, the method of scrambling the input data, the method of suppressing the same code by inserting the logical inversion code of the immediately preceding bit as an auxiliary bit, the frame synchronization method by the frame bit detection, the synchronization protection method that monitors the code error of the frame bit, etc. Is proposed.

However, the 1-bit delay shift system is often used as the frame synchronization circuit. As shown in FIG. 15, this system is composed of a frame comparison / detection portion 81, a synchronization protection portion 82, and a control portion 83, and the frame pulse generated in the control portion and the input data are compared in the frame comparison / detection portion. Here, it is assumed that the frame pulses are dispersed in the data at equal intervals.

Then, when a certain frame pulse is compared with the data, if the codes match, the frame pulse is detected and the synchronization protection state is entered. However, when the codes do not match, the frame pulse is delayed by (1 bit + 1 frame) and compared with the data, but when the codes do not match, the frame pulse is further delayed (1 bit + 1 frame). Then, this delay is repeated until they match.

[0008]

[Problems to be Solved by the Invention] FIG. 16 is a diagram for explaining the problems.
(a) is the case where pseudo synchronization occurs, and (b) is the case where false synchronization occurs at the time of data slip.

Here, in the frame synchronization method as described above, (1) depending on the pattern (burst data, etc.) of the input digital signal, the frame bit pattern may be mistakenly recognized in the decoding processing circuit when the system is started up. Pseudo-sync can occur.

For example, as shown in FIG. 16 (a), a frame bit pattern in which "1" and "0" alternate in the input data (F1 in the figure is "1" and F0 is "0") Are distributed and inserted, and if data of the same pattern exists, pseudo synchronization occurs. (2) After synchronization is established, missynchronization may occur when transmission data slips back and forth.

As shown in FIG. 16 (b), it is assumed that the decoding processing circuit normally synchronizes the frame even if the data having the same pattern as the frame bit pattern is adjacent to the frame bit pattern. , See). However, if the data slips for some reason (for example, the temperature change of the transmission line), erroneous operation occurs.
(See,). (3) The synchronization recovery time becomes longer according to the frame length, which is disadvantageous in terms of maintainability and reliability. (4) When transmitting burst data, the encoding processing unit scrambles the data. The scramble process is performed by taking the exclusive OR of the scramble pattern generated by the scrambler in the circuit and the transmission data.

At this time, the pattern length of the scramble pattern is determined by the number of stages of the scrambler in the circuit, but this length is often different from the frame length. In the system, the scramble pattern is reset at a cycle corresponding to one frame length in order to define the mark ratio per one frame length.

In the case of a parallel data transmission line, the relationship between the scramble pattern and the reset position is different for each channel due to the circuit configuration, and the variation in mark ratio between channels is large. For example, when used in combination with an optical transceiver,
This adversely affects the characteristics of the optical / electrical conversion unit that detects the average value.

An object of the present invention is to provide an optimized frame synchronization circuit and a decoding processing circuit using this circuit.

[0015]

According to a first aspect of the present invention, there is provided auxiliary bit detecting means for detecting an auxiliary bit from input coded data in which a frame synchronizing circuit inserts an auxiliary bit and a frame bit, and transmitting a detection output. , Using the detection output,
It is configured to have a frame synchronization detecting means for detecting a frame bit from the input encoded data.

In the second aspect of the present invention, auxiliary bits and frame bits having a constant cycle are inserted in the encoded data. In the third aspect of the present invention, the cycle of the frame bit is set to be an integral multiple of the auxiliary bit insertion cycle.

In the fourth aspect of the present invention, the auxiliary bit is replaced at the frame bit insertion period. In the fifth aspect of the present invention, an alarm is sent out in an asynchronous state.

The sixth aspect of the present invention is provided with a descrambler section that takes the exclusive OR of the data for which frame synchronization is established and the PN pattern. In the seventh aspect of the present invention, the descrambler unit is set / reset by the frame information output from the frame synchronization detecting unit.

The eighth and ninth aspects of the present invention are provided with an auxiliary bit detecting means having a comparing section and a receiving side controlling section, and a frame synchronizing detecting section having a frame synchronizing detecting section, a synchronizing protecting section and a descrambler, and the frame synchronizing means is provided. The detection unit is configured to detect the frame bit by using the output of the reception side control unit and establish frame synchronization.

In the tenth aspect of the present invention, the exclusive OR output is "0".
If the sign when the exclusive OR output becomes "0" at the place where the n-bit counter becomes "0" is not recognized as the auxiliary bit, set the 2-bit counter to "0" and hunt the auxiliary bit. To start.

The eleventh aspect of the present invention is configured to return to the re-hunting state when a code error of an auxiliary bit is detected even after frame synchronization is established. In the twelfth aspect of the present invention, the synchronization protection unit simultaneously performs auxiliary bit synchronization protection and frame bit synchronization protection to avoid false synchronization at the time of pseudo synchronization or data slip.

In the thirteenth aspect of the present invention, among the encoded data of a plurality of channels, one channel is used as a master and the other channels are used as slaves, and the frame bit information from the frame synchronization circuit of the master is used to establish the frame synchronization of the slaves. I made it up.

In the fourteenth aspect of the present invention, the frame synchronization section of the slave is provided with a scualine function. 15th
According to the present invention, in a coding processing circuit having a scrambler section, a coding processing section, a transmission side control section, a frame synchronization section, and a decoding processing circuit having a decoding processing section, the frame length and the reset length of the PN pattern are set. It has a configurable configuration.

In the sixteenth aspect of the present invention, the n-bit counter provided in the transmission side control unit and the reception side control unit is replaced with a 2 ^K-1 bit counter. In a seventeenth aspect of the present invention, in the optical receiver, the receiving side control unit is provided with a 2 ^K-1 bit counter, and the frame length and the PN pattern reset length can be set.

[0025]

1 is an example of a block diagram of a main part of a frame synchronization circuit of the present invention and an encoding / decoding processing circuit using the same, and FIG. 2 is a flow chart for explaining the operation of the frame synchronization circuit in FIG. is there.

Hereinafter, FIGS. 1 and 2 will be described. First, Fig. 1
The scrambler unit 1 in the inside comprises a PN pattern generating circuit and a gate circuit, and takes an exclusive OR of the PN pattern output from the PN pattern generating circuit and the input digital signal.

The encoding processing unit 2 inserts auxiliary bits and frame bits into the data scrambled by the scrambler unit, and performs mB1C encoding. Transmission side control unit 3
Sets / resets the built-in (m + 1) bit counter, n-bit counter, and 2-bit counter (not shown).

The comparator 41 compares the i-th and (i + 1) -th encoded data input from the digital transmission line to detect an auxiliary bit. The reception side control unit 42 includes a built-in (m + 1) bit counter, an n-bit counter (CNT _n ),
Set / reset the 2-bit counter (CNT ₂ ).

The frame synchronization detection unit 43 generates the output timing of the frame bit and the frame information, the set / reset information of the descrambler unit, and the frame protection information.

The synchronization protection unit 44 performs frame synchronization protection and outputs a frame synchronization alarm. The descrambler unit 5 is composed of a PN pattern generating circuit and a gate circuit (not shown), takes the exclusive OR of the PN pattern output from the PN pattern generating circuit and the frame-synchronized data, and scrambles the scrambled data. Restore the original digital signal.

The decoding processing unit 6 deletes auxiliary bits and frame bits of encoded data. Here, the auxiliary bit is inserted for each (m + 1) bit, and its code is the inversion of the immediately preceding bit. The frame bit is inserted on the auxiliary bit as a 1,0 alternation once in [(m + 1) × n] bits.

Next, mB1C from the encoding processing circuit of FIG.
When the encoded data is input to the decoding processing circuit, the auxiliary bit (C
Bit) and frame bit (F bit) are detected. That is, the 1.2-bit counter (CNT ₂ ) is set to 0 (see S1). 2. In the comparison unit 41, the exclusive OR of the i-th and (i + 1) -th data is taken, and the result is "1" for the first time.
Recognized as C bit (see S2).

At this time, the (m + 1) -bit counter and the n-bit counter of the control section on the receiving side are reset (see S3). If not "1", repeat until "1" (C bit hunting). 3. When the (m + 1) bit counter is "0" (see S4 Y),
If the exclusive OR (S5) of the i-th and (i + 1) th is "1", it is regarded as a C bit (see Y in S5), and the n-bit counter is incremented by 1 (see S6).

CNT _n ++ increments the counter of the n-bit counter by 1. 4. When the (m + 1) bit counter is "0" (see S4 Y)),
If the exclusive OR of the i-th and (i + 1) -th is "0" (S
N) of 5 and not C bit, but there is a possibility of F bit, so start searching C bit from this.

At this time, if the 2-bit counter is 0 (S8
Reset the n-bit counter and set the 2-bit counter to "1" (see S9). The fact that the 2-bit counter is set to "1" means that the F bit is being detected.

If the 2-bit counter is 1, and the n-bit counter is "0" (see Y in S10), the (m + 1) -bit counter in S7 is incremented and a loop with S4 is performed. However, if the n-bit counter is not 0 (see N in S10),
Enter C-bit rehunting. 5. Here, if the sign of the detected bit (i + 1st bit at S5) is "0", the sign of the detected bit at the next n-bit counter becomes "0". If is "1", this bit is recognized as F bit.

After that, if no code error is detected, F
The synchronization is established after 2r times of bits, ie after r stages of backward protection. 6. However, if the sign of the detected bit is "0",
It is not recognized as the F bit, and it is determined in S5 whether it is the C bit.

If it is determined to be C bits, the n-bit counter is incremented by 1 (see S6), and if not determined, the 2-bit counter is set to "0" (see S1), and the C bit rehunting is started.

That is, in the above hunting process, since the C bit is always detected, re-hunting can be performed immediately without waiting for the F bit code error when the encoded data is erroneously burst. it can.

After the frame synchronization is established, the C bit is monitored, and if a C bit code error is detected, the re-hunting state is restored regardless of whether the F bit code is correct or incorrect.
By detecting the C bit in this way, the time until rehunting is shorter than the detection of only the F bit, so that the synchronization recovery time can be shortened.

Further, since the synchronization protection unit simultaneously performs the C-bit synchronization protection and the F-bit synchronization protection, it is possible to avoid pseudo synchronization due to the pseudo synchronization pattern and erroneous synchronization at the time of data slip.

Further, in the transmission side control unit and the reception side control unit, the n bit counter is set to 2 ^K-1 bit counter (K = 1,
2, 3 ...), the value of K can be set arbitrarily, so the circuit configuration of the counter part can be simplified and the frame length and PN pattern reset length can be changed to avoid the occurrence of pseudo sync patterns. Thus, it is possible to make the transmission line mark ratio constant during burst data transmission.

Further, in the parallel data transmission line, it is possible to reduce the variation between channels.

[0044]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is an example of a frame synchronization circuit configuration diagram in FIG. 1, FIG. 4 is an operation explanatory diagram (No. 1) of FIG. 3, FIG. 5 is an operation explanatory diagram (No. 2) of FIG. 3, and FIG. 8 is a block diagram showing the main part of an encoding processing circuit according to an embodiment of the present invention, FIG.
9 is a block diagram of the main part of the decoding processing circuit according to the embodiment of the present invention.
Is a block diagram of the slave side frame synchronization circuit in FIG.
9 is an operation explanatory diagram of the delay circuit in FIG. 9, FIG. 11 is an operation explanatory diagram of FIG. 8, FIG. 12 is a diagram showing another example of the decoding processing circuit of the embodiment of the present invention, and FIG. 13 is an implementation of the present invention. FIG. 14 is a diagram showing still another example of the decoding circuit of the example, and FIG. 14 is a configuration diagram of a main part when the present invention is applied to an optical transmission device.

The same reference numerals denote the same objects throughout the drawings. Hereinafter, mB1C encoding will be referred to as 19B1C encoding as shown in FIG.
~ The description of FIG. 14 will be given. First, the operation of the frame synchronization circuit shown in FIG. 3 until the synchronization is established will be described with reference to FIGS. 1, 4 and 5.

As shown in FIG. 1, the encoding processing circuit is composed of a scrambler unit 1, an encoding processing unit 2 and a transmission side control unit 3. From this circuit, 19B1C encoded data is sent to a frame synchronization circuit 4, The 19B1C encoded data is input to the frame synchronization circuit because it is sent to the decoding processing circuit configured by the descrambler unit 5 and the decoding processing unit 6 (see FIG. 4 (a)).
. The (m + 1) -bit counter and n-bit counter in FIG. 2 correspond to the 20-bit counter and 8-bit counter in FIG.

On the other hand, the frame synchronization circuit shown in FIG. 3 starts hunting when the input reset (b) becomes "H" (see FIG. 4 (b)), and the comparing unit 41 determines that the i-th data of the encoded data ( The exclusive OR with the i + 1) th (hereinafter abbreviated as EX-0R) is taken, and the place where the result becomes "1" for the first time is C
Recognized as a bit (auxiliary bit), EX-OR inversion (k) and 1
Output the bit shift (L) (see Fig. 4 (k) and (L)).

At this time, the 20-bit counter (c) and 8-bit counter (d) of the receiving side control unit 42 are reset (see FIG. 4).
(See (c) and (d)). 20-bit counter information (f) is sent to 8-bit counter (d) and 2-bit counter (e),
The bit counter information (g) is sent to the 2-bit counter.

When the 20-bit counter is "0", i
EX-OR between the 1st bit and the (i + 1) th bit is "1"
If so, it is regarded as C bit and the count value of the 8-bit counter (d) is incremented by 1.

If the EX-OR of the i-th bit and the (i + 1) -th bit is "0" when the 20-bit counter is "0", it is possible that it is not the C bit but the F bit. Therefore, we will start looking for the C bit from this (see Figure 4 (a)).
.

At this time, the 8-bit counter is reset (see FIG. 4 (d)) and the 2-bit counter (e) is set to "1" (see FIG. 4 (e)). When the 2-bit counter is "1", it indicates that the F bit is being detected.

Next, when the 20-bit counter becomes "0",
The EX-OR between the i-th bit and the (i + 1) -th bit is "
If it becomes 0 ", the C bit becomes erroneous and the C
Bit re-hunting begins (see Figure 4 (a))
.

Here, it is assumed that the re-hunting state is entered as described above, and the state transits to the states shown in FIGS. 4 (c) and 4 (d) again. If the sign of the bit detected in the state is "0", then if the sign of the bit detected at the place where the 8-bit counter becomes "0" is "1", this bit is regarded as the F bit. recognize.

After that, if no code error is detected,
Synchronization is established after four F-bits, that is, after the rear two stages.
(See Figure 5 (a)). When synchronization is established, an alarm
(m) becomes "L" (see A in Fig. 5 (m)), and descrambler reset information (h), frame information (i), and frame bit information (j) are output (see B in Fig. 5). .

However, if the sign of the bit detected at the place where the 8-bit counter becomes "0" is "0", it is not recognized as the F bit and it is judged whether it is the C bit or not. Where C
If it is determined to be a bit, the 8-bit counter is incremented by 1, and if not determined, the 2-bit counter is set to "0" and the C bit re-hunting is started.

By detecting the C bit in this way, the time until rehunting is shorter than the detection of only the F bit, so that the synchronization recovery time can be shortened. In the hunting process, the synchronization protection unit 44 simultaneously performs the C-bit synchronization protection and the frame-bit synchronization protection (backward protection), so that it is possible to avoid the pseudo synchronization due to the pseudo synchronization pattern.

Further, after the synchronization is established, the C bit is monitored,
You can perform synchronization protection (forward protection). Forward protection of C bits is 1 in C bits existing within one frame length.
If an error is found even in an individual, it will be counted as one step. The number of protection steps is 2
In the round stage, if a C-bit error is detected in two consecutive frames, re-hunting occurs. This protection makes it possible to avoid false synchronization during data slips.

6 to 11, FIG. 6 is the transmitting side, and FIG.
On the receiving side, 11 in FIG. 6 is a parallel / serial conversion unit, 12, 61 are data swap units, 4a is a master frame synchronization unit, 4b is a slave frame synchronization unit, and 62 is a serial / parallel conversion unit. .

Although the circuit configuration for single-channel data input has been described above, the encoding processing circuit shown in FIG. 6 outputs 20 pieces of parallel input data (one of which is for F / C bit insertion). The data is swapped after the data is converted into 5 series data by multiplexing four by one in the parallel / serial conversion unit 11.
As shown in FIG. 7, 5 series of data are sequentially switched between the series in units of 4 bits (corresponding to 4 pieces of parallel input data) and sent to the scrambler unit 13.

The scrambler unit 13 takes the EX-OR of the five data and the PN pattern, and the F / C bit insertion unit 21 inserts the C bit for every 20 bits and the F bit for every 160 bits to obtain 19B1C. Output as encoded data.

On the other hand, in the decoding processing circuit shown in FIG. 8, one of the five pieces of 19B1C encoded data is used as a master and the remaining four are used as slaves, and the frame synchronization circuit 4a of the master is used.
After synchronizing the frame by using the method described above in 1., the master synchronization information (F flag and F bit information)
To the frame synchronization circuit 4b of each slave.

Therefore, the slave frame synchronization circuit uses the input synchronization information to establish frame synchronization. The slave frame synchronization method will be described with reference to FIGS. 9 and 10.

First, the delay circuit of FIG. 9 (as shown in FIG.
For example, it is composed of 5 stages of shift register) 41b
Delays input data by ± 2 bits, -2 bits,
-1 bit, ± 0 bit, +1 bit, +2 bit delay data, that is, a total of 5 series of data are prepared. In the receiving side control unit 45b, when the F bit information from the master is input, a select signal is generated based on it and the selector unit is generated.
Send to 42b.

As shown in FIG. 10, the selector section compares the delay data selected by the select signal with the F flag sent from the master. If the comparison results do not match, the next delay data is selected, and if they match, the matched select data is output.

Therefore, each slave can eliminate the skew up to ± 2 bits with respect to the master. Since this method starts hunting by multiple slaves at the same time after the master synchronization is established, the synchronization recovery time is short and the circuit scale is small compared to the master.

Now, after the frame synchronization is performed by the above method, each sequence is synchronized with the synchronization data by the descrambler unit 5 in FIG.
EX-OR with the PN pattern and take the data swap section 61
Replace the data between series as shown in 11, and
/ Parallel conversion unit 62 separates each series into four parallel data.

[0067] Incidentally, as shown in FIG. 12, sends the synchronization information of the master to the slave 4b _1, after establishing synchronization at the slave 4b _1, sequentially and so called sending this synchronization information to the slave 4b _2, the synchronization You may make it the composition taken. Also, in FIG.
As shown in FIG. 5, all encoded data sequences may be used as masters to individually perform frame synchronization.

Here, when transmitting the burst data, the data is scrambled by the encoding processing circuit shown in FIG. The scramble process is performed by taking the EX-OR of the scramble pattern generated by the scrambler in the circuit and the transmission data.

At this time, the pattern length of the scramble pattern is determined by the number of stages of the scrambler in the circuit, but this length is often different from the frame length. On the other hand, in the system, the scramble pattern is reset at a cycle corresponding to one frame length in order to define the mark ratio per one frame length.

In the case of parallel data transmission, the conventional problem is that the relationship between the scramble pattern and the reset position differs from channel to channel due to the circuit configuration, and the mark ratio varies among channels. If the mark ratio of the pattern is changed slightly, PN per frame length
The mark ratio of the pattern changes slightly.

If this change amount is known in advance, when the transmission line mark ratio changes and deviates from 0.5, it can be corrected by the amount of the deviation. Therefore, in the parallel data transmission path, it is possible to reduce the variation in the mark ratio between the channels.

When the reset length of the PN pattern is equal to or longer than the frame length and is an integral multiple of the frame length, a pseudo sync pattern may occur. At this time, the 2 ^K-1 bit counter control unit (not shown) controls the 2 ^K-1 bit counter to change the PN pattern and the reset length so that pseudo synchronization does not occur.

FIG. 14 is a block diagram of the essential parts when the frame synchronization circuit of the present invention described in detail above is used in an optical transmission device. As shown in the figure, in an optical receiver in which an optical receiving section having a photo diode (PD), a preamplifier, a reference circuit, and an optical / electrical converting section composed of a limiter amplifier, and the above decoding processing circuit are combined. , The frame length and the reset length of the PN pattern in the descrambler are set to 2 ^K-1 bit counter, and the mark ratio of the transmission path can be changed by controlling the value of K. Here, K is 1,2,3 ....

A reference circuit is used in the light receiving section, and the reference circuit detects the light receiving level. At this time, if the reference circuit detects the average value, the condition that the transmission line mark ratio is always 0.5 is a stable operation condition.

However, the mark ratio of the transmission path data is slightly deviated from 0.5 depending on the mark ratio of the data itself and the appearance pattern even if scramble processing is performed. This causes deterioration of the characteristics of the reference circuit (average value detection circuit).

Therefore, by changing the reset length of the PN pattern generated in the scrambler unit in the transmission unit and the PN pattern generation unit in the descrambler in the reception unit, or by changing the frame length, the transmission line mark ratio is 0.5. Can be subtly changed.

As a result, when the mark ratio of the data itself changes and the transmission line mark ratio deviates from 0.5, it can be corrected so as to approach 0.5. That is, according to the present invention, the synchronization recovery time is shortened, false synchronization and erroneous synchronization at the time of data slip are avoided, the transmission line mark ratio is changed, and variation between channels during parallel transmission is suppressed. Data transmission is performed at a mark ratio that is optimal for the optical receiver's capability when applied to an optical transmission system, and the deterioration of average value detection characteristics in the optical / electrical converter is prevented.
By using a 2 ^K-1 bit counter as the bit counter, the circuit configuration can be simplified, and it greatly contributes to the performance improvement of the encoding / decoding processing device.

[0078]

As described in detail above, according to the present invention,
There is an effect that it is possible to provide an optimized frame synchronization circuit and an encoding / decoding processing circuit using the same.

[Brief description of drawings]

FIG. 1 is an example of a configuration diagram of a main part of a frame synchronization circuit of the present invention and an encoding / decoding processing circuit using the same.

2 is a flowchart for explaining the operation of the frame synchronization circuit in FIG.

FIG. 3 is an example of a frame synchronization circuit configuration diagram in FIG. 1.

FIG. 4 is an operation explanatory diagram (1) of FIG. 3;

FIG. 5 is an operation explanatory diagram (2) of FIG. 3;

FIG. 6 is a main part configuration diagram of an encoding processing circuit according to an embodiment of the present invention.

FIG. 7 is an operation explanatory diagram of FIG. 6;

FIG. 8 is a configuration diagram of a main part of a decoding processing circuit according to an embodiment of the present invention.

9 is a configuration diagram of a slave side frame synchronization circuit in FIG.

10 is an explanatory diagram of the operation of the delay circuit in FIG.

11 is an explanatory diagram of the operation of FIG.

FIG. 12 is a diagram showing another example of the decoding processing circuit according to the embodiment of the present invention.

FIG. 13 is a diagram showing still another example of the decoding circuit according to the exemplary embodiment of the present invention.

FIG. 14 is a configuration diagram of a main part when the present invention is applied to an optical transmission device.

15A and 15B are explanatory views of a conventional example, where FIG. 15A is a configuration diagram and FIG. 15B is an operation explanatory diagram.

FIG. 16 is an explanatory diagram of a problem, where (a) is a case where pseudo synchronization occurs,
(b) is the case of erroneous synchronization at the time of data slip.

[Explanation of symbols]

1 Scrambler 2 Encoding Processor 3 Transmitter Control 4 Frame Synchronization Circuit 5 Descrambler 6 Decoding Processor 11 Parallel / Serial Converter 12 Data Swap (Sender) 41 Comparator 42 Receiver Control 43 Frame sync detection block 44 Sync protection block 61 Data swap block (reception side) 62 Serial
/ Parallel converter

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-58-97937 (JP, A) JP-A-5-3473 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 7/08 H04L 7/00

Claims (3)

(57) [Claims] 1. An auxiliary bit detecting means for detecting an auxiliary bit from input coded data in which an auxiliary bit and a frame bit are inserted and transmitting a detection output, and utilizing the detection output, the input coded data In a frame synchronization circuit characterized by comprising frame synchronization detection means for detecting frame bits, the auxiliary bit detection means is the i-th and (i
Comparing unit for detecting the auxiliary bit by comparing +1) th, and (m + 1) -bit counter for counting the auxiliary bit insertion period , which is set / reset corresponding to the detection state of the auxiliary bit , the (m + 1) bit In cooperation with the counter, (m +
1) Check the frame bit insertion period in × n bit period.
N-bit counter to count, the (m + 1) Bittokau
And hunting in cooperation with the n-bit counter.
Has 2-bit counter that controls the, the two Bittoka
The counter outputs the output of the comparison unit and the (m + 1) -bit counter.
The output of the n-bit counter and the (m +
1) The bit counter outputs the output of the comparison unit and the n-bit counter.
The bit counter outputs the output of the comparison unit and the (m + 1) bit.
Output of the output counter and each of the two
A bit counter, a reception side control unit for sending the output of the n-bit counter to a necessary portion as a control signal, and the frame synchronization detection means uses the control signal to output data, frame bits, and frames from input encoded data. Information, synchronization protection information and descrambler set / reset information generation / transmission frame synchronization detection unit, when synchronization protection is lost using frame bits, frame information and synchronization protection information from the frame synchronization detection unit It is characterized in that it has a sync protector for sending out an alarm and a descrambler, and that the frame sync detector is configured to detect a frame bit using the output of the receiving side controller to establish frame synchronization. And a frame synchronization circuit. Wherein among the encoded data of a plurality of channels to be input, one channel master, the other channel as slave, the frame synchronization detection unit of the master is composed of a frame synchronization circuit according to claim 1 , The frame bit information from the frame synchronization circuit of the master is sent to the frame synchronization unit of the slave channel composed of the synchronization protection unit, control unit, and gate circuit unit, and the input frame bit information matches the frame bit. / A frame synchronization circuit characterized by being configured to establish frame synchronization of a slave by detecting a mismatch. 3. A coding process for generating a PN pattern and performing an exclusive OR of an input digital signal and a PN pattern, and an encoding process for inserting auxiliary bits and frame bits into the digital signal. and parts, m +1 bit counter, n-bit counter, and coding processing circuit and a transmitting-side control unit that performs a set / reset the 2-bit counter, a frame synchronization circuit according to claim 1 or claim 2, A decoding processing circuit having a decoding processing unit for decoding synchronized digital signals, characterized in that the frame length and the reset length of the PN pattern are settable. circuit.