JP3463242B2 - Data processing circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing circuit for battery backup of SDRAM, and more particularly to a data processing circuit for protecting backup data of SDRAM when main power is turned on.

[0002]

2. Description of the Related Art In recent years, SDR has been used as a memory for data processing circuits.
AM (synchronous DRAM) has come to be used. SDRAM is a microprocessor unit (MP
U /) performs a read / write operation in synchronism with a clock, and data can be transferred at a higher speed than a conventional DRAM. SDRAM is a conventional DRA
In addition to being refreshed by a refresh command with addressing from the MPU, which is also performed in M,
It is possible to perform internal refresh without relying on an external signal such as a refresh command from the MPU. The operation in such a refresh system is called a self-refresh mode. For example, if MPU is SDRAM for a long time
When the SDRAM is in the idle state where reading and writing are not performed, the SDRAM is switched to the self refresh mode.

On the other hand, the MPU that controls the SDRAM is
By incorporating the interface for SDRAM,
There is one configured so that the SDRAM can be directly connected.

In the data processing circuit using the SDRAM, when the MPU is in the idle state, a command for instructing the SDRAM to perform self refresh is issued.
Specifically, chip select (CS), row address strobe (RAS), column address strobe (CA)
The clock enable signal output from the hardware of the MPU becomes L level while S) and the write enable (WE) have a predetermined logical value. The clock enable signal is directly connected to the SDRAM, and the SDRAM to which the clock enable signal is input at the L level operates in the self refresh mode. When the MPU is activated, a command for instructing the SDRAM to cancel self refresh is issued. Specifically, MPU
The clock enable signal output by the signal changes from L level to H level. The SDRAM to which the clock enable signal is input at the H level shifts to the normal refresh mode.

Such a data processing circuit has an advantage that power consumption can be suppressed when it is not used for a long time.

[0006]

Some data processing circuits are provided with a battery backup in order to retain the data in the memory even when the main power supply is turned off. Therefore, if a battery backup is introduced into the data processing circuit using the SDRAM described above, the following operation logic can be considered.

When the main power supply is turned off and the battery backup is started, the MPU issues a self-refresh entry command to the SDRAM, and thereafter the SDRAM maintains the self-refresh mode during the battery backup. When the main power supply is turned on and the MPU is activated, the MPU issues a self-refresh cancel command to the SDRAM and shifts to the normal refresh mode.

When the main power source is turned on, the MPU is power-on reset. The MPU issues a self-refresh cancellation command immediately after the power-on reset (M
PU hardware raises the clock enable signal to H level). As a result, the SDRAM is released from the self-refresh mode and refreshed in response to the refresh command from the MPU. On the other hand, immediately after the power-on reset, the MPU needs to perform an initialization process for setting the states of internal registers and input / output (I / O) ports by software. The MPU can issue the refresh command only after the initialization process is completed.
Therefore, the refresh command is issued after the initialization process is completed.

In the above operation logic, the initialization process usually requires 200 to 300 msec. However, data cannot be guaranteed in the SDRAM unless it is refreshed within 16 msec. SDR that released self-refresh mode immediately after power-on reset
Since the AM is not refreshed until the MPU initialization processing is completed, data will be lost.

As described above, the conventional data processing circuit using the SDRAM is well compatible with the operation of stopping the MPU without turning on / off the main power source, but the main power source when the memory is backed up by a battery is used. It cannot be turned on / off, and the data held by the battery backup will be lost when the main power is turned on.

Therefore, an object of the present invention is to solve the above problems and to provide a data processing circuit for protecting the backup data of the SDRAM when the main power is turned on.

[0012]

In order to achieve the above object, the present invention relates to a data processing circuit for backing up an SDRAM holding data by a battery, a clock enable signal output from the MPU immediately after a power-on reset, and the MPU. Based on the initialization processing end signal indicating that the initialization processing in (3) has been completed, the SDRAM is instructed to cancel the self-refresh.

The initializing process end signal is the MP that becomes high impedance during power-on reset.
The I / O port terminal of U may be pulled up or pulled down to a voltage of a negative logic level, and an affirmative logic level may be output from this I / O port to indicate that the initialization process is completed.

The clock enable signal from the clock enable signal output terminal of the MPU is logically ANDed with the initialization processing end signal, and this logical AND signal is added to the S signal.
It may be given to the clock enable signal input terminal of the DRAM.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

A data processing circuit according to the present invention comprises a battery-backed SDRAM 1 and an MPU 2 incorporating an SDRAM interface. The main power source of this data processing circuit is commercial 100V. here,
Turning on / off the main power source means cutting off commercial 100V and bringing the interrupted commercial 100V into conduction.
This is different from the apparent on / off due to the transition of the idle state / active state in which the MPU 2 is not reset. DC constant voltage V converted from commercial 100V when the main power supply is on
_S is applied to all data processing circuits. When the main power supply is off, the DC constant voltage V _S disappears, but the backup voltage V _B by the battery is switched and applied to the module to be backed up such as the SDRAM 1.

This data processing circuit has a constant DC voltage V _S
A reset module 3 is provided which outputs a reset signal for a certain period in response to rising of the voltage to a specified voltage. This reset signal is input to the reset terminal r of the MPU 2 and is used for power-on reset of the MPU 2. In addition, this data processing circuit is provided with a power supply monitoring module 4 that monitors commercial 100 V or a constant DC voltage V _S to quickly detect power-off. The power-off detection signal is input to the interrupt terminal i of the MPU 2 and is used to cause the MPU 2 to interrupt the power-off process.

The MPU 2 is provided with a clock enable signal output terminal c. In the command in which the MPU 2 instructs the SDRAM 1 to cancel self-refresh, the clock enable signal becomes H level, and SD
In the command for instructing the RAM 1 to perform self-refresh entry, the clock enable signal becomes L level. Further, the MPU 2 is provided with an I / O port terminal p used for an I / O port. The I / O port is for inputting / outputting signals by software commands. In the present invention, the initialization processing end signal indicating that the initialization processing in the MPU 2 is completed is output from this I / O port. The initialization processing end signal indicates the end of the initialization processing at the H level. Although not shown, inside the MPU 2, the I / O port terminal p has a configuration that becomes high impedance during power-on reset. Therefore, I /
The O port terminal pulls down the pull-down resistor 5 so that it does not become the positive logic level H level during the power-on reset.
Is pulled down to the voltage of L level (ground potential) via.

A logic module 6 to which a clock enable signal and an initialization processing end signal are input is provided between the MPU 2 and the SDRAM 1. Since the clock enable signal is at the H level and the initialization processing end signal is also at the H level to indicate the end of the initialization processing in the self refresh cancellation command, the logic module 6 can be realized by an AND circuit. The output of the logic module 6 is input to the clock enable signal input terminal cx of the SDRAM 1. The AND circuit is also backed up by the backup voltage V _B.

FIG. 2 shows another form of signal output of the MPU 2. Here, the initialization processing end signal output from the MPU 2 indicates the end of the initialization processing at the L level. Therefore, the I / O port terminal p is pulled up to the H level voltage (backup voltage V _B ) via the pull-up resistor 7 so as not to be the L level which is a positive logic when the power is off. In order to match the logic with the clock enable signal, the initialization processing end signal is inverted via the inverter 8. The inverter 8 is also backed up by the backup voltage V _B. This form is I
It may be applied to the MPU in which the / O port terminal p becomes H level during the power-on reset.

The operation of the data processing circuit according to the present invention will be described below.

First, when the main power supply is off, as shown in FIG. 3, the power supply monitoring module 4 promptly detects the power supply off and lowers the interrupt signal (the signal at the interrupt terminal i of the MPU 2). The MPU 2 preferentially starts the power-off process by an interrupt, and sets the initialization process end signal (signal of the I / O port terminal p) to a negative logic level (L level) as a part of the power-off process. As a result, the input of the clock enable signal input terminal cx of the SDRAM 1 becomes L level, and the SDRAM 1 shifts to the self refresh mode. This operation ends before the reset signal (signal of the reset terminal r) due to power off falls. Since the input of the logic module 6 is pulled down even after the MPU 2 stops operating, the clock enable signal input terminal c of the SDRAM 1
x is fixed to the L level.

Next, when the main power supply is turned on, the reset module 3 outputs a reset signal (a signal at the reset terminal r) for a certain period, as shown in FIG. MPU2
Issues a command for canceling self-refresh immediately after the power-on reset (the hardware of the MPU raises the clock enable signal output terminal c to the H level). At this point, the I / O port terminal p has a high impedance inside the MPU, but is pulled down to the L level via the pull-down resistor 5. After the power-on reset, the MPU 2 uses software to perform an initialization process for setting the states of internal registers and I / O ports. At the end of this initialization processing, the I / O port terminal p indicating the end of the initialization processing is changed to H level. Since the clock enable signal output terminal c of the MPU 2 is already at the H level, SDRA
The clock enable signal input terminal cx of M1 rises to the H level, and the SDRAM 1 cancels the self refresh mode. At this point, since the MPU 2 has completed the initialization process, it is possible to issue a refresh command to the SDRAM 1 at any time.

In this way, the SDRAM 1 maintains the self-refresh mode until the initialization processing of the MPU 2 is completed, so that the backup data of the SDRAM 1 can be protected.

[0025]

The present invention exhibits the following excellent effects.

(1) At power-on reset, SDRAM is initialized until the initialization process in MPU is completed.
In addition, the self-refresh mode is not released and data loss is prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of a data processing circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a main part of a data processing circuit according to an embodiment of the present invention.

FIG. 3 is a signal timing diagram when the main power supply is off in the data processing circuit of FIG.

FIG. 4 is a signal timing diagram when the main power supply is turned on in the data processing circuit of FIG.

[Explanation of symbols]

1 SDRAM 2 MPU 3 reset module 4 Power supply monitoring module 5 pull-down resistors 6 logic modules 7 Pull-up resistor

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 11/40-11/4099 G06F 12/00 G06F 12/16

Claims (3)

(57) [Claims] 1. In a data processing circuit for backing up an SDRAM that holds data by a battery, a clock enable signal output by an MPU immediately after a power-on reset and an initialization processing end signal indicating that the initialization processing in the MPU is completed. Based on
A data processing circuit for instructing the SDRAM to cancel self refresh. 2. The initialization processing end signal has a high impedance during the power-on reset.
7. An I / O port terminal of PU is pulled up or pulled down to a voltage of a negative logic level, and a positive logic level is output from this I / O port to indicate that the initialization process is completed. 1. The data processing circuit according to 1. 3. The clock enable signal from the clock enable signal output terminal of the MPU is logically ANDed with the initialization processing end signal, and the AND signal is applied to the clock enable signal input terminal of the SDRAM. The data processing circuit according to claim 1.