JP3459075B2 - Synchronous serial bus method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous serial bus system in which serial data is sent from a master device to a plurality of slave devices and the slave devices that have received the data confirm the reception.

[0002]

2. Description of the Related Art Conventionally, as a synchronous serial bus system,
2-wire I ² C bus system (Flip's), 3-wire I
M-bus system (ITT / Inter Metallic
Company), 4-wire M-bus system (Motorola Co.), etc. are known. The I ² C bus system performs data transmission using two cables that bidirectionally transmit a clock and serial data. In the IM bus system, as shown in FIG. 7, in addition to the clock CLK and the data DATA, the control signal CTR is used to detect the head device address of the instruction code of a plurality of bytes sent from the master device to the slave device.
This is a 3-wire synchronous serial bus system in which a line for transmitting L is added. In this IM bus system, an "END" code is used for an instruction composed of a plurality of bytes to clarify the delimiter for each instruction and prevent the occurrence of malfunction. The M bus system uses four cables, that is, a clock line, two transmission / reception data lines, and a slave select cable. Since the slave device connected to the M bus system determines the device to be accessed (slave) by the slave select signal from the master device, unlike the above-mentioned I ² C bus system and IM bus system, a device address is assigned. No need.

[0003]

Since the I ² C bus system is a two-wire system, the hardware configuration is simple, but all the slave devices connected to this I ² C bus system are individually identified. There is a problem that a number is assigned and a special decoder is required to identify the identification number. In addition, since data is transmitted and received with one data line, the protocol (communication procedure) is complicated and there is a risk of hang-up in the multi-master mode. Note that the hang-up phenomenon in the multi-master mode means a state in which a plurality of CPUs are all waiting in a slave state due to some abnormality. The IM bus system, as described above,
The probability of malfunctions is reduced, but talker (master device)
There is a problem that it is not possible to confirm whether or not the command of (1) is correctly interpreted as a listener (slave device), and it is not to form a multi-master configuration. The M-bus system can have a multi-master configuration, but has a problem that the number of slave selects increases in proportion to the number of master devices and the connection becomes complicated.

[0004]

In order to solve the above-mentioned problems, a single master type synchronous serial bus system as a first embodiment of the present invention comprises one master device and a plurality of master devices.
Slave device is connected via a synchronous serial bus.
The master device takes the initiative in transmission and
Data from a master device to multiple slave devices
-Synchronizing with the clock provided by the device
Slave that wants to receive the data via Albus
The slave device that transmitted the data to the device and received the data
Data received via the serial bus
Validity of data sent back to the device and sent by the master device
Single-master synchronous serial bus to confirm
Is a method, one master device includes a master control unit for controlling the data transmission, and a clock generating means for generating a clock having a data output register, and a data input register, the plurality of slave devices each is set the address to have a slave control means for controlling data transmission, the slave register, a decoder, a buffer, the synchronous serial bus includes a clock transmission line, a plurality of the master device A first data transmission line for serially transmitting data to a slave device, and a second data transmission line for serially transmitting data from one of the plurality of slave devices to the master device,
A control signal transmission line for transmitting a control signal, wherein the master device and the plurality of slave devices include the clock transmission line, the first data transmission line, and the second
Connected via the data transmission line and the control signal transmission line of the master device, the master control means in the master device, when the data transmission to one slave device of the plurality of slave devices, the clock The generating means is energized to generate a clock and send it to the clock transmission line, send a control signal indicating the start of transmission to the control signal line, and send the first data transmission line via the data output register. To the slave device, the function code including information indicating the data transmission to the slave device, the address code of the slave device of the data transmission partner, and the data are sequentially transmitted, and the slave register in the slave device is input via the clock transmission line. Funk input via the first data transmission line in synchronization with the clock If the received address code matches the address of the slave device in the address check in the decoder, the buffer stores the data stored in the slave register as the second data. The data is returned to the master device via a transmission line, and the master control means of the master device outputs the data input via the second data transmission line and held in the data input register, and the data output. It is characterized in that whether or not the data sent to the register for data match is checked. Also, synchronous serial bus method of multimaster system as a second embodiment of the present invention, a plurality of
The master device and multiple slave devices are synchronized
Of the master device and each of the master devices
Has the initiative and can transmit among the master devices
Data from an active master device to multiple slave devices.
Synchronized with the clock provided by the master device capable of transmission
To receive the data via the synchronous serial bus
To the desired slave device and receive the data.
The reverb device receives the data received via the synchronous serial bus.
Data to the master device of the transmission source,
-Multimass to check the validity of the data transmitted by the device
A synchronous serial bus method terpolymers method, the plurality
Each of the master devices includes a master control unit that controls data transmission, a clock generation unit that generates a clock, a data output register, a data input register, and a monitoring circuit that detects a data transmission enabled state. Have,
Wherein each is set the address to the plurality of slave devices has a slave control means for controlling data transmission, the slave register, a decoder, a buffer, before
A synchronous serial bus transmits a clock transmission line, a first data transmission line for serially transmitting data from the master device to a plurality of slave devices, and data from one of the plurality of slave devices to the master device. A second data transmission line for serial transmission, a control signal transmission line for transmitting a control signal, and a bus inhibit signal transmission line for transmitting a bus inhibit signal indicating that the master device is transmitting, The plurality of master devices and the plurality of slave devices include the clock transmission line, the first data transmission line, and the second data transmission line.
Data transmission line, the control signal transmission line and the bus inhibit signal transmission line are connected, the master control means in the master device,
After the bus inhibit signal transmission line is disabled when the bus inhibit signal transmission line is in the usable state, the clock generating means is activated when the data is transmitted to one of the plurality of slave devices. Energize to generate a clock and send it to the clock transmission line, send a control signal indicating the start of transmission to the control signal line, and send the slave device to the first data transmission line via the data output register. A function code including information indicating data transmission to the slave device, an address code of the slave device of the data transmission partner, and data are sequentially transmitted, and the slave register in the slave device is
The function code, address code, and data input via the first data transmission line are held in synchronization with the clock input via the clock transmission line, and received by the address check in the decoder. When the address code matches the address of the slave device, the buffer returns the data held in the slave register to the master device via the second data transmission line, and the master control means of the master device. After checking whether the data input via the second data transmission line and held in the data input register and the data sent to the data output register match, Characterized by enabling the above bus inhibit signal transmission line To.

[0005]

In the single-master type synchronous serial bus system of the first embodiment, the master device outputs the control signal to the control signal transmission line, the clock to the clock transmission line, and the first data transmission line. Device data of the slave device to which serial data should be transmitted and serial data are transmitted, and the plurality of slave devices receive the serial data in response to the transmitted clock, and the data received by the slave device with the same device address is received. Is sent to the master device via the second transmission line. In the multi-master type synchronous serial bus method of the second mode, the master device that performs communication sets the control signal to the control signal after disabling the inhibit signal line when the inhibit signal line indicates the usable state. Output to the transmission line, output the clock to the clock transmission line, and
Of the slave device to which the serial data is transmitted, the device address of the other slave device transmitting the serial data, and the serial data, and the plurality of slave devices respectively receive the serial data in response to the transmitted clock. The slave device having the matched address sends the received data to the source master device via the second transmission line, and the source master device receives the inhibit signal line when receiving the data from the slave device. Ready to use.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the structure of a single master type synchronous serial bus system of a first embodiment of the present invention. In this synchronous serial bus system, the master device 1, the first slave device 3, and the second slave device 4 are connected by four cables 2A to 2D.

FIG. 2 shows a circuit configuration of the master device 1 shown in FIG. In the figure, the master device 1 temporarily outputs data to be sent to a control unit 11 including an arithmetic control unit (CPU), RAM, ROM, etc. (not shown), a clock generator 12 for generating a clock CLK, and slave devices 3, 4. It has a shift register 13 for storing, and a shift register 14 for temporarily storing transmission data from the slave devices 3, 4. The RAM stores the data to be sent to the slave devices 3 and 4, and also stores the data received from the slave devices 3 and 4. ROM is CPU
It stores the program to be operated in. The signal output from the shift register 13 of the master device 1 and input to the slave device via the cable 2A is called a master out signal MOSI (Master-Out / Slave-In), and vice versa. The signal input to the shift register 14 in the master device 1 via the cable 2C is a master-in signal MISO (Master-In / Slave-Ou).
t). Clock C generated by clock generator 12
LK is input to the slave devices 3 and 4 via the cable 2A. The control unit 11 also outputs a control signal CTRL to the slave devices 3 and 4 via the cable 2D.

FIG. 3 shows the first slave device 3 shown in FIG.
The circuit configuration of is shown. In the figure, the first slave device 3 inputs a master out signal MOSI in accordance with a clock CLK input via a control unit 32 having the same circuit configuration as the control unit 11 in the master device 1 and a cable 2A. Shift register 31, decoder 3
3 and a buffer circuit 34. A device address ADR is set in the decoder 33. As will be described later, when the device address output from the first master device 1 matches the set device address ADR, the buffer circuit 34 is activated. Then, the serial data from the shift register 31 described later is output as the master-in signal MISO. The second slave device 4 also has the same circuit configuration as the first slave device 3. However, the device address ADR set in the decoder 33
Is different.

The operation of the synchronous serial bus system shown in FIGS. 1 to 3 will be described with reference to FIG. However, in order to simplify the description, only the first slave device 3 will be described as a slave device. The second slave device 4 is also the first
The same operation as that of the slave device 3 is performed. Master device 1
The control unit 11 therein energizes the clock generator 12 to output the clock CLK from the clock generator 12 via the cable 2A, and outputs the "high" level control signal CTRL to the cable 2D and the master out signal M.
As the OSI, the first function code FUNC1 is output from the shift register 13 to the cable 2B. The control signal CTRL is set to "low" level after outputting the function code FUNC1. This control signal CTRL is input to the control unit 32 of the first slave device 3 to put the control unit 32 in the data input processing control state. The function code FUNC1 is input to the shift register 31 of the first slave device 3 based on the clock CLK.

When the control signal CTRL is at the "low" level, the control unit 11 in the master device 1 causes the master out signal MOSI via the shift register 13.
As device address ADR1 and data DAT
A1 is sequentially output to the cable 2B. The shift register 31 in the first slave device 3 inputs the device address ADR1 and the data DATA1 according to the clock CLK. The control unit 32 uses the device address ADR
When 1 is input to the shift register 31, the control signals S32a and S3 are sent to the shift register 31 and the decoder 33.
2b is output and the first data, that is, the device address ADR1 is input to the decoder 33. The device address ADR is set in the decoder 33, and when this set address and the input device address ADR1 match, the buffer circuit 34 is energized. In the shift register 31, the function code FUNC1 sent from the master device 1 and the device address ADR1 are sent.
And the data DATA1 are held, and the buffer circuit 34 transfers the data held in the shift register 31 to the master-in signal MIS via the cable 2C.
It is output as O to the master device 1. The function code FUN held in the shift register 31
C1, device address ADR1 and data DATA
1 is stored in the RAM in the control unit 32 and is used as data from the first slave device 3.

The shift register 14 in the master device 1 receives the function code F sent as the master-in signal MISO, that is, the master-out signal MOSI.
UNC1, device address ADR1 and data DA
Take in TA1 sequentially. The control unit 11 compares the data received in the shift register 14 with the above-mentioned transmitted data and compares the transmitted slave device, in this case, the first device.
It is confirmed whether or not the communication with the slave device 3 has been normally performed.

After the above-described one series of communication operations, the next data communication operation is performed in the same manner as above. The same communication processing as described above is performed for the second slave device 4 or another slave device (not shown).

As described above, since all slave devices have dedicated data lines for reception and transmission according to their positions, malfunctions due to data communication collisions and protocol reading errors do not occur. Further, in this synchronous serial bus system, the above-mentioned communication can be performed with the four cables 2A to 2D, so that the connection is easy. Moreover, a complicated protocol is not required, and the circuit configuration in the master device 1 and the circuit configuration in the slave device are simple.

FIG. 5 shows the configuration of a synchronous serial bus system as a second embodiment of the present invention. This synchronous serial bus system is a multi-master system synchronous serial bus system. In this example, two master devices 1,
5 are arranged. This synchronous serial bus system is shown in Fig. 1.
A cable 2E for transmitting a bus inhibit signal BUSINH is added to the synchronous serial bus system shown in FIG.

The circuit configuration of the first master device 1 and the circuit configuration of the second master device 5 are the same. FIG. 6 shows a circuit configuration of the first master device 1. The circuit of the first master device 1 shown in FIG. 6 corresponds to the master device 1 shown in FIG.
The monitoring circuit 15 is added to the circuit configuration of FIG.

In the synchronous serial bus system shown in FIG. 5, since the two master devices 1 and 5 are connected, the communication performed by the first master device 1 taking the initiative and the second master device 1. It is possible that there may be a collision with the communication that the 5 takes on the initiative. A monitoring circuit 15 is provided to prevent this communication collision.
Monitors the signal level of cable 2E. The control unit 11 inputs the monitoring result of the monitoring circuit 15. If the level of the cable 2E is "low" level, the control unit 11 desiring to transmit the bus inhibit signal BUS.
INH is output to the cable 2E to set the cable 2E to the "high" level and acquire the transmission right (bus right) of its own.
As a result, immediately after that, even if the second master device 5 desires to transmit, the transmission right cannot be acquired until the cable 2E becomes "low" level.

The transmission operation of the first master device 1 which has acquired the bus transmission right, its transmission data, the response operation of the slave device side, etc. are the same as the operations and transmission data in the synchronous serial bus system of the first embodiment described above. Becomes In addition,
During this communication period, the second master device 5 also receives the data from the first master device 1 similarly to the first slave device 3 and the second slave device 4, and receives the data from the slave device 1 like the slave device. Can work as one.
When the desired communication is completed, the control unit 11 in the first master device 1 receives the bus inhibit signal BUSIN.
H is set to "low" level to release the inhibit state of the cable 2E. Therefore, after that, the second master device 5 can perform communication.

As described above, even if there are a plurality of master devices, a multi-master synchronous serial bus system can be realized simply by adding the cable 2E and adding the monitoring circuit 15 to the master device. . Moreover, the circuit configuration to be realized is simple without requiring a complicated protocol.

[0019]

As described above, according to the synchronous serial bus system of the first embodiment of the present invention, a master device and a plurality of slave devices can be used with only four cables and with a simple protocol. It is possible to perform reliable synchronous data communication between them. In addition, according to the synchronous serial bus system of the second aspect of the present invention, a plurality of master devices can be used in a simple protocol with a simple protocol without communication collisions based on communication between a plurality of master devices. Reliable synchronous data communication can be performed between the master device and the plurality of slave devices.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a synchronous serial bus system according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a master device in FIG.

FIG. 3 is a diagram showing a configuration of a slave device in FIG.

FIG. 4 is a timing diagram showing an operation of the circuit shown in FIGS. 1 to 3.

FIG. 5 is a diagram showing a configuration of a synchronous serial bus system according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a master device in FIG.

FIG. 7 shows an example of a conventional synchronous serial bus system, IM.
It is a timing diagram which shows transmission of a bus system.

[Explanation of symbols]

1,5 Master device 3,4 Slave device 2A-2D cable 11 Master device control unit 12 clock generator 13, 14 Master device shift register 15 Monitoring circuit 31 Slave device shift register 32 Slave device control unit 33 decoder 34 buffer circuit CLK clock MOSI master out signal MISO master-in signal CTRL control signal BUSINH bus inhibit signal

   ─────────────────────────────────────────────────── ─── Continued front page       (56) References JP-A-2-307151 (JP, A)                 JP-A-2-266728 (JP, A)                 JP-A-63-236155 (JP, A)                 JP 58-219627 (JP, A)

Claims (2)

(57) [Claims] 1. A master device and a plurality of slave devices.
Is connected via a synchronous serial bus to the master
The device is in control of the transmission and is
Data from the master device to the slave devices of
Via the synchronous serial bus
Send the data to the desired slave device and
The slave device that receives the data
The data received via the
Sing to check the validity of the data sent by the star device
A master-serial synchronous serial bus system, wherein the master device includes master control means for controlling data transmission, clock generation means for generating a clock,
Yes and data output register, and a data input register
And, wherein the plurality of slave devices and addresses to each set comprises a slave control means for controlling data transmission, the slave register, a decoder, a buffer, the synchronous serial bus includes a clock transmission line A first data transmission line for serially transmitting data from the master device to a plurality of slave devices; and a second data transmission line for serially transmitting data from one of the slave devices to the master device. And a control signal transmission line for transmitting a control signal, wherein the master device and the plurality of slave devices include the clock transmission line, the first data transmission line, the second data transmission line, and the control. The master control means in the master device is connected via a signal transmission line. When transmitting data to one of the slave devices, the clock generating means is energized to generate a clock, which is sent to the clock transmission line, and the control signal line indicates a control signal indicating the start of transmission. The function code including information indicating data transmission to the slave device, the address code of the slave device of the data transmission partner, and the data are sequentially transmitted to the first data transmission line via the data output register. The slave register in the slave device holds a function code, an address code and data input via the first data transmission line in synchronization with a clock input via the clock transmission line, In the address check in the decoder, the received address code is When it matches the address of the slave device, the buffer returns the data held in the slave register to the master device via the second data transmission line, and the master control means of the master device is It is checked whether or not the data input via the second data transmission line and held in the data input register and the data sent to the data output register match. Master-based synchronous serial bus system. 2. A plurality of master devices and a plurality of slave devices
Is connected via a synchronous serial bus to the master
Each of the devices is in charge of transmission and the masters
A master device that can transmit multiple
Data from the master device that can transmit the data
Via the synchronous serial bus synchronized with the clock
To the slave device that wants to receive the data,
The slave device that received the data is the synchronous serial bus
The data received via the master device of the transmission source
Validate the data sent back and transmitted by the master device.
Multi-master synchronous serial bus method to check
In each of the plurality of master devices, a master control unit that controls data transmission, a clock generation unit that generates a clock, a data output register, a data input register, and a data transmission enable state are set. With the monitoring circuit to detect
A, wherein the plurality of slave devices and addresses to each set comprises a slave control means for controlling data transmission, the slave register, a decoder, a buffer, the synchronous serial bus includes a clock transmission line and the first data transmission line, the data from one of said plurality of slave devices for data serially transmitting from the transmission capable master device <br/> to a plurality of slave devices among the plurality of master devices Transmission
A second data transmission line for serially transmitting data to the master device, a control signal transmission line for transmitting a control signal, and a bus inhibit signal indicating that the master device capable of transmitting is transmitting. A bus inhibit signal transmission line, wherein the plurality of master devices and the plurality of slave devices include the clock transmission line, the first data transmission line, the second data transmission line, and the control signal transmission line. And connected via the bus inhibit signal transmission line, the master control means in the master device disables the bus inhibit signal transmission line when the bus inhibit signal transmission line indicates a usable state. Data transmission to one of the multiple slave devices At this time, the clock generating means is energized to generate a clock and send it to the clock transmission line, send a control signal indicating the start of transmission to the control signal line, and send the control signal through the data output register. The function code including information indicating data transmission to the slave device, the address code of the slave device of the data transmission partner, and the data are sequentially sent to one data transmission line, and the slave register in the slave device is the clock transmission line. The function code, the address code, and the data input via the first data transmission line are held in synchronization with the clock input via the, and the received address code is determined by the address check in the decoder. When the address of the slave device matches, the above buffer is The data held in the slave register is returned to the master device via the second data transmission line, and the master control means of the master device receives the data via the second data transmission line and receives the data. After checking whether or not the data held in the data input register and the data sent to the data output register match, the bus inhibit signal transmission line is enabled. Multi-master synchronous serial bus system.