JP3458415B2 - Unit test method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention makes it difficult for a unit having a plurality of semiconductor elements, such as a board, a package, or a highly integrated circuit (LSI), to run an ordinary test program for testing. The present invention relates to a unit test method, and more particularly, to a unit test method for performing a good test in consideration of temperature conditions of a semiconductor element mounted in the unit when the semiconductor element is actually operating.

The characteristics of a semiconductor device, for example, the logical delay time, changes with temperature. Since C-MOS, which is becoming mainstream recently, generates heat in accordance with switching operation, in a unit having a plurality of semiconductor elements, a temperature distribution according to the operating condition of each semiconductor element occurs in each unit. I will end up.

Conventionally, in consideration of the variation due to the temperature distribution, that is, even if there is the variation due to the temperature distribution,
We have designed the logic with enough margin so that it can operate sufficiently.

However, with the recent improvement in the performance of the data processing apparatus, the operating frequency thereof has become higher. With this, however, the logic design condition becomes stricter, and the variation in the performance due to the temperature change cannot be ignored. It has become to.

Therefore, it is necessary to assume the temperature distribution occurring in the unit in the actual operating state by, for example, a simulation, and perform the logic design in consideration of the logic delay characteristic corresponding to the assumed temperature. Therefore, the unit testing of the unit also requires a method of testing the semiconductor unit in consideration of the logic delay of the semiconductor element due to the temperature distribution.

[0006]

2. Description of the Related Art FIG. 3 is a diagram for explaining a conventional unit test method, and FIG. 4 is a diagram for explaining a temperature distribution during actual operation.

Conventionally, as shown in FIG. 3, the unit 1
When performing a unit test in which a plurality of semiconductor elements A, B, C, and D are mounted, each semiconductor element A, B, C, D
Since the temperature of is not controlled from the outside, an element that does not generate heat when it is in an actual operating state (switching state) even when energized, such as the C-MOS described above, is not operating. It was a unit test, and it was a test at room temperature.

[0008]

As described above, the semiconductor element has a characteristic that changes depending on temperature, such as the logical delay time. As described above, in an element that generates heat along with the actual operation (switching operation), there is a difference in heat generation between the portion where switching operation is intense and the portion where switching operation is small.

FIG. 4 is a diagram for explaining the temperature distribution during actual operation in the unit 1. As in the example shown in FIG. 4, when this unit, such as a package or a board, is mounted on a data processing device and a program is actually run,
The heat generated in the semiconductor element A is 1 W and the temperature is 30
Although the temperature is C, the semiconductor element B generates heat of 10 W, and if the temperature is 85 ° C., the temperature distribution shown in FIG. Will come out.

Therefore, a clock is supplied to the unit 1, and each semiconductor element A, B, C, D of the clock is supplied.
When measuring the logical delay for each of the semiconductor devices A, B, C, and D shown in FIG. 4, clock measurement is performed at a constant temperature as shown in FIG. Since the measurement is performed under a temperature condition different from the actual operating state, there is a problem in that it is impossible to carry out a test according to the logic design, for example, adjustment of clock variations.

In view of the above-mentioned conventional drawbacks, the present invention provides a unit testing method for testing a unit having a plurality of semiconductor elements, the unit testing method taking into consideration the temperature characteristics of the semiconductor elements mounted in the unit. The purpose is.

[0012]

FIG. 1 and FIG. 2 are views showing an embodiment of the present invention. FIG. 1 shows a heat source body A to be provided at a predetermined portion of a unit so FIG. 2 shows a case in which the temperature conditions in the actual operating states of the semiconductor devices A to D are controlled to be set, and FIG. 2 shows a predetermined semiconductor device A to the internal logic circuit in the unit, for example, a scan chain. Is used to set the temperature condition in the actual operating state by performing a pseudo operation. The above problems are solved by the unit test method configured as follows.

(1) In a unit test of a unit 1 having a plurality of semiconductor elements (A, B, ...), each of the semiconductor elements when the unit 1 is mounted in an apparatus and put into an actual operating state
Means for setting temperature conditions equivalent to the temperature of (A, B, ...) 10
The temperature condition setting means 10
The test is performed by setting the temperature of each semiconductor device (A, B, ...) of 1 to a predetermined temperature.

(2) As the temperature condition setting means 10, a heat source is provided at a predetermined place of the unit 1 so that the external unit 2
From this, by controlling the heat source, each semiconductor element (A, B, ...)
Is set to a predetermined temperature.

(3) As the temperature condition setting means 10, a predetermined logic circuit in the unit 1 is operated to set the temperature of each semiconductor element (A, B, ...) to a predetermined temperature. To do.

(4) As a method of operating the above logic circuit, a scan chain is used.

[0017]

That is, in the unit testing method according to the present invention, the semiconductor devices A to A in the unit are heated from the external control device to, for example, the heat source A until the temperature becomes close to the actual operating state.
Or by scanning a predetermined data with a predetermined clock using a scan chain to a logic circuit, such as a flip-flop (FF), which configures the semiconductor element A. The semiconductor elements A to
By operating the internal circuit {flip-flop (FF)} of the semiconductor elements A to heat up to a temperature close to the actual operating state, and performing a test of the unit.
For example, the above-mentioned clock delay adjustment or critical path measurement is performed.

Therefore, by placing each of the semiconductor elements A to a state close to the actual operating state, there is an effect that a more accurate unit test such as clock delay adjustment and critical path measurement can be performed.

[0019]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 and FIG. 2 described above are diagrams showing an embodiment of the present invention.

In the present invention, each of the semiconductor elements A to A in the unit 1 is heated to a temperature close to the actual operating state.
A test is performed by applying heat from the heat source A to the outside, or an internal circuit of the semiconductor element A is pseudo-operated by using, for example, a scan chain, so that the semiconductor element A The means for conducting the test by heating the internal circuit is the means necessary for carrying out the present invention. The same reference numerals indicate the same objects throughout the drawings.

The unit testing method of the present invention will be described below with reference to FIGS. First, as shown in FIG.
A control device 2 is provided near each semiconductor element A in the unit 1.
A heat source A that can be controlled from is provided.

Specifically, when the unit 1 is at the level of a printed board or a printed board, the heat source bodies A to A are provided in the vicinity of the highly integrated circuits (LSI) A mounted on the unit 1. By mounting a predetermined voltage from the external control device 2 to heat the heat source bodies A to, the highly integrated circuits (LSI) A to are maintained at a temperature close to an actual operating state. In the unit 1, each highly integrated circuit (LSI)
When the temperature distributions are almost the same as those in the actual operation of A to A, a predetermined test is performed.

Further, when the unit 1 is a highly integrated circuit (LSI), a resistor is provided near each logic element at the stage of designing the highly integrated circuit (LSI), and the highly integrated circuit (LSI) is provided. The highly integrated circuit by controlling the resistor from outside the (LSI).
After the temperature distribution inside the (LSI) is close to the temperature distribution when the highly integrated circuit (LSI) is actually operating,
Test the highly integrated circuit (LSI).

The temperature distribution in each unit 1 as described above is calculated in advance by, for example, logic simulation.
Since it can be recognized, it suffices to control the heat source bodies A to etc. so as to obtain the temperature distribution.

Next, in the embodiment shown in FIG. 2, each semiconductor element A is usually constructed by using the scan chain circuit for logic operation test provided in each unit 1. The flip-flop (FF) group is subjected to a pseudo operation that is close to the actual operating state to heat the flip-flop (FF) group.

Specifically, as shown in FIG.
For the scan chains forming the semiconductor elements A to, the control device 2 repeats scanning in and scanning out predetermined data with a predetermined clock for a predetermined time, whereby the semiconductor elements A to It is possible to generate heat by artificially operating (switching operation).

The scan chain consists of logic elements, in particular
Flip-flops (FF) are connected in series to test the logical operation of the flip-flops (FF). Repeated scan-in and scan-out of predetermined data to this flip-flop (FF) group is repeated. As a result, the temperature of each flip-flop (FF) can be adjusted so that the temperature distribution of the corresponding semiconductor elements A through in the unit can be made equal to that in the actual operation.

The above embodiment has shown the method of using the scan chain, but the point is that the operating rates and temperature distributions of the internal circuits of the semiconductor devices A to A are obtained by the above-mentioned logic simulation and the like. It suffices that the heat generation amount of the internal circuits of the semiconductor elements A to be controlled to a desired value by controlling from the control device 2, and the difference in the method does not particularly limit the present invention.

As described above, according to the present invention, in a unit test of a unit having a plurality of semiconductor elements, the unit is
It is equipped with means for setting temperature conditions equivalent to the temperature of each semiconductor when it is mounted in the device and in the actual operating state, and the temperature setting means sets the temperature of each semiconductor of the unit to a predetermined temperature. Test. As the temperature condition setting means, a heat source body is provided at a predetermined place of the unit, and the heat source body is externally controlled to set the temperature of each semiconductor element to a predetermined temperature. Further, as the temperature condition setting means, a predetermined logic circuit in the unit is operated to set the temperature of each semiconductor element to a predetermined temperature. A feature is that a scan chain is used as a means for operating a predetermined logic circuit in the unit.

[0030]

As described above in detail, according to the unit test method of the present invention, a more accurate unit test, for example, by placing each semiconductor device A to a state close to an actual operating state, It is effective in adjusting the clock delay and measuring the critical path.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention (No. 1).

FIG. 2 is a diagram showing an embodiment of the present invention (Part 2).

FIG. 3 is a diagram illustrating a conventional unit test method.

FIG. 4 is a diagram for explaining temperature distribution during actual operation.

[Explanation of symbols]

1 unit 10 temperature condition setting means 2 external controller heat source A to D A, B, C, D semiconductor element or heat source FF flip-flop

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-156175 (JP, A) JP-A-54-138344 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/66 G01R 31/26 G01R 31/28

Claims (4)

(57) [Claims] 1. When the device is mounted in an apparatus and is in an actual operating state
There in a way that Kino temperature of the semiconductor device for testing an electronic circuit units that have a plurality of different semiconductor elements in each element
Te, set the temperature individually for each semiconductor device under test unit
The temperature condition setting means for determining the actual temperature of each semiconductor element is used by the temperature condition setting means.
A unit test method, characterized in that the test is carried out in a state where the temperature is set to a temperature corresponding to the operating state . 2. The unit to be tested is the temperature condition setting means.
The heat source body is disposed at a predetermined position of the upper, by controlling the heat source body, the actual operating temperature of the semiconductor element
The unit test method according to claim 1, wherein a predetermined temperature corresponding to the state is set. Wherein said temperature setting means is tested unit
By operating a predetermined logic circuits provided within, according to claim 1, characterized in that set to a predetermined temperature corresponding to the actual operating conditions the temperature of the semiconductor <br/> element Unit test method. 4. A predetermined logic provided in the unit under test.
The unit test method according to claim 3, wherein a scan chain is used as the circuit .