JP3452657B2 - Information collection apparatus and method in communication network - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication network for transmitting cells having data, and to an apparatus and method for collecting information for each connection set on the communication network. For more details, see ATM (Asychronous Tr
ansfer Mode: An information collecting device and method for collecting information about the state and characteristics of a connection in a communication network using an exchange technology.

[0002]

2. Description of the Related Art ATM exchange, which is the core of broadband ISDN (Integrated Services Digital Network), which is a next-generation communication network, converts all information into fixed length packets called cells and handles them in an integrated manner within the communication network. This is a technology that enables high-speed transfer of information.

In an ATM network, a VPI (Virtual Path Identifie) of a header portion of a cell to be transmitted is used.
r: virtual path identifier) or VCI (Virtual Channel Iden)
The virtual connection (ATM connection) to which the cell belongs is designated by tifier (virtual channel identifier), and the routing control of the cell is performed for each ATM connection.

ATM connections include VP connections identified by VPI and VC connections identified by VPI and VCI. One of the important functions in a communication network (ATM network) that uses this ATM switching technology is maintenance and operation (OAM: Operation, Adm) that monitors network failures and performance.
inistration and Maintenance) function. OA is a cell that carries information for maintenance and operation on the ATM network.
Called M cell.

OA used for network fault monitoring
The M cell has an alarm indication signal (AIS).
Signal) cell and remote fault indication (RDI: Remote Defec)
t Indication) There is a cell. AIS cells and RDI cells are generated when a failure occurs in the ATM layer of the protocol.

[0006] For example, in the fault monitoring of the ATM layer by the AIS cell, the AI state transition condition is AI.
When one S cell is received, it is supposed to transit to the fault state. Then, when the alarm cell is not continuously received for 3 seconds or when the user cell is received, the normal state is restored. In the latter case, the user cell is the target cell for restoring the alarm state to the normal state. Further, it is necessary to notify the call processor of the ATM switch whether this alarm state is a fault state or a normal state.

The OAM cells used to monitor the performance of the network include PM (Performance Management).
t) There are cells, etc. The ATM network data collection device that measures the characteristics of the ATM connection by the ATM cell including the OAM cell and the user cell is
There are a TM connection quality measuring device and an ATM cell billing device.

ATM flowing into or out of an ATM exchange
In an ATM network data collection device that measures the characteristics of a cell, the characteristics of the cell are judged from the ATM cells that have flowed into the ATM network data collection device and the statistical information is updated. Further, it has a function of handing over the contents of the statistical information to the call processor in response to the read instruction of the call processor.

The ATM connection quality measuring device collects information such as the number of discarded cells, the number of passed cells, and the number of bit errors in the network, and measures the quality of the ATM connection. Further, the ATM cell charging device measures the number of cells flowing into the ATM switch, the number of cells discarded by the ATM switch, etc. for each ATM connection.

FIG. 31 is a block diagram of a conventional ATM network data collection device. In FIG. 31, the connection identification circuit 1 starts from the arriving cell to the statistical information memory 7
The connection identifier corresponding to the address of the network data to be updated is detected. The network data collection circuit 3 collects or calculates data used for updating from the arrived cells.

The statistical information memory 7 stores network data. The network data update circuit 6 receives the connection identification circuit 1 in the statistical information memory 7 when the cell arrives.
The value of the network data stored at the address indicated by and the output of the network data collection circuit 3 are added.

The processor interface circuit 2 receives the read request from the line control processor or the call processing processor and reads the contents of the statistical information memory 7. The address selector 4 selects an access address of the statistical information memory 7 output from the connection identification circuit 1 and the processor interface circuit 2. Further, the data selector 5 selects data to be written to the statistical information memory 7 output from the network data update circuit 6 and the processor interface circuit 2.

FIG. 32 shows the structure of the statistical information memory 7 when the number of passing cells for each VPI is measured by the ATM network data collection device shown in FIG. In the statistical information memory 7 shown in FIG.
The number of passing cells having is stored in the address i.

When a cell arrives, the connection identification circuit 1 latches the VPI of the arrived cell. At that time, the address selector 4 selects the output of the connection identification circuit 1 and reads the number of passing cells from the address of the statistical information memory 7 indicated by the VPI output from the connection identification circuit 1.

The network data updating circuit 6 adds 1 to the number of passing cells read from the statistical information memory 7,
The incremented number of passing cells is written in the statistical information memory 7 via the data selector 5.

When there is a read request from the line control processor or call processor, the processor interface circuit 2 creates a read address. At this time,
The address selector 4 selects the output of the processor interface circuit 2, and the number of passing cells is read from the statistical information memory 7. Then, the processor interface circuit 2 writes the number of passing cells to 0 in the statistical information memory 7. As a result, the read number of passing cells is cleared to 0 (0 clear function).

As described above, in the ATM network data collection device, the statistical information when the cell arrives is read into the statistical information memory 7, the statistical information updated at that time is written, and the statistical information when the read request is issued from the processor. Of 4 and subsequent clearing of the statistical information to 0 are required.

In the conventional ATM network data collection device, in order to avoid contention between the memory update at the time of cell arrival and the memory read request from the call processor or the like, generally, as shown in FIG. 33, the transit time of one cell (cell slot). Is time-shared. Then, in each time slot obtained by division, the corresponding access of the four types of memory access is performed.

[0019]

The device for monitoring the alarm cells (AIS cells, RDI cells) as described above is an indispensable device for widespread wideband ISDN, but there is no precedent yet. Therefore, there is a need to provide a device that manages alarm conditions using defined transition conditions and notifies the ATM switch call processor of them.

At this time, a memory for holding an alarm state for each ATM connection and a condition for recovering the alarm state are 3
There is a problem that a memory for holding a timer value for counting the alarm cell non-reception time per second is required, and the hardware of the memory becomes large.

Further, in order to accurately measure the unreceived time of 3 seconds, it is necessary to increase the number of ticks for counting this. However, the timer value has to be updated for all the set ATM connections within the time of the step width. Therefore, when the number of ATM connections becomes enormous, a large step size is required, and there is a problem that the measurement error of the unreceived time becomes large.

Further, in order to store the alarm state, if the alarm states of the ATM connections are arranged one by one in the address direction of the memory, when the call processor of the ATM switch is notified, one ATM connection is read out once. It only knows the alarm status of.

When a certain ATM connection is in a troubled state, it is necessary to inform the call processor which connection is in a troubled state. It takes a lot of processing time to read the alarm state of from the memory. In this case, it is necessary to read the alarm status of the connection in the normal status, which is wasteful. Therefore, there is a problem that it takes a lot of time for the call processor to grasp the alarm status of all ATM connections.

Further, the conventional ATM network data collection device has the following problems. 32 and 33 show the case where the ATM network data collection device collects a single piece of statistical information (the number of passing cells), but generally there are a plurality of items of statistical information to be collected. Therefore, it is generally necessary to update a plurality of statistical information upon arrival of one cell.

Here, the items of statistical information are (a),
(B), ..., 1 cell transit time (1 cell time)
Is divided into memory access cycles as shown in FIG. In FIG. 34, the number of memory access cycles within one cell time is four times the number of items corresponding to the four types of access shown in FIG.

By the way, the basic processing speed of an ATM cell is 156 Mbps (megabytes / second) or 622 Mbps, and the length of one cell is 53 bytes (or 54 bytes).
Therefore, one cell time is about 2.7 μs (for 156 Mbps) or about 675 ns (for 622 Mbps).
In the ATM network data collection device intended to collect a plurality of statistical information, the memory access as shown in FIG. 34 must be executed within these one cell time.

At this time, since there is a lower limit to one memory access cycle, the number of memory accesses within one cell time is naturally limited. For example, the basic processing speed is 6
When the memory access cycle is set to 75 ns in the 22 Mbps interface, the maximum number of accesses that can be made within one cell time is nine. Since the number of memory accesses in one cell time is four times the number of items of statistical information, the number of items in this case is limited to two or less.

Further, in the conventional memory access method as shown in FIG. 34, since one cell time is fixedly divided into four times the number of items of statistical information, even if there is an item which is not updated depending on the arriving cell. A time slot for updating is assigned to the item. Therefore, there is a wasteful time slot that is not actually needed.

An object of the present invention is to provide an apparatus and method for efficiently collecting information for each connection set on the communication network in a communication network for transmitting cells having data. More specifically, it is an object of the present invention to efficiently hold information about the state and characteristics of a connection in an ATM network at low cost and to notify the call processor quickly.

[0030]

DISCLOSURE OF THE INVENTION The present invention is an information collecting apparatus and method for collecting information about cells for each connection established on a communication network for transmitting cells having data.

FIG. 1 is a principle diagram of the information collecting apparatus of the present invention. The information collecting apparatus of FIG. 1 includes a collecting unit 11, an updating unit 12, a reading unit 13, and a storing unit 14. The storage means 14 stores the first information regarding the cell passing through the exchange in the communication network, for each connection set in the communication network.

Here, the connection means a virtual connection set in the communication network,
In ATM communication, it is identified by VPI or VPI and VCI.

The collecting means 11 identifies the connection to which the arriving cell belongs and determines the second connection related to the arriving cell.
And the updating means 12 updates the first information stored in the storage means 14 by using the second information extracted by the collecting means 11.

The reading means 13 reads and outputs the updated first information from the storage means 14 in response to a request from the processor provided for the exchange. The processor provided for the exchange is, for example, a call processor.

When the information device of FIG. 1 collects information about a failure of the communication network, the storage means 14 has a failure state indicating that there is a failure related to a connection of the communication network and a normal state indicating that there is no failure. Among them, the alarm state indicating any one of them is held as the first information.

Then, the updating means 12, when a cell notifying the occurrence of a failure regarding a certain connection arrives,
As the second information, the failure status is written in the alarm status related to the connection held by the storage means 14.

The storage means 14 has an alarm state / timer table memory which holds the alarm state and the timer value for counting the time during which the alarm state is in the failure state as the first information in one address.

Then, the updating means 12 updates the timer value, and when the timer value of a certain connection reaches a predetermined value, changes the alarm state of the connection to the normal state. The alarm state / timer table memory holds a plurality of sets of alarm states and timer values corresponding to one connection at one address, and the updating means 12 once sets a plurality of timer values held at one address. Access to update.

Further, the storage means 14 has an alarm state list table memory for holding a plurality of alarm states corresponding to a plurality of connections at one address, and the reading means 13 has an alarm state from the alarm state list table memory. Read out.

When at least one of a plurality of alarm states corresponding to a plurality of connections belonging to a certain group indicates a failure state, the storage means 14 indicates that there is a failure related to any one of the plurality of connections of the group. It has an alarm state OR display table memory for storing the indicated data.

The reading means 13 first reads the above-mentioned data of a certain group in the alarm state OR display table memory, and reads the alarm state when the data indicates that there is a failure.

Further, the storage means 14 indicates that when at least one of a plurality of alarm states corresponding to a plurality of connections belonging to a certain group is changed, there is an alarm state change relating to any one of the plurality of connections of the group. It has an alarm state change OR display table memory for storing the indicated data.

The reading means 13 first reads the above data of a certain group of the alarm state change OR display table memory, and reads the alarm state when the data indicates that there is an alarm state change.

Further, when the alarm status of a certain connection changes, the storage means 14 latches change information consisting of at least one of the alarm status after the change and the type of failure and the identifier of the connection in the order of occurrence. The read-out means 13 reads the change information latched by the alarm-state latch means.

Here, the type of failure means, for example, a distinction between an AIS cell and an RDI cell. When the information collecting apparatus of FIG. 1 measures the characteristics of a connection using a communication cell passing through the exchange, the storage means 14 stores the first information consisting of two or more data regarding the passing cell in the communication network. It is stored for each connection set to.

Then, the collection means 11 refers to the second information and sends to the update means 12 an update request for the data of one of the identifier of the connection of the arrived cell and the first information.

Based on the received connection identifier and one data update request, the updating means 12 sets the
It has an address creating means 15 for creating a storage address of the storage means 14 corresponding to one data.

Then, the updating means 12 selects the above-mentioned one data that needs to be updated from the first information stored in the storage means 14 based on the connection identified by the collecting means 11 and the second information. , Using the second information, part 1
Update one data.

Further, the collecting means 11 makes the first information if the first information needs to be updated as a result of referring to the second information.
And sends a request to update the information to the updating means 12. Further, when the update means 12 receives the update request for the first information, the update means 12 prohibits the read by the read means 13 during the passage time of the arrived cell, and permits the read when the update request for the first information is exhausted. It has adjusting means 16.

Then, when the update means 12 receives the update request for the first information, the update means 12 updates the first information using the second information extracted by the collection means 11, and the read means 1
When the updating means updates the first information within the passage time of the arrived cell, the storage means 1 is provided outside the passage time.
The first information is read from 4.

The memory means 14 of FIG. 1 is the embodiment of the alarm state transition table memory 63 of FIG. 4, the fault recovery timer table memory 64, the alarm state / timer table memory 66 of FIG. 6, the alarm state list table memory 67, and the alarm of FIG. It includes a state OR display table memory 68, an alarm state change OR display table memory 68 ', an alarm state latch circuit 69, and a statistical information memory 97 of FIG. The alarm state latch circuit 69 corresponds to alarm state latch means.

The alarm cell processing circuit 61 of FIGS. 4 and 6 corresponds to the collecting means 11 and the updating means 12 of FIG. 1, and the failure recovery timer updating circuit 62 corresponds to the updating means 12. Figure 15
The connection identification circuit 91 and the network data collecting circuit 93 correspond to the collecting means 11, and the network data updating circuit 96 corresponds to the updating means 12.

The address creating circuit 98 of FIG. 15 corresponds to the address creating means 15, and the access adjusting circuit 99 corresponds to the adjusting means 16. Further, the processor interface circuit 65 of FIGS. 4 and 6 and the processor interface circuit 92 of FIG. 15 correspond to the reading means 13.

[0054]

In the case of collecting the information on the failure of the communication network, if the arriving cell is a cell notifying the occurrence of the failure, the updating means 12 writes the failure state in the alarm state regarding the connection to which the cell belongs. When the timer value of a connection reaches a predetermined value, the updating means 12 returns the alarm status of the connection from the failure status to the normal status.

Thus, the presence / absence of a failure is managed for each connection set in the communication network. Also, 1
The alarm status and timer value corresponding to one connection are stored in one address of the alarm status / timer table memory. Therefore, it is not necessary to separately prepare a memory for storing the alarm state and a memory for storing the timer value, and the memory is saved.

By storing a plurality of sets of alarm states and timer values in one address, the updating means 12 can update a plurality of timer values with one access, which corresponds to a large number of connections. The time required to update the timer value is shortened. Therefore, the accuracy of the timer value is improved.

A plurality of alarm states corresponding to a plurality of connections are stored in one address of the alarm state list table memory. Therefore, the reading means 13 can read a plurality of alarm states at once from the alarm state list table memory.

Since it is possible to determine whether or not the alarm status of the connection in a certain group includes the failure status based on the data in the alarm status OR display table memory, when the failure status does not include the failure status, the alarm status of the connection in the group is determined. Does not need to be read. Therefore, the reading of the alarm state is made efficient.

The alarm status change OR display table It is possible to determine whether or not the alarm status of the connection in the group has changed by the data in the memory. Therefore, if the alarm status does not change, the alarm status of the connection in the group is determined. Does not need to be read. Therefore, the reading of the alarm state is made efficient.

Only when the alarm state changes, the alarm state latching means latches change information such as the changed alarm state in the order of occurrence. As a result, the reading unit 13 can read only the changed alarm states in the order of occurrence, and the readout of the alarm states becomes efficient.

When measuring the characteristics of a connection using a communication cell, the collection means 11 sends a request for updating the connection identifier and data of the arrived cell to the updating means 12. As a result, the updating unit 12 recognizes that the data of the first information needs to be updated.

The address creating means 15 creates a storage address of the storage means 14 in which the data of the connection is stored, based on the connection identifier and the data update request.

As a result, the updating means 12 can selectively update only the data that needs to be updated, and it is not necessary to access the data that need not be updated. Therefore, it is possible to reduce the number of memory accesses for updating within the passage time of one cell.

Further, the adjusting means 16 reads the reading means 1 during the passage time (cell slot) of the cell accompanied by the data update.
Reading by 3 is prohibited. As a result, in this cell slot, it is not necessary to provide a time slot for reading by the reading means 13 and clearing to zero.

Since the reading means 13 waits until there is no data update request and reads the first information, it is not necessary to provide a time slot for updating data in the cell slot at the time of reading. Therefore, the number of time slots required for one cell slot is further reduced.

As described above, the efficiency of holding and reading the collected information is improved.

[0067]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 shows an example of an ATM communication network using the information collecting apparatus according to the embodiment of the present invention. In FIG. 2, the subscriber's terminal 31 and terminal 41
An ATM connection is established between the terminals 42 and 47.

For example, the cell generated at the terminal 31 includes the transmission line 32 on the subscriber side, the interface 33, and the ATMSW3.
4, interface 35, ATM network transmission line 36, ATM cross-connect device 36 ', ATM network transmission line 36 ", interface 37, ATMS
It is sent to the terminal 41 via the W38, the interface 39, and the transmission line 40 on the subscriber side.

The cell generated at the terminal 42 is the transmission line 43 on the subscriber side, the interface 44, the ATMSW3.
4, interface 35, ATM network transmission line 36, ATM cross-connect device 36 ', ATM network transmission line 36 ", interface 37, ATMS
It is sent to the terminal 47 via the W38, the interface 45, and the transmission line 46 on the subscriber side.

Interfaces 33, 39, 44, 45
Are subscriber interfaces provided as subscriber circuits such as trunks.
Reference numerals 7 are interfaces for relaying communication within the ATM network. Also, the call processor 48,
Reference numeral 49 is a call processing processor provided in each of the ATM exchanges 34 'and 38'. The information collecting device of the present invention is, for example, an interface 33, 35, 37, 39,
It is housed in 44, 45, etc.

In the transmission path of the cell from the terminal 31 to the terminal 41, when a failure occurs in the transmission path 36 in the direction of the terminal 41 due to, for example, disconnection of a cable for communication, the ATM cross connect device 36 'detects this VP failure. Then, the VP-AIS cell is transmitted toward the terminal 41. This VP
-AIS cells are detected at the interface 37, which informs the call processor 49 that this VP is in a faulty state.

Further, when the VP failure of the transmission line 36 is detected, A
The TM switch 38 'transmits a VP-RDI cell toward the terminal 41 in order to notify the ATM switch 34' of the occurrence of the VP failure toward the terminal 41. This VP-RDI cell is detected by the interface 35, and the interface 35 notifies the call processor 48 that the transmission path 36 to the terminal 41 is in a failure state.

FIG. 3 is a block diagram of an interface that accommodates the information collecting apparatus of the present invention. The interface 51 of FIG. 3 is, for example, the interfaces 33, 35, 3 of FIG.
Call processor 56 corresponding to 7, 39, 44, 45
Corresponds to the call processor 49, 48.

In FIG. 3, the physical layer terminating device 52 controls the physical layer protocol between the transmission line and the ATM switch. The alarm collection device 53 and the network data collection device 54 respectively correspond to the embodiments of the information collection device of the present invention. The line control processor (firmware) 55 sends a command from the call processor 56 to the physical layer terminating device 5.
2, alarm collection device 53, network data collection device 5
4 and the call processor 56 to provide necessary information.

Next, the alarm collecting apparatus of the present invention will be described with reference to FIGS. 4 to 12. Figure 4
The example of 1 structure of the alarm collection device 53 of FIG. 3 is shown. Figure 4
The alarm collection device 60-1 includes an alarm cell processing circuit 61, a failure recovery timer updating circuit 62, an alarm state transition table memory 63, a failure recovery timer table memory 64, and a processor interface circuit 65.

The alarm state transition table memory 63 has a VP
An alarm state transition table in which an alarm state for each ATM connection designated by I or VCI is registered is held. The failure recovery timer table memory 64 is a failure recovery timer in which a timer value for each ATM connection is registered in order to measure the alarm cell non-reception time of 3 seconds, which is one condition for recovering the alarm status from the failure status to the normal status. Hold the table.

The alarm state transition table memory 63 and the fault recovery timer table memory 64 are each, for example, a RAM.
(Random Access Memory). The alarm cell processing circuit 61 determines whether the arriving cell is an alarm cell, a cell targeted for failure recovery, or another cell. Then, the alarm state transition table of the alarm state transition table memory 63 is written according to the type of the arrived cell. The failure recovery timer updating circuit 62 updates the registered data in the alarm state transition table and the failure recovery timer table.

In the ATM communication, the ATM connection to which the cell belongs is identified by the VPI and VCI of the header part of the cell. The OAM cell of the VP connection can be discriminated by the value of VPI and a predetermined VCI. The VC connection OAM cell is a PTI (Payload Type Ide) in the cell header.
ntifier) and the VPI and VCI.

In the OAM cell, the information indicating the type of the OAM cell is written in the first byte of the user area (payload) of the cell.
It can be identified as a DI cell.

The processor interface circuit 65 exchanges information with the line control processor 55,
In response to a request from the line control processor 55, the alarm status of the ATM connection is read from the alarm status transition table.

FIG. 5 shows an example of the alarm state transition table stored in the alarm state transition table memory 63 of FIG. The alarm state transition table of FIG.
The alarm state An of M connection n (n = 0, 1, 2, ...) Is stored in the address n. For example, when the alarm state An is 0, it indicates a normal state, and when it is 1, it indicates a fault state.

When the arriving cell is an alarm cell for notifying the failure of ATM connection 0, the alarm cell processing circuit 6
1 writes 1 to the alarm status A0 stored in the address 0 of the alarm status transition table, resets the timer value of the ATM connection 0 in the failure recovery timer table, and starts counting. Then, this operation is repeated every time the alarm cell of the ATM connection 0 arrives. Normally, an alarm cell is sent every second until the fault that occurred occurs is recovered.

When an alarm state read request is issued from the line control processor 55, the processor interface circuit 6
5 reads the alarm state transition table and informs that ATM connection 0 is in a failure state. The failure state of the ATM connection 0 is notified to the call processor 56 of FIG. 3 through the line control processor 55.

If the alarm cell of the next ATM connection 0 does not arrive until the timer value of the ATM connection 0 reaches 3 seconds, the fault recovery timer updating circuit 62 changes the alarm state A0 of the alarm state transition table to 0. . afterwards,
The call processor 56 is notified through the line control processor 55 that the ATM connection 0 has become normal.

When a user cell belonging to an ATM connection arrives before the timer value of the ATM connection reaches 3 seconds, it is considered that the fault has been recovered and the alarm state of the ATM connection is set to the normal state. It may be configured to return.

In this way, the ATM shown in FIGS.
Manages alarm status on a connection-by-connection basis and manages them by ATM
It is possible to notify the call processor of the exchange. However, in the embodiment of FIG. 4, the alarm state transition table memory 63 and the failure recovery timer table memory 64 are provided separately, and two memories are required.
Further, since the alarm state transition table of FIG. 5 stores the alarm states of one ATM connection at one address, it takes time to read all the alarm states.

FIG. 6 shows another example of the configuration of the alarm collection device 53 shown in FIG. The alarm collection device 60-2 of FIG. 6 includes an alarm cell processing circuit 61, a failure recovery timer updating circuit 62, an alarm state / timer table memory 66, an alarm state list table memory 67, an alarm state OR display table memory 68, and an alarm state change. An OR display table memory 68 ', a fault connection latch circuit 69, and a processor interface circuit 65 are provided.

Of these, the alarm state list table memory 6
7. The alarm state OR display table memory 68, the alarm state change OR display table memory 68 ', and the fault connection latch circuit 69 are not necessarily provided. Further, only the alarm state list table memory 67, a combination of the alarm state list table memory 67 and the alarm state OR display table memory 68, or the alarm state list table memory 67 and the alarm state change OR display table memory 68 '.
Combination, or alarm status list table memory 6
7 and the fault connection latch circuit 69 may be combined.

In FIG. 6, the basic operations of the alarm cell processing circuit 61, the failure recovery timer updating circuit 62, and the processor interface circuit 65 are the same as those in FIG. The differences from the embodiment of FIG. 4 will be mainly described below.

FIG. 7 shows an example of the configuration of the alarm state / timer table held in the alarm state / timer table memory 66. In the alarm status / timer table of FIG. 7,
For one address of the memory, the alarm status of one ATM connection stored in the alarm status transition table memory 63 of FIG. 4 and the failure recovery timer table memory 64
And the timer value of the same ATM connection stored in.

ATM connection n (n = 0, where alarm cell processing circuit 61 or failure recovery timer updating circuit 62 exists)
1, 2, ...) When updating the alarm status An, the corresponding address n is designated and the updated value of An is written.

As described above, if the alarm state transition table and the failure recovery timer table are stored in one memory, the storage area of the memory can be effectively used and the required hardware can be reduced.

However, when the information of one ATM connection is assigned to one address and the number of ATM connections becomes enormous, the time required to update the timer value for all the connections becomes long, and the measurement time until the failure recovery occurs. There may be an error in.

FIG. 8 shows another example of the alarm state / timer table stored in the alarm state / timer table memory 66. In the alarm status / timer table of FIG. 8, the alarm status of two ATM connections stored in the alarm status transition table memory 63 of FIG. 4 and the failure recovery timer table memory 64 are stored for one address of the memory. The same two ATM connection timer values are assigned.

For example, address 0 stores the alarm states and timer values of ATM connections 0 and 1, address 1 stores the alarm states and timer values of ATM connections 2 and 3, and address 2 stores ATM connection 4 The alarm states and timer values of 5 and 5 are stored.

In the configuration of FIG. 8, when the failure recovery timer updating circuit 62 updates the failure recovery timer value, the timer values of two ATM connections can be updated simultaneously by one memory access. Therefore, the time required to update the timer values for all connections is about half that of the configuration of FIG. 7, and the time required to update the timer is shortened.

In FIG. 8, two ATMs are assigned to one address.
It stores the alarm status of the connection and the timer value,
By storing the information of many ATM connections in one address, the time required for updating the timer is further shortened.

In the embodiments shown in FIGS. 4 and 5, in order to read the alarm states of all ATM connections in the alarm state transition table in response to a read request from the line control processor 55, as many alarm state transition tables as the number of connections are read. The memory 63 must be accessed.

Therefore, a memory for displaying the alarm state in a bit map is separately provided, and a plurality of A's can be read by one reading.
If the alarm status of the TM connection can be read, the number of memory accesses can be reduced.

In the embodiment shown in FIG. 6, an alarm state list table memory 67 is provided in addition to the alarm state / timer table memory 66 for storing the alarm states so that the processor interface circuit 65 can read the alarm states at high speed.

FIG. 9 shows the alarm state list table memory 67.
3 shows an example of the configuration of the alarm status list table stored in FIG. The alarm status list table of FIG. 9 stores alarm statuses of eight ATM connections at one address.

For example, for the address 0, the alarm states A0, A1, A2, A3, A of the ATM connections 0 to 7 are given.
4, A5, A6, A7 are stored, and AT is stored at address 1.
M connection 8 to 15 alarm status A8, A9,
A10, A11, A12, A13, A14 and A15 are stored.

When an alarm cell arrives, the alarm cell processing circuit 61 updates the alarm state of the alarm state / timer table and then updates the corresponding alarm state of the alarm state list table. The processor interface circuit 65 receives the alarm state read request from the line control processor 55,
The alarm state is read from the alarm state list table memory 67 and is transmitted to the line control processor 55.

In FIG. 9, one memory access results in 8
The alarm statuses of individual ATM connections can be read, and the alarm statuses of all connections can be read at high speed. The number of alarm states stored in one address may be any plural number and is not limited to eight.

Even if the alarm state list table is provided,
At the time of arrival of the alarm cell and at the time of updating the alarm state by the failure recovery timer updating circuit 62, it is easier in terms of hardware configuration to arrange the alarm states one by one in the memory address direction. On the other hand, when a read request is issued from the line control processor 55, it is better to read more alarm states of ATM connections with one memory access. Therefore, in addition to the alarm state / timer table, an alarm state list table having a form in which a plurality of alarm states are arranged at one address is provided.

Similar effects can be expected even if the alarm state list table memory 67 of FIG. 6 is added to the embodiment of FIG. When the alarm status in the failure status is read from the alarm status list table and transmitted to the line control processor 55, for example, when the failure status is written in the last read address of the alarm status list table, the waste becomes very large.

In order to reduce this waste, for example, the following 3
There are two possible ways. The first two of them are methods of reading the alarm state in two stages. In the first method, alarm states of ATM connections are grouped for each arbitrary plurality. First, each group is notified of the presence / absence of a fault condition, and then the alarm state of the ATM connection in the group including the fault condition is read to determine which A
Notify whether the TM connection is in a failure state.

In the second method, the AT is set for each arbitrary plurality.
Group M connection alarm status changes. First, the presence / absence of an alarm state change is notified to each group unit, and then the alarm state of the ATM connection in the group including the alarm state change is read to notify which ATM connection of the alarm state has changed.

The other method is to separately store only the information of the ATM connection whose alarm state has changed. In this method, for example, information such as the identifier of an ATM connection that has transitioned from a normal state to a fault state and the type of failure is held as change information in a latch circuit, for example. Information is read sequentially.

In the embodiment of FIG. 6, the alarm status OR display table memory 68 stores the presence / absence of a failure status for each ATM connection group, and the alarm status change OR display table memory 68 'stores the alarm status for each ATM connection group. Whether or not there is a change is stored, and the alarm state latch circuit 69
Holds information about the ATM connection whose alarm state has changed. By using the alarm state OR display table memory 68, the alarm state change OR display table memory 68 ', or the alarm state latch circuit 69, the readout of the alarm state is speeded up.

FIG. 10 shows an example of the constitution of the alarm state OR display table held in the alarm state OR display table memory 68 and the relation between the alarm state list table.
The alarm cell processing circuit 61 divides all the ATM connections into several groups, with a plurality of ATM connections corresponding to a plurality of alarm states stored in one address of the alarm state list table as one group. Then, the logical sum of the values indicating the alarm states in each group is calculated and stored as the failure state of each group in the alarm state OR display table.

For example, as shown in FIG. 10, if even one value of the alarm state in one group is 1, 1 indicating that there is a failure state in the group is 1 in the alarm state OR display table. Marked in the corresponding column. When all the alarm status values in the group are 0, it is considered that there is no failure status, and 0 is written in the corresponding column in the alarm status OR display table.

When an alarm state read request is issued from the line control processor 55, the processor interface circuit 6
5 first reads the alarm state OR display table. Then, the alarm state list table is further read out only for the group showing the fault state, and which ATM
Informs the line control processor 55 whether the connection is in a failure state.

FIG. 11 shows an example of the constitution of the alarm state change OR display table held in the alarm state change OR display table memory 68 'and the relation between the alarm state list table.

The alarm cell processing circuit 61 divides all the ATM connections into several groups, with a plurality of ATM connections corresponding to a plurality of alarm states stored in one address of the alarm state list table as one group. To do. Then, the logical sum of the values indicating the alarm state change in each group is calculated and stored as the alarm state change of each group in the alarm state change OR display table.

For example, as shown in FIG. 11, if even one value of the alarm state in one group changes from 0 to 1, 1 indicating that there is a change in the alarm state in the group is an alarm. The corresponding column in the state change OR display table is marked as an alarm state change. When all the alarm status values in the group remain 0, it is considered that the alarm status does not change, and 0 is written in the corresponding column in the alarm status OR display table.

Similarly, when the value of the alarm status in the alarm status list table changes from 1 to 0, 1 indicating that there is a change in the alarm status is written in the alarm status change OR display table.

When an alarm state read request is issued from the line control processor 55, the processor interface circuit 6
5 first reads the alarm state change OR display table.
Then, the alarm state list table is read out only for the group showing the alarm state change, and the line control processor 55 is notified of which ATM connection has changed the alarm state and how.

If the alarm state OR display table memory 68 or the alarm state change OR display table memory 68 'is provided, it is not necessary to always read all the alarm states in the alarm state list table.

FIG. 12 is a block diagram showing an example of the configuration of the alarm state latch circuit 69. When the alarm cell arrives,
The alarm cell processing circuit 61 stores the change information such as the identifier of the corresponding ATM connection and the type of failure in the alarm state FIFO 71 in the order of arrival. Further, when the alarm state / timer table timer value reaches the value (3 seconds) designated by the recovery condition, the failure recovery timer updating circuit 62 sequentially outputs the corresponding ATM connection change information to the alarm state FIF.
Store in O71.

As a result, the information of the ATM connection whose alarm status has changed is changed to the alarm status FIFO in the order of occurrence of the change.
It is stored in 71. Although the VPI or VCI of the alarm cell is used as the identifier of the ATM connection, an identification number or the like may be defined and used. The failure type is information indicating whether the alarm cell is an AIS cell or an RDI cell, for example.

In response to the read request from the line control processor 55, the processor interface circuit 65 sequentially reads the information of the alarm state FIFO 71 and sends it to the line control processor 55.

The FIFO control circuit 72 controls the write operation to the alarm state FIFO 71 by the alarm cell processing circuit 61 and the fault recovery timer updating circuit 62 and the read operation from the alarm state FIFO 71 by the processor interface circuit 65.

FIG. 13 shows the alarm status FIFO 71 and the FIFO.
A specific configuration example of the O control circuit 72 is shown. FIG.
In the above, the dual port RAM 81 is used as the alarm state FIFO 71, and the FIFO control circuit 72 is
It is composed of a D circuit 82, counter circuits 83 and 84, and a subtraction circuit 85.

The dual port RAM 81 has a terminal Din for inputting write data (write data) and a terminal Dout for outputting read data (read data). Further, a terminal WA to which an address (write address) for writing the write data is input, a terminal RA to which an address (read address) for reading the read data is input,
And terminals WE and RE to which a write enable signal and a read enable signal are input, respectively.

The counter circuit 83 updates the value of the output Q each time a pulse is input to the terminal CLK to specify the write address, and the counter circuit 84 similarly specifies the read address.

Further, the subtraction circuit 85 subtracts the write address input to the terminal B from the read address input to the terminal A and outputs the logical signal FULL from the terminal L. For example, when the difference between the values of the terminals A and B reaches a predetermined value, the signal F
ULL becomes a logic 1 and indicates that the storage area of the dual port RAM 81 is full (FULL state). When the difference between the values of terminal A and terminal B is less than the predetermined value, signal FU
LL becomes a logical 0, indicating that there is a free space in the storage area.

An alarm state change signal is input from the alarm cell processing circuit 61 and the fault recovery timer updating circuit 62 to one input terminal of the AND circuit 82, and the inversion of the signal FULL is input to the other input terminal. The alarm cell processing circuit 61 outputs an alarm state change signal as logic 1 when an alarm cell arrives, and the fault recovery timer update circuit 62 outputs an alarm state change signal as logic 1 when the ATM connection is restored from the fault state. To do.

Therefore, when there is some change in the alarm state registered in the alarm state / timer table and there is a free space in the storage area of the dual port RAM 81,
The AND circuit 82 outputs logic 1 as a write enable signal. Write enable signal is dual port RA
Input to the terminal WE of M81 and the counter circuit 8
It is also input to the terminal CLK of 3 and the write address is counted up.

As a result, the change information of the ATM connection having the change in the alarm state sent from the alarm cell processing circuit 61 or the failure recovery timer updating circuit 62 is written in the dual port RAM 81 as the write data. In this case, the write data contains the changed alarm state (failure state or normal state) and the alarm type (VP-AIS /
VP-RDI / VC-AIS / VC-RDI) and AT
The M connection identifier (VPI / VCI) is included.

The alarm cell processing circuit 61 and the fault recovery timer updating circuit 62 reset the alarm state change signal to logic 0 after the writing of the ATM connection information is completed.
To In this way, writing of write data to the dual port RAM 81 is performed when the alarm state of the ATM connection changes.

On the other hand, the read data is read from the dual port RAM 81 when a read request is issued from the line control processor 55. At this time, the read enable signal from the processor interface circuit 65 becomes a logic 1, for example. The read enable signal is input to the terminal RE of the dual port RAM 81 and also to the terminal CLK of the counter circuit 84 to count up the read address.

As a result, the ATM connection change information read from the dual port RAM 81 is sent to the line control processor 55 via the processor interface circuit 65 in the order in which the change occurred.

If the alarm state latch circuit of FIG. 13 is provided,
The line control processor 55 can read only the information of the ATM connection whose alarm state has changed, and
It is not necessary to read the alarm status of M connection. Next, the network data collection device of the present invention will be described with reference to FIGS. 14 to 30.

As an example of the network data collection device 54, the configuration of FIG. 31 can be considered. However, in the embodiment, instead of the statistical information memory 7, a statistical information memory having a configuration as shown in FIG. 14 is used.

In FIG. 14, data of a plurality of items of statistical information is stored in one memory address designated by the VPI and the item of statistical information. For example, the data of three items (a), (b), and (c) regarding the ATM connection whose VPI is 0 is stored in the first address. Similarly, for the items (d) and subsequent items, data for each of the following three items is sequentially stored at the next address. However, data of two items (m) and (n) are stored at the last address of VPI = 0. The same applies to the ATM connection data whose VPI is 1 or more.

FIG. 15 shows an access cycle for the statistical information memory shown in FIG. In FIG. 15, since data of three items can be read or written by one memory access, the number of divisions of one cell time can be reduced as compared with the case of FIG. 34 in which data of the same number of items is accessed. You can

If the number of divisions in one cell time is the same, data of many items can be stored in the statistical information memory. In this way, by expanding the statistical information memory in the data direction, it becomes possible to collect a large amount of statistical information within one cell time.

However, in the configuration of FIG. 14, since a plurality of items are arranged at the same memory address, the storage area is required for the items of the same address, and the memory amount increases. In the current general-purpose memory, data direction (bit direction)
Since the width of is generally 8 bits or 16 bits, a large number of memories must be used due to the constraint condition in the bit direction.

FIG. 16 shows the network data collection device 5
4 is another configuration example of No. 4. The network data collection device of FIG. 16 includes a connection identification circuit 91, a processor interface circuit 92, and a network data collection circuit 9.
3, an address selector 94, a data selector 95, a network data updating circuit 96, a statistical information memory 97, an address creating circuit 98, and an access adjusting circuit 99.

In FIG. 16, the statistical information memory 97 is
Save network data. The connection identification circuit 91 reads the identification information of the ATM connection to which the cell arrives from the arrived cell, and the address creation circuit 98
Give to. The identification information of the ATM connection is, for example, an identifier such as VPI or VCI.

The network data collecting circuit 93 collects or calculates data used for updating the statistical information memory 97 from the arrived cells. Then, it checks the items of statistical information that need to be updated, and sends update requests for those items to the address creation circuit 98 and the access adjustment circuit 99.

The address creating circuit 98 searches the address of the data that needs to be updated in the statistical information memory 97 on the basis of the output of the connection identifying circuit 91 and the update request from the network data collecting circuit 93, and obtains the obtained address. It is given to the address selector 94.

The network data updating circuit 96, when the cell arrives, receives the address selector 9 in the statistical information memory 97.
The value of the network data stored in the address designated by 4 is read. Then, the output of the network data collection circuit 93 is added to the read value, and the data selector 9
5 to the statistical information memory 97.

The processor interface circuit 92 receives the read request from the line control processor 55, reads the network data in the statistical information memory 97, and sends it to the line control processor 55. Further, the data sent from the line control processor 55 is sent to the access adjusting circuit 99.
To the data selector 95 via.

In response to the read request from the processor interface circuit 92, the access adjustment circuit 99 prohibits the line control processor 55 from reading in the cell slot in which the network data is updated, and waits until the cell slot in which the update is not performed. Control.

The address selector 94 selects an access address of the statistical information memory 97 designated by the address creating circuit 98 and the access adjusting circuit 99. Also,
The data selector 95 is the network data update circuit 9
6 and the write data to be output to the statistical information memory 97 from the access adjusting circuit 99 is selected.

FIG. 17 shows an example of the structure of the statistical information memory 97 when the ATM connection is designated by the VPI. In FIG. 17, one AT is assigned to one address
Data of one item regarding the M connection is stored. The data storage address is specified by the value of VPI and the item of statistical information.

For example, the data items (a) to (n) relating to the ATM connection whose VPI is 0 are sequentially stored one by one, and then the data items (a) to (n) relating to the ATM connection whose VPI is 1 are stored. They are stored one by one in order. The same applies to data with VPI of 2 or more.

FIG. 18 shows an example of memory access by the network data collection circuit of FIG. When a cell arrives, as shown in FIG. 18A, among the ATM connection items (a) to (n) to which the cell belongs,
Items that need to be updated are sequentially read from the statistical information memory 97, and the updated data are sequentially written. At this time, the processor interface circuit 92 does not read.

Therefore, the number of memory accesses within one cell time upon arrival of a cell is at most twice the number of items.
If the items that need to be updated are limited, then less memory access is required. The access address at this time is generated by the address generation circuit 98.

At the time of reading by the line control processor 55, as shown in FIG.
After the items (a) to (n) of the TM connection are sequentially read, those data in the statistical information memory 97 are sequentially cleared to 0. Therefore, the line control processor 55
The number of times of memory access within one cell time at the time of reading by is 2 times the number of items.

FIG. 19 is a schematic diagram showing a cell slot in which the reading shown in FIG. 18B is performed. As shown in FIG. 19, in the cell slot where the data in the statistical information memory 97 needs to be updated, even if a read request is received from the line control processor 55, reading is not performed. In the cell slot of the cell that needs to be updated, the memory access shown in FIG. 18A is performed.

Then, in the cell slot of the cell in which the data in the statistical information memory 97 does not need to be updated, the line control processor 55 permits the read and the data is read through the processor interface circuit 92. Such read control is performed by the access adjustment circuit 99.
Done by.

FIG. 20 shows the address creating circuit 98 of FIG.
An example of the configuration is shown. Address creating circuit 9 of FIG.
8 has an address adjustment circuit 101 for selecting an item to be updated from the items (a) to (n) of the statistical information. The address adjusting circuit 101 is a network data collecting circuit 93.
An access address is generated from each update request of items (a) to (n) which is the output of

The output of the address adjusting circuit 101 and the ATM connection identifier (for example, VPI) output from the connection identifying circuit 91 are passed to the address selector 94 as an access address of the statistical information memory 97.

By providing the address generation circuit 98, it is possible to selectively generate the address of the data that needs to be updated and reduce the number of memory accesses within one cell time.

FIG. 21 shows the access adjustment circuit 99 shown in FIG.
An example of the configuration is shown. The access adjustment circuit in FIG. 21 includes a NOR circuit 102 and an AND circuit 103. N
The OR circuit 102 takes the logical sum of the update requests for the respective items, which is the output of the network data collection circuit 93, and outputs the negative thereof to the AND circuit 103. The AND circuit 103 is
The logical product of the output of the NOR circuit 102 and the μP read request from the processor interface circuit 92 is output to the address selector 94. Further, the ATM connection identifier (for example, VPI) designated by the processor interface circuit 92 is delivered to the address selector 94.

When at least one of the update requests of items (a) to (n) is logic 1, the output of the NOR circuit 102 is logic 0. Therefore, the μP read request is logical 1
Therefore, the AND circuit 103 outputs a logic 0 even when there is a read request from the processor interface circuit 92. At this time, the address selector 94 generates an access address based on the output of the connection identification circuit 91.

When all the update requests of items (a) to (n) are logic 0, the output of the NOR circuit 102 becomes logic 1,
If the μP read request is logic 1, the AND circuit 103 outputs logic 1. At this time, the address selector 94
Generates an access address for the data of items (a) to (n) based on the ATM connection identifier given from the access adjusting circuit 99.

As described above, the read request from the line control processor 55 is masked by using the logical sum condition of the update requests of the respective items, so that the line control processor 55 performs the read up to the cell slot in which the data update is not performed. Can be delayed.

Next, an ATM connection quality measuring device as an example of the network data collecting device will be described with reference to FIGS. 22 to 28. The ATM connection quality measuring device has the same structure as the network data collecting device 54 of FIG.
nal Telecommunication Union) -T Recommendation I. OAM called 610 PM (Performance Management) cell
ATM cells are used to measure the quality of ATM connections.

As an example, the ATM connection quality measuring devices accommodated in the interfaces 33 and 39 of FIG. 2 are the ATM switch 34 'and the ATM switch 3 respectively.
A case will be described in which the quality of ATM connections multiplexed on the transmission lines 36 and 36 ″ between 8 ′ is measured.

First, the ATM connection quality measuring device in the interface 33 multiplexes one PM cell every time a predetermined number of user cells pass through the ATM connection to be measured. MSN (Monitori
ng Sequence Number), TUC (Total User Cell Numb
er), BIP (Bit Interleaved Parity) 16, CRC
Information such as (Cyclic Redundancy Check) is stored.

MSN is the sequence number of the PM cell in question, TUC represents the number of user cells passing before the PM cell in question, and BIP16 represents the PM cell immediately before and the P cell in question.
It is a BIP16 code for a user cell between M cells, and CRC is a CRC code of the PM cell.

Next, the ATM connection quality measuring device in the interface 39 uses the MS in the received PM cell.
Information such as N and TUC is compared with inflowing user cells, and various statistical information such as the number of cells discarded on the transmission path 36 and the number of bit errors is updated. The call processor 49 of the ATM switch 38 then uses the interface 3 as necessary.
Various kinds of statistical information are read from the ATM connection quality measuring device in FIG.

FIG. 22 shows a PM cell insertion position when a PM cell is inserted between user cells of an ATM connection. PM for every 4 user cells flowing
When inserting a cell, as shown in FIG. 22, M is inserted in an empty slot after four user cells C1, C2, C3, C4.
A PM cell with SN = 1 is inserted. TU of this PM cell
C is 4 and BIP16 is the calculation result for the user cells C1 to C4.

The next PM cell of MSN = 2 should originally be inserted at the position indicated by (↑) after the user cells C5, C6, C7, and C8, but the user cell C9 is located at this position.
Therefore, it is actually inserted in the subsequent empty slot indicated by ↑. Therefore, the TUC of this PM cell is M
The number of user cells between two PM cells, which is 5 is added to 4 which is the TUC of the PM cell with SN = 1, yields 9. BIP1
6 is a calculation result for the user cells C5 to C9. M
User cells C10 and C11 are provided after the PM cell of SN = 2.
Continues.

In FIG. 22, PM cells are inserted every four user cells, but in practice, for example, 256 and 51 are inserted.
PM cells are inserted every 2 or 1024 and quality measurement is performed.

Specific network data items collected by the ATM connection quality measuring device in the interface 39 for each ATM connection include, for example, the following items.

Number of Discarded Cells Discarded on Transmission Line Number of Mixed Cells Mixed on Transmission Line Number of Cell Data Error Bits Generated on Transmission Line Number of User Cells Transmitted by ATM Switch 34 Number of Blocks with Cell Discarded Cell Mixing Occurred The number of blocks in which a bit error has occurred The number of CRC errors in a PM cell The number of cells mixed in with an item indicates the number of cells that have arrived extra due to incorrect insertion, etc., and the number of error bits in an item is determined by the ATM connection quality measuring device itself. Calculated BIP16 value and P
It represents the difference from the value of the M cell. The block (monitoring block) in the items (1) to (3) means a section between one PM cell and a PM cell before the same regarding an ATM connection.

The statistical information memory 97 of the ATM connection quality measuring device for storing these statistical information is constructed as shown in FIG. 23, for example. In FIG. 23, for each ATM connection identified by the VPI, data of one item of to is stored in one address. The access address is designated by the VPI and the item type.

Focusing on each of the items 1 to 3, one PM
The item and the item are not updated at the same time when the cell arrives. Further, the bit error of the item is defined only when there is no discarding / mixing between the received PM cells. Therefore, it can be seen that the items and cannot be updated simultaneously. For the same reason, the items and cannot be updated at the same time.

Further, considering that the data of (1) are valid only when the CRC result of the PM cell is normal (the data of the item is 0), at least the item and the item are not updated at the same time.

At this time, the access cycle to the statistical information memory 97 of FIG. 23 can be configured as shown in FIG. When the PM cell arrives, as shown in FIG. 24A, the memory access may be performed up to 6 times within one cell time.

First, the item or item data is read from the statistical information memory 97, then the item or item data is read, and then the item or item data is read. Then, the update data of item or item is written in the statistical information memory 97, the update data of item or item is written next, and the update data of item or item is written next.

When the data of the item of the arriving PM cell is not 0, the information of the PM cell is not always normal, and therefore, even if the data of the items 1 to 3 are subsequently read, they are not updated.

When a read request is issued from the line control processor 55, as shown in FIG. 24 (b), the cell slot of a cell other than the PM cell in which data is not updated is not read out in the cell slot of the PM cell in which data is updated. Read with. The cell slot of a cell other than the PM cell is, for example, a cell slot of a user cell or an empty slot.

In this way, the number of memory accesses to the statistical information memory 97 can be reduced. Figure 2
5 shows an example of the configuration of the address creating circuit 98 in the ATM connection quality measuring device. The encoders 111, 112, 113 and the selector 114 in FIG. 25 correspond to the address adjustment circuit 101 in FIG.

In FIG. 25, when the network data collection circuit 93 requests the update of the data of each item of to, it is assumed that the update request of the corresponding item is logical 1. The update requests for the items 1 to 3 are input I1 and I2 of the encoder 111, inputs I3, I4 and I5 of the encoder 112, and inputs I3 and I of the encoder 113, respectively.
4, connected to I5.

The relationship between the inputs I1 and I2 of the encoder 111 and the output O1 is as shown in FIG. When the inputs I1 and I2 are logic 0 and 0 and when they are logic 1 and 0, the output O1 is logic 0, and when the inputs I1 and I2 are logic 0 and 1, the output O is output.
1 becomes logical 1. Input I1 and I2 are logical 1 and 1 because the update request with the item does not become logical 1 at the same time.
It never becomes.

Input I of encoders 112 and 113
The relationship between 3, I4, I5 and outputs O2, O3 is as shown in FIG. When the inputs I3, I4, and I5 are logic 0, 0, 0 and when the inputs are logic 1, 0, 0, the outputs O2 and O3 are logic 0,
It becomes 0. The inputs I3, I4, and I5 are logic 0, 1,
When it is 0, the outputs O2 and O3 are logic 0 and 1, and the input I
Outputs O2, O when 3, I4, I5 are logic 0, 0, 1
3 becomes logical 1 and 0.

Two or more update requests out of items do not become logical 1 at the same time.
Since two or more of the update requests among them do not become logical 1 at the same time, two or more of the inputs I3, I4, and I5 cannot become logical 1 at the same time.

The output O1 of the encoder 111 is input to the input SI1 of the selector 114 together with the two logic 1 signals. The outputs O2 and O3 of the encoder 112 are input to the input SI2 of the selector 114 together with the signal of logic 0, and the outputs O2 and O3 of the encoder 113 are input to the input SI3 of the selector 114 together with the signal of logic 1.

The selector 114 selects any one of the inputs SI1, SI2 and SI3 according to the value of the update time slot signal supplied from the network data collection circuit 93 and outputs it to the address selector 94.

For example, when accessing item or data, the update time slot signal becomes 00,
Input SI1 is selected. Also, when accessing any of the data items ,,, the update time slot signal becomes 01, the input SI2 is selected, the item,
, The update time slot signal becomes 10, and the input SI3 is selected.

Then, an access address is generated by the output of the selector 114 and the VPI which is the output of the connection identification circuit 91 and is given to the address selector 94. For example, when updating item data, input SI
1 is selected and the output of the selector 114 becomes 011. In the case of an ATM connection with VPI = 0, the address output to the address selector 94 is 0011 (=
3) and the address 3 of the statistical information memory 97 of FIG.
Pointing to.

Similarly, when updating the item data, the input SI1 is selected and the output of the selector 114 becomes 111 (= 7). When updating the data of the items and, the input SI2 is selected, and the outputs of the selector 114 are 000, 001, and 010, respectively. Input SI3 is selected when updating the data of the items ,, and the outputs of the selector 114 are 100 and 10, respectively.
It becomes 1,110.

The structure of the access adjusting circuit 99 in the ATM connection quality measuring device is the same as that shown in FIG.
Next, an ATM cell charging device which is another example of the network data collecting device will be described with reference to FIGS. 28 and 29.

In the ATM cell billing device which provides the pay-per-use function of the ATM connection, the number of cells flowing into the ATM switch is measured for each ATM connection, and the information is measured by the call processor 56 through the line control processor 55.
To notify.

Here, specific network data items collected by the ATM cell charging device for each ATM connection include, for example, the following (1) to (8). (1) Number of CLP = 0 user cells passing through ATM switch (2) Number of CLP = 1 user cells passing through ATM switch (3) Number of CLP = 0 OAM cells passing through ATM switch (4) ATM switch Number of OAM cells with CLP = 1 that passed (5) Number of user cells with CLP = 0 that violated UPC (6) Number of user cells with CLP = 1 that violated UPC (7) Number of OAM cells with CLP = 0 that violated UPC ( 8) CLP (Cell Loss Priority) of items (1) to (4) of the number of OAM cells with CLP = 1 violating UPC
Indicates the priority of discarding the cell when the buffer in the ATM switch is congested. Since cells with CLP = 0 receive high quality services that are hardly discarded even during congestion,
The charges will be higher. Moreover, the cell of CLP = 1 is
It is easy to be discarded at the time of congestion, and the charge is relatively low.

UPC (Usage Paragraph) of items (5) to (6)
meter control) is a method in which a subscriber declares a cell rate band, and counts cells exceeding the declared band as UPC violation cells.

The structure of the statistical information memory 97 (charging memory) of the ATM cell charging device for storing these statistical information is as follows.
It becomes similar to FIG. The billing memory contains (1) to (8)
The number of arriving cells is stored for each of the eight types of attributes shown in.

Here, paying attention to the items (1) to (8), when one cell arrives, the cell has CLP =
0 user cell, CLP = 1 user cell, CLP = 0
Of the OAM cell of CLP = 1 and the OAM cell of CLP = 1, it is impossible to update two or more of the items (1) to (4) simultaneously. For the same reason, items (5)-
There can be no more than one simultaneous update of (8).

At this time, the access cycle to the statistical information memory 97 can be configured as shown in FIG.
When a cell arrives, as shown in FIG. 28A, memory access may be performed up to four times within one cell time.

First, the data of any of the items (1) to (4) is read from the statistical information memory 97, and then the data of any of the items (5) to (8) is read. Then, the update data of any of items (1) to (4) is written to the statistical information memory 97, and then the update data of any of items (5) to (8) is written.

When a read request is issued from the line control processor 55, as shown in FIG. 28 (b), the cell is not read in the user cell or the cell slot of the OAM cell accompanied by the data update, and the cell such as an empty cell in which the data is not updated. Read in the cell slot of.

In this way, the number of memory accesses to the statistical information memory 97 can be reduced. Figure 2
9 is an address generation circuit 9 in the ATM cell charging device
8 shows a configuration example of No. 8. The encoder 12 of FIG.
1, 122 and the selector 123 correspond to the address adjusting circuit 101 in FIG.

In FIG. 29, the update request for each item (1) to (8) is received from the network data collection circuit 93 as in FIG. The update requests for the items (1) to (8) are input to the encoder 121 via inputs I6, I7,
I8, I9, inputs I6, I7, I of the encoder 122
8 and I9 are connected.

Input I of encoders 121 and 122
The relationship between 6, I7, I8, I9 and outputs O4, O5 is shown in FIG.
It becomes like 0. When the inputs I6, I7, I8, I9 are logic 0, 0, 0, 0 and when the inputs are logic 1, 0, 0, 0, the outputs O4, O5 are logic 0, 0.

When the inputs I6, I7, I8, I9 are logic 0, 1, 0, 0, the outputs O4, O5 are logic 0, 1 and the inputs I6, I7, I8, I9 are logic 0, 0, 1,
When it is 0, the outputs O4 and O5 are logic 1 and 0. Input I
When 6, I7, I8 and I9 are logic 0, 0, 0 and 1, the outputs O4 and O5 are logic 1 and 1.

Two or more update requests of the items (1) to (4) never become the logic 1 at the same time, and similarly, two or more update requests of the items (5) to (8) do the logic at the same time. Since it never becomes 1, the inputs I6, I7, I8, I9
No more than one of them will be a logical one.

The outputs O4 and O5 of the encoder 121 are input to the input SI4 of the selector 123 together with the signal of logic 0, and the outputs O4 and O5 of the encoder 122 are input to the input SI5 of the selector 114 together with the signal of logic 1.

The selector 114 selects either the input SI4 or SI5 according to the value of the update time slot signal supplied from the network data collection circuit 93 and outputs it to the address selector 94.

For example, when accessing the data of items (1) to (4), the update time slot signal becomes 0, and the input SI4 is selected. Also, items (5)-
When accessing any of the data in (8), the update time slot signal becomes 1, and the input SI5 is selected.

Then, an access address is generated by the output of the selector 123 and the VPI which is the output of the connection identification circuit 91 and is given to the address selector 94. For example, when updating the data of the item (1), the input SI4 is selected, the output of the selector 123 becomes 000, and when updating the data of the items (2), (3) and (4), the input SI4 is changed. When selected, the outputs of the selector 123 become 001, 010 and 011 respectively. When updating the data of items (5), (6), (7), and (8), the input SI5 is selected, and the outputs of the selector 123 are 100, 101, 110, and 111, respectively.

The structure of the access adjusting circuit 99 in the ATM cell billing device is also the same as that shown in FIG. As described above, the number of accesses to the statistical information memory at the time of cell arrival can be reduced, and the network data collection device can be configured with an inexpensive memory having an access speed slower than that of the conventional statistical information memory.

Also, as compared with the case where the statistical information memory is expanded in the bit direction as shown in FIG. 14, the number of statistical information memories can be smaller. The statistical information memory shown in FIGS. 14, 17, and 23 is an AT identified by VPI as an example.
Network data is stored for each M connection. However, in the present invention, the ATM connection can be defined by any other method, and the statistical information memory stores the network data for each defined ATM connection.

For example, an ATM connection identified by VPI and VCI can be handled in the same manner.

[0210]

According to the present invention, in a communication network for transmitting cells such as ATM cells, it becomes possible to efficiently collect information for each connection set on the communication network.

More specifically, it is possible to efficiently hold information on characteristics such as the alarm state and quality of the connection in the communication network, the number of passing cells, etc. at low cost. In addition, it is possible to efficiently read the held information and notify the call processor accommodated in the exchange or the like.

Further, the time used as the alarm condition transition condition can be accurately counted.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of a communication network according to an embodiment.

FIG. 3 is a configuration diagram of an interface in the embodiment.

FIG. 4 is a configuration diagram (1) of the alarm collection device according to the embodiment.

FIG. 5 is a diagram showing a configuration example of an alarm transition table.

FIG. 6 is a configuration diagram (part 2) of the alarm collection device according to the embodiment.

FIG. 7 is a diagram (part 1) showing a configuration example of an alarm state / timer table.

FIG. 8 is a diagram (part 2) showing a configuration example of an alarm state / timer table.

FIG. 9 is a diagram showing a configuration example of an alarm state list table.

FIG. 10 is a diagram showing an example of an alarm state OR display table.

FIG. 11 is a diagram showing an example of an alarm state change OR display table.

FIG. 12 is a block diagram of an alarm status latch circuit.

FIG. 13 is a diagram showing an example of an alarm state latch circuit.

FIG. 14 is a diagram (part 1) showing a configuration example of a statistical information memory.
Is.

FIG. 15 is a diagram (No. 1) showing memory access.

FIG. 16 is a configuration diagram of a network data collection device according to an embodiment.

FIG. 17 is a diagram showing a configuration example of a statistical information memory (No. 2)
Is.

FIG. 18 is a diagram (No. 2) showing memory access.

FIG. 19 is a diagram (No. 1) showing the timing of reading by the processor.

FIG. 20 is a configuration diagram (1) of an address creating circuit.

FIG. 21 is a configuration diagram of an access adjustment circuit.

FIG. 22 is a diagram showing PM cell insertion positions.

FIG. 23 is a configuration diagram of a statistical information memory in the connection quality measuring device.

FIG. 24 is a diagram showing memory access in the connection quality measuring device.

FIG. 25 is a configuration diagram (part 2) of the address generation circuit.

FIG. 26 is a diagram (No. 1) showing input and output values of the encoder.

FIG. 27 is a diagram (No. 2) showing input and output values of the encoder.

FIG. 28 is a diagram showing memory access in the charging device.

FIG. 29 is a configuration diagram (3) of the address generation circuit.

FIG. 30 is a diagram (No. 3) showing input and output values of the encoder.

FIG. 31 is a configuration diagram of a conventional network data collection device.

FIG. 32 is a diagram showing a configuration example of a conventional statistical information memory.

FIG. 33 is a diagram showing a basic unit of conventional memory access.

FIG. 34 is a diagram showing memory access in a conventional time division time slot.

[Explanation of symbols]

1, 91 Connection identification circuit 2, 65, 92 Processor interface circuit 3, 93 Network data collection circuit 4, 94 Address selector 5, 95 Data selector 6, 96 Network data update circuit 7, 97 Statistical information memory 11 Collection means 12 Update means 13 read-out means 14 storage means 15 address creation means 16 adjusting means 31, 41, 42, 47 terminals 32, 36, 36 ″, 40, 43, 46 transmission path 33, 35, 37, 39, 44, 45, 51 interface 34 , 38 ATMSW 34 ', 38' ATM switch 36 'ATM cross-connect device 48, 49, 56 call processor 52 physical layer terminating device 53 alarm collector 54 network data collector 55 line control processor 61 alarm cell processing circuit 62 fault recovery Timer New circuit 63 Alarm status transition table memory 64 Fault recovery timer table memory 66 Alarm status / timer table memory 67 Alarm status list table memory 68 Alarm status OR display table memory 68 'Alarm status change OR display table memory 69 Alarm status latch circuit 71 Alarm State FIFO 72 FIFO control circuit 81 Dual port RAM 82, 103 AND circuits 83, 84 Counter circuit 85 Subtraction circuit 98 Address creation circuit 99 Access adjustment circuit 101 Address adjustment circuit 102 NOR circuits 111, 112, 113, 121, 122 Encoder 114, 123 selector

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yutaka Ezaki Yutaka Ezaki 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Koji Amano 1-4-4 Hakata Station, Hakata-ku, Fukuoka City, Fukuoka Prefecture, Fujitsu Limited Kyushu Communication Systems Co., Ltd. (56) Reference JP 5-191408 (JP, A) JP 6-69923 (JP, A) JP 61-163494 (JP, A) IEICE technical research Report CS91-92 (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/56 H04L 12/24-12/26

Claims (25)

(57) [Claims] 1. An information collecting device for monitoring a failure of a communication network by means of a communication cell passing through an exchange, wherein first information relating to the failure of the communication network is stored for each connection set in the communication network. Storage means for identifying the connection to which the arriving cell belongs and extracting second information relating to the arriving cell; and the storage means using the second information extracted by the collecting means. And updating means for updating the first information stored in the storage means , and reading means for reading and outputting the updated first information from the storage means, the storage means comprising the communication network of the communication network. Connexion
Failure status indicating that there is a failure related to the
Normal state indicating no faults
The alarm status indicating either is stored as the first information.
The update means has a failure related to the connection.
When the cell notifying the
As the second information, the connection information stored in the storage means is stored.
The alarm status related to the connection, the storage means stores the duplicate status corresponding to the plurality of connections.
Number of alarm states holding one alarm address
A state list table memory, and the reading means includes the alarm state list table memory
An information collecting apparatus , wherein the alarm status is read from the information collecting apparatus. 2. The information collecting apparatus according to claim 1, wherein the storage unit stores first information regarding a fixed-length packet having data. 3. The information collecting apparatus according to claim 2, wherein the storage unit stores first information regarding a cell in asynchronous transfer mode communication. 4. The information collecting apparatus according to claim 3, wherein the collecting unit identifies the connection using at least one of a virtual path identifier and a virtual channel identifier included in the arrived cell. . 5. The memory means includes an alarm state transition table memory that holds the alarm state, and a failure recovery timer table memory that stores a timer value for counting the time during which the alarm state is in the failure state. The updating means updates the timer value in the failure recovery timer table memory, and when the timer value reaches a predetermined value, changes the alarm state related to the connection to the normal state, and the reading means. in response to a request from the processor provided in the exchange correspondence, information collection apparatus according to claim 1, wherein the reading the alarm condition from the alarm state transition table memory. 6. The alarm status storing unit stores the alarm status and a timer value for counting the time during which the alarm status is in the fault status in one address.
A timer table memory is provided.
1. The information collection device described in 1 . 7. The alarm status / timer table memory holds a plurality of sets of the alarm status and the timer value corresponding to one connection at one address, and the updating means stores the one address. 7. The information collecting apparatus according to claim 6 , wherein the plurality of timer values held in are updated by one access. 8. The storage means has a failure relating to any one of the plurality of connections when at least one of the plurality of alarm states corresponding to the plurality of connections belonging to a certain group indicates the failure state. The alarm state OR display table memory storing data indicating that the read means reads the data of the certain group of the alarm state OR display table memory, and the data indicates that the fault exists. the information collection apparatus according to claim 1, wherein the reading the alarm condition from said alarm condition list table memory. 9. The storage means stores, when a change occurs in at least one of the plurality of alarm states corresponding to the plurality of connections belonging to a certain group, an alarm state change relating to any one of the plurality of connections. An alarm state change OR display table memory for storing data indicating that there is, and the reading means reads the data of the certain group of the alarm state change OR display table memory;
If the data indicates that there is a change in the alarm state,
Information collection apparatus according to claim 1, wherein the reading the alarm condition from said alarm condition list table memory. 10. The storage means, when at least one of the plurality of alarm states corresponding to the plurality of connections belonging to a certain group indicates the failure state,
An alarm state OR display table memory for storing data indicating that there is a failure relating to any one of the plurality of connections, wherein the reading means reads the data of the certain group of the alarm state OR display table memory, information collection apparatus according to claim 1, wherein the reading the alarm condition to indicate that the data is the failure. 11. The storage means, when a change occurs in at least one of the plurality of alarm states corresponding to the plurality of connections belonging to a certain group, an alarm state change relating to any one of the plurality of connections. An alarm state change OR display table memory for storing data indicating that there is, and the reading means reads the data of the certain group of the alarm state change OR display table memory;
Information collection apparatus according to claim 1, wherein the reading the alarm condition to indicate that the data is the alarm status change. 12. An alarm for latching, when the alarm status of the connection changes, the storage means latches change information including the changed alarm status, at least one of the failure types, and the connection identifier. 7. A state latch means is provided, and the read means reads the change information latched by the alarm state latch means.
1. The information collection device described in 1 . 13. The alarm status latching means, when the alarm status changes from the fault status to the normal status,
13. The information collecting device according to claim 12 , wherein the change information is latched when the alarm state changes from the normal state to the fault state. 14. The alarm state latch means includes a storage circuit for holding the change information in chronological order, according to claim 13, characterized in that it comprises a memory control circuit for controlling writing and reading of the memory circuit Information collection device. 15. An information collecting device regarding a communication cell passing through an exchange in a communication network, wherein first information consisting of two or more data regarding the passing cell is stored for each connection set in the communication network. Storage means, collecting means for identifying the connection to which the arriving cell belongs, and extracting second information regarding the arriving cell, based on the connection and the second information identified by the collecting means, Updating means for selecting one piece of data that needs to be updated from the first information stored in the storage means and updating the one piece of data using the second information; and a reading means for reading and outputting the information, when the processor reads the first information, the cell arrives
The timing of the read timing is
An information collection device characterized by dynamically allocating mobile slots . 16. The collecting means refers to the second information and sends an update request for the connection identifier and the one data to the update means, and the update means receives the received connection identifier. 16. An address creating means for generating an address corresponding to the one data of the first information based on the update request of the one data.
Information collection device described. 17. An information collecting device having a connection quality measuring device for performing quality measurement for each connection using a cell for maintenance and operation of the communication network, wherein the storage means comprises: Data of two or more measurement items related to connection quality is stored as the first information, and the collecting unit has the connection identifier of the cell for the maintenance operation and the data of the two or more measurement items. As the second information, the updating means updates data of one measurement item that needs to be updated among the two or more measurement items, and updates data of measurement items that do not need to be updated. The information collecting apparatus according to claim 15 , wherein the information collecting apparatus is not provided. 18. An information collecting device having a cell charging device that provides a pay-per-use charging function for each connection, wherein the storage means uses the number of arrived cells for each attribute of the passing cells as the first information. Storing, the collecting means extracts the identifier and the attribute of the connection that the arriving cell has as the second information, and the updating means stores in the storage means corresponding to the attribute of the arriving cell. 16. The information collecting apparatus according to claim 15, wherein the number of cells is updated and the number of cells in the storage unit corresponding to other attributes is not updated. 19. An information collecting device for a communication cell passing through an exchange in a communication network, a storage means for storing first information about the passing cell for each connection set in the communication network, and an arrived cell. Collecting means for identifying the connection to which the belongs and extracting the second information regarding the arrived cell; and the collecting means when the first information stored in the storage means needs to be updated. Updating means for updating the first information by using the extracted second information; and, if the updating means updates the first information within the transit time of the arrived cell, outside the transit time. 2. An information collecting device, comprising: a reading unit that reads out the first information from the storage unit. 20. As a result of referring to the second information, the collecting means sends an update request for the first information to the updating means when the first information needs to be updated, When the update means receives the update request for the first information, the update means prohibits the read by the read means during the passage time of the arrived cell, and when the update request for the first information is exhausted, 20. The information collecting apparatus according to claim 19, further comprising adjusting means for permitting reading. 21. An information collecting device having a connection quality measuring device for performing quality measurement for each connection using a cell for maintenance and operation of the communication network, wherein the storage means comprises: Data of two or more measurement items related to connection quality is stored as the first information, and the collecting unit has the connection identifier of the cell for the maintenance operation and the data of the two or more measurement items. As the second information, and when the reading means does not need to update any of the two or more measurement items, data of one measurement item of the two or more measurement items is extracted. 20. The information collecting device according to claim 19, wherein 22. An information collecting device having a cell charging device for providing a pay-per-use charging function for each connection, wherein the storage means uses the number of arrived cells for each attribute of the passing cells as the first information. The collecting means extracts the connection identifier and the attribute of the arrived cell as the second information, and the reading means needs to update the number of arrived cells in the storage means. 20. The information collecting apparatus according to claim 19 , wherein the number of the arrived cells is read out when there is no cell. 23. An information collecting method for monitoring a failure of a communication network by means of a communication cell passing through an exchange, wherein first information regarding a failure of the communication network is set for each of a plurality of connections set in the communication network. At a single address, identifying the connection to which the arriving cell belongs, extracting second information about the arriving cell, updating the first information using the second information, and updating An information collecting method, comprising: each step of reading the first information obtained. 24. A method of collecting information about a communication cell passing through an exchange in a communication network, wherein first information consisting of two or more data about a passing cell is stored for each connection set in the communication network. It is necessary to identify the connection to which the arriving cell belongs, extract the second information regarding the arriving cell, and update the first information based on the connection and the second information 1 Selecting one data, updating the one data using the second information, and reading the updated first information.
And the cell arrives when the processor reads the first information
The timing of the read timing is
A method of collecting information, characterized by dynamically allocating mobile slots . 25. A method of collecting information about a communication cell passing through an exchange in a communication network, wherein first information about a passing cell is stored for each connection set in the communication network, and the arriving cell belongs to the first information. If it is necessary to identify a connection, extract second information about the arriving cell, and update the first information, the second information
Updating the first information by using the information of No. 1, and updating the first information within the transit time of the arrived cell, each step of reading the first information outside the transit time. Information collection method characterized by.