JP3446658B2 - Processor and its performance evaluation method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor having a function of executing instructions regardless of the order in which the instructions appear in a program, and a performance evaluation method thereof.

[0002]

2. Description of the Related Art Conventionally, in order to improve the processing performance of a pipeline processor that processes a single instruction sequence, for example, Japanese Patent Application Laid-Open No. 8-283289 and Japanese Patent Application Laid-Open No. 7-182.
In JP-A No. 160, etc., a processor of a superscalar method for executing a plurality of instructions at the same time or an Out of Order instruction issuing method for executing the instructions in different order is proposed.

A processor of such a system is provided with a reservation station and a reorder buffer so that instructions can be executed regardless of the order of appearance in the program, and information on the instructions decoded by the instruction decoder is provided. To the reservation station or reorder buffer. Then, based on the information registered in the reservation station or the reorder buffer, the respective instructions are executed in the order in which the program can be processed most efficiently.

However, in the case where the instructions executed by such a processor continuously access the same operand, particularly when an instruction having a long operation time is followed by an instruction referencing the same operand, or a branch instruction is issued. If the latency from the determination of the branch destination to the determination of the branch destination is long, the reservation station and the reorder buffer become full, and it becomes impossible to register information on the subsequent instruction. When this occurs, the instruction Out o
f Order execution and speculative execution cannot be performed, and the processing performance of the processor cannot be utilized.

[0005]

However, in the conventional processor, by grasping the occurrence of such a state and investigating the cause, an effective measure for effectively executing Out of Order execution or speculative execution. There was no means. That is, in the past, analysis was performed by relying on the source list of the program in order to find out the occurrence of the above state, but from the source list of the program, it is possible to know how the processor actually processes the instruction sequence. It was difficult to identify the relevant location that causes the above situation.

Further, since the conventional processor has no means for checking whether or not the reservation station or the reorder buffer is full, whether or not Out of Order execution or speculative execution of instructions is effectively performed for each different program. However, it was difficult to evaluate the performance of speculative execution in the processor.

It is an object of the present invention to provide a processor capable of performance evaluation as to whether or not execution is efficiently performed regardless of the order of appearance of instructions, and a method of evaluating the performance.

[0008]

To achieve the above object, a processor according to a first aspect of the present invention relates to an instruction fetched from a storage device for executing an instruction in a program regardless of the order of appearance. A buffer for temporarily storing information, a fullness determination means for determining whether or not the buffer is full by storing information about an instruction, and a fullness number counting for counting the number of times the fullness determination means determines fullness. Means and a full processing means for performing a predetermined full processing according to the number of times the full-number counting means counts.

In the above processor, a predetermined full process is performed while the buffer is full. This full processing can be, for example, externally indicating that the buffer is full or outputting data inside the processor to the outside. As a result, it becomes possible to evaluate the performance as to whether or not the execution is efficiently performed regardless of the order of appearance of the instructions.

The number of times the full-frequency counting means determines that the clock is full may be the number of times a predetermined clock signal is input while the full-frequency counter is determined to be full. Further, the number of times until the full process is performed may be set externally.

In the above processor, the fullness determination means may determine that the buffer is full when the buffer is full for a predetermined time or more.

In the above processor, the full processing means may include means for stopping the operation of the processor, for example.

In this case, the processor includes registration means for registering information relating to the issued or completed instruction when the instruction temporarily stored in the buffer is issued or when the execution of the instruction is completed. It may further include means for outputting information regarding an instruction registered in the registration means to the outside when the operation of the processor is stopped by the full processing means.

In the above processor, the full processing means may also include means for generating a predetermined interrupt to the processor.

In this case, the processor outputs the operating state of at least one of the fullness determining means and the fullness counting circuit to the outside when the fullness processing means generates an interrupt to the processor. Can be further provided.

In the above processor, the buffer may include an entry bit indicating whether or not each entry is valid. In this case, the processor may further include detection means for detecting whether or not the buffer is full by logically operating the values of all entry bits included in the buffer. The determining means may determine whether or not the buffer is full based on the result of the logical operation by the detecting means.

In the above processor, the buffer is a reorder buffer that holds the decoding result of the instruction fetched from the storage device until the execution of the instruction is completed, and / or the decoding result of the instruction fetched from the storage device. Can be configured by a reservation station that holds the command until the instruction is issued.

In order to achieve the above object, a processor performance evaluation method according to a second aspect of the present invention is a method for temporarily executing information about an instruction fetched from a storage device for executing an instruction in a program regardless of the order of appearance. A method for evaluating the performance of a processor having a buffer for storing, wherein a full determination step of determining whether or not the buffer is full by storing information regarding an instruction, and the buffer being full in the full determination step A full control step of causing the processor to perform a predetermined process in accordance with the number of times it is determined to be present.

In the above processor evaluation method, the fullness determining step may determine that the buffer is full when the buffer is full for a predetermined time or more.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the overall configuration of the processor according to this embodiment. As shown, the processor includes an instruction cache 101, an instruction decoder 102, and a reservation station 103.
A reorder buffer 104, a computing unit 105, a renaming register 106, a register 107, a detection circuit 109, a reorder buffer full determination circuit 110,
Reorder buffer full counter circuit 111, detection circuit 112, reservation station full determination circuit 1
13, reservation station full counter circuit 114, hardware stop circuit 115, interrupt /
An exception processing circuit 116, OR circuits 117 and 118, and an instruction tracer 119 are provided.

The instruction cache 101 is a buffer for storing a part of instructions stored in a main storage device (not shown). The instruction decoder 102 decodes the instruction read from the instruction cache 101, and registers information about the instruction including the decoded result in the reservation station 103 and the reorder buffer 104.

The reservation station 103 checks an issuable instruction among the registered instructions, and the computing unit 105 does not depend on the order in which the issuable instructions are registered.
Issue to. That is, the reservation station 103 performs the Out of Order instruction issuing process, and can check the register dependency between the registered instructions and issue an instruction that has no register dependency with other instructions. It is judged as a command. The information regarding the command registered in the reservation station 103 is erased by the issuance of the command.

The reorder buffer 104 is a buffer for storing information about an instruction that is speculatively executed by branch prediction when a branch instruction appears, and the instruction decoder 1
The information of the renaming register 106 updated by the instruction being speculatively executed is stored in association with the information about the instruction registered by 02. The information about the instruction registered in the reorder buffer 104 is erased when the branch destination of the branch instruction is determined and the instruction execution is completed, or when the speculatively executed instruction is invalidated.

The arithmetic unit 105 extracts an operand required for the received instruction from the renaming register 106 or the register 107, executes the arithmetic operation, and writes the data of the arithmetic result into the renaming register 106 or the register 107. Renaming register 106
Is a register for temporarily saving the register update value during speculative execution. The register 107 is a register that can be referred to by a program.

The detection circuit 109 includes a reorder buffer 10
4 detects that there are no free entries, that is, the reorder buffer 104 is full, and the reorder buffer full signal 121 is sent to the reorder buffer full determination circuit 1
Output to 10. The detailed configuration of the detection circuit 109 will be described later.

The reorder buffer full determination circuit 110 is
When the reorder buffer full signal 121 is continuously received for a fixed clock time or longer from the detection circuit 109, it is determined that the reorder buffer 104 is full, and the reorder buffer full detection signal 12 is determined to be full.
2 is output to the reorder buffer full counter circuit 111. The detailed configuration of the reorder buffer full determination circuit 110 will be described later.

Reorder buffer full counter circuit 111
Counts the number of times the reorder buffer full detection signal 122 is received, and outputs the interrupt request signal 124 or the hardware stop request signal 123 according to the counted value. The reorder buffer full counter circuit 1
The detailed configuration of 11 will be described later.

The detection circuit 112 detects that the reservation station 103 is full. The reservation station full determination circuit 113 includes the detection circuit 1
When 12 indicates that the reservation station 103 is full for a certain clock period or more, it is determined that the reservation station 103 is full. The reservation station full counter circuit 114 counts the number of times that the reservation station 103 is determined to be full, and outputs an interrupt request signal 126 or a hardware stop request signal 125 according to the counted value.

When the hardware stop circuit 115 receives the hardware stop request signals 123 and 125,
The normal arithmetic operation of the hardware including this processor is stopped.

When the interrupt / exception processing circuit 116 receives the interrupt request signals 124 and 126, it causes an internal interrupt or exception to this processor,
When this is accepted, a predetermined interrupt process is performed.
Note that “exception” is included in an interrupt in a broad sense, and therefore “interrupt” includes “exception”.

The OR circuit 117 takes the logical sum of the hardware stop request signals 123 and 125 and supplies it to the hardware stop circuit 115. The OR circuit 118 takes the logical sum of the interrupt request signals 124 and 126 to generate an interrupt /
It is supplied to the exception processing circuit 116.

The instruction tracer 119 has a FIFO (First
In First Out) buffer, it stores information about issued instructions in the order in which they were actually issued. When the instruction tracer 119 also receives the hardware stop request signals 123 and 125, it outputs their contents to the outside.

FIG. 2 is a diagram showing the configuration of the detection circuit 109 of FIG. As shown in FIG. 2, the reorder buffer 10
4 is a Valid-bit 20 indicating whether each entry is valid or invalid
1 and the detection circuit 109 has all Valid-bi
It is configured by an AND circuit 202 that takes the logical product of t201. The detection circuit 109 (AND circuit 202) outputs the reorder buffer full signal 121 when the Valid-bits 201 of all entries are valid.

FIG. 3 is a diagram showing the configuration of the reorder buffer full determination circuit 110 of FIG. As shown in FIG.
The reorder buffer full determination circuit 110 includes a full detection count 301, a full detection counter 302, and a comparator 30.
3, a countdown circuit 304, and a multiplexer 3
05 and a selector 306.

The full detection count 301 is composed of a flip-flop whose initial value can be set, and how many clock times the reorder buffer full signal 121 is stored.
Is used to determine if the reorder buffer 104 is full. The full detection counter 302 is a counter used to determine that the reorder buffer 104 is full when the reorder buffer 104 is full for the clock period set in the full detection count 301.

The comparator 303 has a full detection counter 302.
Is compared with "all0", and if they match, the full detection counter zero signal 321 is output. The countdown circuit 304, when selected by the multiplexer 305, counts down the value of the full detection counter 302 at each clock timing.

The multiplexer 305 selects the countdown circuit 302 to count down the full detection counter 302 while the reorder buffer full signal 121 is input, and when the reorder buffer full signal 121 is not input, the full detection is performed. The count 301 is selected to initialize the value of the full detection counter 302. The multiplexer 305 also receives the full detection counter zero signal 3
When 21 is input, the full detection counter 30
A signal for holding the value of 2 is selected.

The selector 306 selects the full detection counter zero signal 321 output from the comparator 303 when the reorder buffer full signal 121 is input, and selects "0" otherwise. As a result, when the reorder buffer 104 is full for a certain period of time, the reorder buffer full detection signal 122 is output to the reorder buffer full counter circuit 111.

FIG. 4 is a diagram showing the configuration of the reorder buffer full counter circuit 111 of FIG. The reorder buffer full counter circuit 111 includes a reorder buffer 110.
Can be roughly divided into a circuit that counts the number of times that is determined to be full and a circuit that counts the timing of generating an interrupt.

As shown in FIG. 4, the reorder buffer full counter circuit 111 includes a reorder buffer full counter 403 and a count-up circuit 40 as the former circuit.
4, hardware stop / interrupt occurrence count 405, comparator 406, hardware stop suppression 407, EIF
408, a selector 409, a NOT circuit 410, A
And an ND circuit 411. On the other hand, as the latter circuit, the countdown circuit 412 and the multiplexer 41 are provided.
3, an interrupt counter 414, and a comparator 415. Hardware stop / interrupt occurrence count 405
Is also used as the latter circuit.

The reorder buffer full counter 403 is
This counter is used to stop the hardware when it is determined that the reorder buffer 104 is full for the clock period set in the hardware stop / interrupt generation count 405. Count-up circuit 4
04, when selected by the selector 409, causes the reorder buffer full counter 403 to count up at each clock timing.

Hardware stop / interrupt generation count 405
Is configured by a flip-flop whose initial value can be set, and determines how many times the value of the reorder buffer full counter 403 stops the hardware and how many times the value of the interrupt counter 414 causes an interrupt. Used to make a decision.

The comparator 406 compares the value of the reorder buffer full counter 403 with the value of the hardware stop / interrupt occurrence count 405, and outputs a full count match signal 421 when they match.

The hardware stop inhibition 407 is composed of a flip-flop that can be initialized, and determines whether or not to stop the hardware when the full count match signal 421 is output from the comparator 406. The value set in the hardware stop suppression 407 is the NOT circuit 410
It is input to the AND circuit 411 via, and the operation of the hardware is not stopped when the set value is “1”, and the operation of the hardware is stopped only when the set value is set to “0”. It has become.

Once the high level (value "1") signal is output from the AND circuit 411, the EIF 408 holds the value and outputs it as the hardware stop request signal 123 to stop the hardware stop shown in FIG. Output to the circuit 113 and the instruction tracer 119.

The selector 409 selects the count-up circuit 404 while the reorder buffer full detection signal 122 is input, and selects the reorder buffer full counter 40.
When 3 is counted up and the reorder buffer full detection signal 122 is not input, a signal for holding the value of the reorder buffer full counter 403 is selected.

The countdown circuit 412 includes the selector 4
When it is selected by 13, the interrupt counter 414 is counted down at every clock timing. The interrupt counter 414 is the reorder buffer 10
3 is a counter used to output the interrupt request signal 124 when it is determined that the hardware stop / interrupt generation count 405 is full for the clock period set. The comparator 415 compares the content of the interrupt counter 414 with “all0” and outputs the interrupt request signal 124 when they match.

While the reorder buffer full detection signal 122 is being input, the multiplexer 413 selects the countdown circuit 412 to count down the interrupt counter 414, and the reorder buffer full detection signal 1
When 22 is not input, the hardware stop / interrupt occurrence count 405 is selected and the interrupt counter 414 is selected.
Initialize the value of. The multiplexer 413 also selects a signal for holding the value of the interrupt counter 414 when the interrupt request signal 124 is input.

The reservation station 103
Of the detection circuit 112, the reservation station full determination circuit 113, and the reservation station full counter circuit 114, which detect whether or not the memory is full, are the same as the detection circuit 109, the reorder buffer full determination circuit 110, and the reorder buffer full counter circuit 111, respectively. Substantially the same.

The operation of the processor according to this embodiment will be described below.

First, when an instruction is read from the instruction cache 101, the instruction decoder 102 decodes the instruction. When the instruction decoder 102 decodes the instruction, the instruction decoder 102 outputs information about the instruction including the decoding result to the reservation station 103 and the reorder buffer 1.
04 and so on.

The reservation station 103 determines that an instruction having no register dependency with other instructions among the registered instructions can be executed regardless of the order in which the instructions appear in the program, and the arithmetic unit 105 Issue the command to the. The arithmetic unit 105 extracts a necessary operand from the renaming register 106 or the register 107 for the instruction issued from the reservation station 103, executes the arithmetic operation, and outputs the arithmetic result to the register 107 (in some cases, renaming). Write to register 106).

On the other hand, the reservation station 103
When the branch instruction is issued from, the branch destination of the branch instruction is predicted, and the instructions after the predicted branch destination are sequentially read from the instruction cache 101. Similarly, an instruction to be executed after branch prediction is also decoded by the instruction decoder 102, and information is registered in the reservation station 103 and the reorder buffer 104. Further, the reservation station 103 issues a command, and the calculator 105 executes the calculation.

However, when the speculative execution of the instruction is performed by the branch prediction, each speculatively executed instruction and the updated number of the renaming register 106 are stored in the reorder buffer 10.
Written to 4. After that, when the branch destination of the branch instruction from which the speculative execution is started is fixed and the branch prediction is successful, the operation written in the renaming register 106 based on the information registered in the reorder buffer 104. The resulting data is written back to the register 107. This completes the execution of the instruction.

On the other hand, if the branch prediction fails, the data written in the renaming register 106 is invalidated, and the instructions after the confirmed actual branch destination are read from the instruction cache 101. When the execution of the speculatively executed instruction is completed or the data of the operation result is invalidated by the speculative execution, the reorder buffer 10
The information related to the instruction registered in 4 is cleared.

In parallel with the sequential execution of the instructions in the program as described above, whether performance is efficiently executed in this processor regardless of the order of appearance of the instructions including speculative execution. Actions are performed to evaluate. The operations of the detection circuit 109, the reorder buffer full determination circuit 110, and the reorder buffer full counter circuit 111 for this purpose will be described by taking the case of the timing chart of FIG. 5 as an example.

First, in the time slot T0, the detection circuit 109 detects that there is an empty entry in the reorder buffer 104, and the reorder buffer full signal 121.
Is not output. In this case, time slot T
In 0 to T1, when the value of the full detection counter 301 is “2”, the full detection counter 302 continues to hold the value.

Next, at time slot T1, when the detection circuit 109 detects that the reorder buffer 104 is full, a reorder buffer full signal 121 is output. As a result, in the time slot T2, the full detection counter 302 causes the reorder buffer full signal 12
By inputting 1, the value changes from "2" to "1"
Is counted down.

Next, in the time slot T2, when the detection circuit 109 detects again that there is an empty entry in the reorder buffer 104, the multiplexer 305.
Selects the output of full detection count 301. As a result, at time slot T3, the reorder buffer full signal 121 is no longer input, and the value of the full detection counter 302 is returned to the initial value "2".

Next, if the detection circuit 109 continues to detect that the reorder buffer 104 is full during the time slots T4 to T6, the full detection counter 3
The value of 02 continues to count down. Then, when the value becomes "0" in the time slot T5, the full detection counter zero signal 321 is output from the comparator 303 in the time slot T6. Also, the time slot T6
Then, since the reorder buffer full signal 121 and the full detection counter 0 signal 321 are input to the multiplexer 305, the value of the full detection counter 302 remains held at “0”. In this way, the reorder buffer full determination circuit 111 determines that the reorder buffer 104 is full only when a fixed clock time has elapsed.

Next, it is assumed that the reorder buffer full signal 121 and the reorder buffer full detection signal 122 continue to be output in the time slots T6 to T7. During this period, the value of the reorder buffer full counter 403 is counted up to "2", and at the same time, the value of the interrupt counter 414 is counted down to "0".

Next, at time slot T8, the detection circuit 109 again detects that there is a free entry in the reorder buffer. As a result, the reorder buffer full signal 121 is not output, the reorder buffer full detection signal 122 is not input, and the value of the reorder buffer full counter 403 is held at “2”. Furthermore, the reorder buffer full signal 121
Is input, the multiplexer 305 selects the output of the full detection count 301, and the full detection counter 3
The value of 02 is initialized to "2". After that, it waits for the time slots T9, T10, ... And the input of the reorder buffer full signal 121 again.

Here, the reorder buffer full counter 4
The value of 03 is the hardware stop / interrupt occurrence count 405.
When it matches the value of, the full count match signal 421 is output. Here, if the hardware stop inhibition 407 is not in the stop inhibition state (value "1"), the output of the AND circuit 411 becomes high level (value "1"), and EI
The hardware stop signal 123 is output from F408. The EIF 408 once outputs the hardware stop signal 123.
When is input, this output state is held.

By inputting the hardware stop signal 123 from the EIF 408 to the hardware stop circuit 115 and the instruction tracer 119 in this way, the normal arithmetic operation of the hardware is stopped, and the data stored in the instruction tracer 119 is externally stored. Is output to. Further, in this state, the value of the flip-flop that can be read from the outside or the value registered in the instruction tracer may be read to the outside.
In this way, it is possible to find out the cause of how full the reorder buffer 104 is based on the data output to the outside.

On the other hand, in the time slot T7, the value of the interrupt counter 413 becomes "0", and the interrupt request signal 124 is output to the interrupt / exception processing circuit 114. Here, if the hardware stop inhibition 407 is in the stop inhibition state (value “0”) and the interrupt for the interrupt request signal 124 is not masked, the interrupt / exception processing circuit 114 determines that the processor Generate an interrupt to.

When the generated interrupt is accepted, the interrupt / exception processing circuit 114 can detect the full state of the reservation station 103 and / or the reorder buffer 104 in real time by executing a predetermined interrupt processing routine. it can.

Further, in the time slot T8, the multiplexer 412 selects the value of the stop / interrupt count 405 as an output according to the output of the comparator 414.
As a result, the value of the interrupt counter 414 is initialized to "2", the interrupt request signal 124 is not output, and the normal arithmetic operation is resumed.

The operations of the detection circuit 112, the reservation station full determination circuit 113, and the reservation station full counter circuit 114 are performed by the detection circuit 109 and the reorder buffer full determination circuit 11, respectively.
0, which is substantially the same as the operation of the reorder buffer full counter circuit 111.

As described above, when the hardware stop request signals 123 and 125 are output and input to the hardware stop circuit 115 and the instruction tracer 119 via the OR circuit 117, the hardware stop circuit 115 determines that the processor The normal calculation operation by is stopped. Also,
The contents of the data stored in the instruction tracer 119 and other contents are output to the outside.

On the other hand, when the interrupt request signals 124 and 126 are output and input to the interrupt / exception processing circuit 116 via the OR circuit 118, the interrupt / exception processing circuit 116 issues an interrupt to this processor. . Then, when this interrupt is accepted, as the interrupt process, for example, the fact that the reorder buffer 104 or the reservation station 104 is full is notified to the outside.

As described above, in the processor according to this embodiment, the reorder buffer 104 and / or
Alternatively, when the reservation station 103 is full, the operation of the hardware can be stopped and the data of the instruction tracer 119 and other data can be output to the outside. Further, the occurrence of the interrupt can output to the outside that the reorder buffer 104 and / or the reservation station 103 are full.

As a result, when the instructions in the program are executed regardless of the order of appearance, including the speculative execution, the reservation station 103 and the reorder buffer 104 are found to be full,
In addition, it is possible to find out under what circumstances it was full. Therefore, in the processor according to the present embodiment, it is possible to appropriately perform performance evaluation as to whether or not execution is efficiently performed regardless of the order of appearance of instructions in the program.

Further, in the processor according to this embodiment, the reorder buffer full determination circuit 110 and the reservation station full determination circuit 113 detect that the reorder buffer 104 and the reservation station 103 are full in the set clock period, respectively. Only when they are determined to be full. For this reason, it becomes possible to observe only the places where they are likely to continue to be full and affect the performance of the processor.

Since the hardware stop inhibition 407 is provided, the reservation station 103 and / or the reorder buffer 104 can be found to be full without stopping the operation of the hardware. You can check the number of clocks that are full, and you can understand the difference in characteristics between programs.

Hardware stop / interrupt count 40
By providing 5, it is possible to stop the operation of the hardware or generate an interrupt at an arbitrary timing.

In the above embodiment, the detection circuit 109,
Although the operations of the reorder buffer full determination circuit 110 and the reorder buffer full counter circuit 111 have been described according to the timing chart of FIG. 5, the operations of these circuits are not limited to the case of the timing chart of FIG.

In the above embodiment, the processing executed when the count value of the reorder buffer full counter circuit 111 or the reservation station full counter circuit 114 reaches a predetermined value is the hardware stop circuit 1.
Hardware stop by 15 and instruction tracer 1
The contents of 19 are read out or an interrupt is generated by the interrupt / exception processing circuit 116. However, it is possible to perform other processing as the full processing in such a situation.

In the above embodiment, the processor having both the reservation station 103 and the reorder buffer 104 has been described as an example. However,
The present invention can be applied to a processor having only one of a reservation station and a reorder buffer.

[0080]

As described above, according to the present invention,
In a processor equipped with a buffer that temporarily stores information about instructions fetched from a storage device in order to execute instructions in a program regardless of the order in which they appear, whether or not they are efficiently executed regardless of the order in which they appear. Performance evaluation is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an entire processor according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a detection circuit of FIG.

3 is a diagram showing a configuration of a reorder buffer full determination circuit of FIG.

FIG. 4 is a diagram showing a configuration of a reorder buffer full counter circuit of FIG.

FIG. 5 is a timing chart showing an operation of the processor according to the exemplary embodiment of the present invention.

[Explanation of symbols]

101 instruction cache 102 Instruction decoder 103 reservation station 104 reorder buffer 105 arithmetic unit 106 renaming register 107 registers 109 detection circuit 110 Reorder buffer full judgment circuit 111 Reorder buffer full counter circuit 112 detection circuit 113 Reservation station full judgment circuit 114 Reservation Station Full Counter Circuit 115 Hardware stop circuit 116 Interrupt / Exception Processing Circuit 117 OR circuit 118 OR circuit 119 Command Tracer

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Claims (10)

(57) [Claims] 1. A buffer for temporarily storing information on an instruction fetched from a storage device for executing instructions in a program regardless of the order of appearance, and a buffer for storing the information on the instruction to fill the buffer. A fullness determining means for determining whether or not there is a fullness, a fullness number counting means for counting the number of times the fullness determination means determines fullness, and a fullness for performing a predetermined fullness processing according to the number of times the fullness counting means counts. A processor comprising: a processing unit. 2. The processor according to claim 1, wherein the fullness determining means determines that the buffer is full when the buffer is full for a predetermined time or more. 3. The processor according to claim 1, wherein the full processing means includes means for stopping the operation of the processor. 4. When an instruction temporarily stored in the buffer is issued or when the execution of the instruction is completed,
The method further includes: a registration unit that registers information about the issued or completed instruction, and a unit that outputs information about the instruction registered in the registration unit to the outside when the operation of the processor is stopped by the full processing unit. The processor of claim 3 characterized. 5. The processor according to claim 1, wherein the full processing means includes means for generating a predetermined interrupt to the processor. 6. A means for outputting the operating state of at least one of said fullness determining means and said fullness counting circuit to the outside when said fullness processing means generates an interrupt to said processor. The processor of claim 5 characterized. 7. The buffer includes an entry bit indicating whether or not each entry is valid, and the processor performs a logical operation on values of all entry bits included in the buffer to fill the buffer. 3. The method according to claim 1, further comprising detection means for detecting whether or not the buffer is full, and the fullness determination means determines whether or not the buffer is full based on a result of a logical operation by the detection means. 7. The processor according to any one of items 1 to 6. 8. The reorder buffer, wherein the buffer holds a decoding result of an instruction fetched from a storage device until execution of the instruction is completed, and / or a decoding result of the instruction fetched from the storage device is stored by the instruction. 8. Processor according to any one of the preceding claims, characterized in that it is constituted by a reservation station which holds it until issued. 9. A method for evaluating the performance of a processor, comprising a buffer for temporarily storing information on an instruction fetched from a storage device for executing an instruction in a program regardless of the order of appearance, and storing the information on the instruction. Accordingly, a fullness determination step of determining whether or not the buffer is full, and a fullness control that causes the processor to perform a predetermined process according to the number of times that the buffer is determined to be full in the fullness determination step. A method of evaluating performance of a processor, comprising: 10. The processor performance evaluation method according to claim 9, wherein the fullness determining step determines that the buffer is full when the buffer is full for a predetermined time or more. .