JP3442916B2 - Thin film semiconductor device and liquid crystal display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device, and more particularly to a CMOS structure thin film transistor used in an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art Display devices such as electroluminescence, light emitting diode, plasma, fluorescent display, and liquid crystal can have a thin display section, and are used for display devices such as office equipment and computers or special display devices. As the demand is rising.

Among these display devices, a thin film transistor (Thin Film Transistor):
An active matrix liquid crystal display (Active Ma) using a TFT as a pixel switching element.
trix-Liquid Crystal Displ
ay: AM-LCD) is expected as a display with high image quality, high quality, and low power consumption, and research and development are being conducted by various companies.

Pol using polycrystalline silicon (poly-Si) as a channel active layer of a TFT for AM-LCD
The y-SiTFT has high mobility, and when applied to a pixel TFT, it can be made finer and can be used not only as a pixel switching element but also as a peripheral driving circuit for controlling the pixel TFT. Therefore, poly-
The SiTFT has an advantage that the peripheral drive circuit section can be formed at the same time as the pixel section (drive circuit integrated LCD), and the mounting cost of the drive circuit chip can be reduced and the frame can be narrowed.

LC integrated with a drive circuit currently on the market
D is a small and medium-sized display used for a projection type display and a viewfinder. The manufacturing process uses a solid-phase growth method (600 ° C. process) for forming the poly-Si film and thermal oxidation (900 ° C. or higher process) for forming the oxide film, and therefore involves a high temperature process. It will be. Therefore, it is required to use a quartz substrate or a high heat resistant substrate. Such a quartz substrate or a high heat-resistant substrate is expensive, which causes a high cost.

On the other hand, a-Si (amorphous silicon)
Since the TFTLCD is formed by a low temperature process of 450 ° C. or lower (a temperature that the glass substrate can withstand), a low-cost large area glass substrate can be used. Therefore, if the poly-Si film forming step and the gate oxide film forming step, which are usually high-temperature processes, and the impurity activating step can be formed by the above-mentioned low-temperature process, multi-chamfering of an LCD panel,
The advantages such as cost reduction and throughput improvement are extremely large.

Excimer laser annealing (EL) is used as a poly-Si film forming technique and an impurity activating technique in a low temperature process.
The method according to A) is being studied. According to this method,
Since the a-Si film is instantly melted and crystallized by the irradiation of the excimer laser, the substrate is less damaged by heat and a low-cost glass substrate can be used.

By the way, in order to form the drive circuit at the same time as the pixel portion, it is necessary to form the drive circuit by a thin film transistor similar to the pixel TFT. In addition, a driving circuit including a CMOS circuit is required for low power consumption.

Here, the structure and manufacturing process for simultaneously forming an n-channel TFT and a p-channel TFT by using a CMOS circuit as a driving circuit formed of thin film transistors will be described below.

First, C of a general poly-Si TFT
The cross-sectional structure of the MOS circuit TFT will be described with reference to FIG. That is, a transparent insulating film 1001 is formed on the transparent insulating substrate 1.
Are coated on the high resistance semiconductor layers 1002a and 1002b and the low resistance semiconductor layer 10 which are active layers.
03a, 1003b, 1004a, 1004b.
These semiconductor layers are dehydrogenated by forming an a-Si: H film with a thickness of 50 nm on the insulating film 1001 by, for example, a plasma CVD method and subjecting the a-Si: H film to thermal annealing. And then ELA aS
It is formed by converting the i film into poly-Si.

When a glass substrate is used, in order to suppress diffusion of sodium ions etc. from the glass substrate,
It is common to form a base film as an undercoat instead of directly forming an active layer on a substrate.

Impurities such as phosphorus (P) are implanted into the low resistance semiconductor layers 1003a and 1004a and then activated by heat or the like. On the other hand, the low resistance semiconductor layer 1003
Impurities such as boron (B) are implanted into b and 1004b, and then activated by heat or the like.

A gate insulating film 1 having a thickness of 70 nm to 100 nm is formed on the high resistance semiconductor layers 1002a and 1002b.
005 is APCVD, PECVD, ECR-PECV
D and the like. This gate insulating film 100
5, gate electrodes 1009a and 1009b are provided.

Low resistance semiconductor layers 1003a, 1003b,
The source electrode 1 is provided on each of 1004a and 1004b.
006a, 1006b, drain electrodes 1007a, 10
07b is connected. In addition, the gate electrode 1009a
An interlayer insulating film 1008 is provided to insulate the source / drain electrodes. The transparent insulating film 1001 is an undercoat for preventing contamination of the thin film transistor from the glass substrate.

In the structure described above, the low resistance semiconductor layer 1
003a, 1004a and low resistance semiconductor layers 1003b, 1
Since different impurities are implanted into 004b, it is necessary to separate the impurities.

This step will be described with reference to FIGS. 8 and 9. First, the semiconductor layer 1002 is formed over the substrate 1, patterned, and then the gate insulating film 1005 is formed, and then a film to be the gate electrode 1009 is formed (FIG. 8).
(A)). Then, the gate electrodes 1009a and 1009b
Is patterned (FIG. 8B).

Next, for example, a resist film or an aluminum film to be a mask material 1020a for implanting impurities is formed in a portion to be a p-channel TFT, and then patterned, and impurities are implanted using this mask material 1020a. Then, for example, phosphorus (P) is applied to the portion to be the n-channel TFT.
And the like are injected (FIG. 8C). And the mask material 10
20a is removed (FIG.8 (d)).

Then, in order to form the p-channel side,
A mask material 1020b is formed on the n-channel side in the same manner as in the step shown in FIG. 8C, impurities are implanted, and the p-channel T
For example, boron (B) or the like is injected into the portion to be the FT (FIG. 9A), and the mask material 1020b is removed (FIG. 9).
(B)).

After that, an interlayer insulating film is formed, contact holes are opened, and source / drain electrodes are formed.
The TFT circuit of the OS is completed (FIG. 9 (c)). But,
When a CMOS circuit is formed by the above steps,
There were the following problems.

First, when resist or aluminum is used as a mask material in the impurity implantation step, heat and impurities generated at that time are injected into the mask material by the impurity implantation step, and as a result, the mask material itself is altered. However, the removal process becomes complicated. In addition, a TFT defect occurs due to the residue after removing the mask material, and the TFT can be efficiently used.
Therefore, the CMOS circuit cannot be formed.

Furthermore, since the active layer on the p-channel side and the active layer on the n-channel side are present in the same layer, if these active layers are too close to each other, it causes a short circuit. However, there is a problem that high integration is difficult.

[0022]

SUMMARY OF THE INVENTION The present invention solves the problems that occur when a CMOS circuit is formed by a conventional method, makes it possible to perform an impurity implantation step without using a mask material, and It is an object to provide a thin film semiconductor device that can be integrated. Another object of the present invention is to provide a liquid crystal display device including the thin film semiconductor device.

[0023]

In order to solve the above problems, the present invention (claim 1) provides a transparent insulating substrate, a first semiconductor film selectively formed on the transparent insulating substrate, and A first channel region of a first conductivity type formed in the first semiconductor film, and a first drain region of a second conductivity type and a first drain region formed on both sides of the first channel region.
Source region, a first insulating film formed on the first semiconductor film and the transparent insulating substrate, and a first insulating film formed on a portion of the first insulating film on the first channel region. 1
Gate electrode, a second semiconductor film formed on the first insulating film on the transparent insulating substrate, and a second conductivity type second channel formed on the second semiconductor film. And a first region formed on each side of the second channel region.
A conductive type second drain region and a second source region, a second insulating film formed so as to cover the gate electrode and the second semiconductor film, and a second insulating film A second gate formed on the portion above the second channel region.
And a first electrode, the first channel region, the first channel region,
Drain region, the first source region, and the first
A second thin film transistor is formed by the second channel region, the second drain region, the second source region, and the second gate electrode. The first insulating film constitutes a gate insulating film of the first thin film transistor, the second insulating film constitutes a gate insulating film of the second thin film transistor, and There is provided a thin film semiconductor device characterized by comprising an interlayer insulating film of the thin film transistor of No. 1.

In the above thin film semiconductor device, the first and second semiconductor layers are composed of polycrystalline silicon. Further, the present invention (Claim 3) provides a liquid crystal display device using the thin film semiconductor device as a drive circuit.

According to the present invention, 2 having different electrical conductivity
In the case of forming a thin film transistor (TFT) of a type, by forming semiconductor layers to be channel layers in layers (first and second semiconductor layers) of different levels, it is unnecessary in the impurity implantation process. Provided is a thin film semiconductor device having a structure capable of efficiently forming both channel TFTs without forming a mask material for not injecting impurities into places.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. According to an embodiment of the present invention, a CMOS circuit is used as a driving circuit using thin film transistors, and n
The structure and manufacturing process for simultaneously forming the channel TFT and the p-channel TFT will be described below.

First, a poly- according to an embodiment of the present invention
The cross-sectional structure of the CMOS circuit TFT of SiTFT will be described with reference to FIG. That is, a transparent insulating film 101 is coated on a transparent insulating substrate 1, and a high resistance semiconductor layer 102a and a low resistance which are active layers of a first thin film transistor (TFT), for example, a p-channel transistor, are formed on the transparent insulating film 101. There are semiconductor layers 103a and 103b. For these semiconductor layers, an a-Si: H film having a thickness of 50 nm is formed on the insulating film 101 by, for example, a plasma CVD method.
Dehydrogenation is performed by subjecting the -Si: H film to thermal annealing, and then the a-Si film is poly-doped by ELA.
-Si is formed.

When a glass substrate is used, in order to suppress diffusion of sodium ions and the like from the glass substrate, it is common to form an undercoating base film on the substrate instead of directly forming the active layer. Is.

In the low resistance semiconductor layers 103a and 104a,
After impurities such as boron (B) are implanted, they are activated by heat or the like. A gate insulating film 105 having a thickness of 70 nm to 100 nm is formed on the high resistance semiconductor layer 102a.
a is formed by APCVD, PECVD, ECR-PECVD, or the like. A gate electrode 109a is provided on the gate insulating film 105a.

A source electrode 106a and a drain electrode 107 are formed on the low-resistance semiconductor layers 103a and 104a, respectively.
a is connected. In order to insulate the gate electrode 109a from the source / drain electrodes, the interlayer insulating film 108 is formed.
a and 112 are provided. The transparent insulating film 101 is an undercoat for preventing contamination of the thin film transistor from the glass substrate.

Further, the second thin film transistor (TF
T) For example, in an n-channel transistor, the high resistance semiconductor layer 102 which is an active layer is formed on the insulating film 111 formed at the same time as the gate insulating film 105a of the first transistor.
b, and low resistance semiconductor layers 103b and 104b. These semiconductor layers are formed on the insulating film 111 by, for example, plasma C
An a-Si: H film is formed to a thickness of 50 nm by the VD method, and this a-Si: H film is subjected to thermal annealing for dehydrogenation, and then the a-Si film is subjected to poly-Si by ELA. It can be formed by converting.

The low resistance semiconductor layers 103b and 104b include
After implantation of impurities such as phosphorus (P), it is activated by heat or the like. 7 is formed on the high resistance semiconductor layer 102b.
The gate insulating film 105b having a thickness of 0 nm to 100 nm is
It is formed by APCVD, PECVD, ECR-PECVD, or the like. A gate electrode 109b is provided on the gate insulating film 105b.

A source electrode 106b and a drain electrode 107 are formed on the low resistance semiconductor layers 103b and 104b, respectively.
b is connected. Further, in order to insulate the gate electrode 109b and the source / drain electrodes, the interlayer insulating film 1 is formed.
08b is provided.

Since different impurities are injected into the low resistance semiconductor layers 103a and 104a and the low resistance semiconductor layers 103b and 104b, the implantation process will be described with reference to FIG.

First, the first TFT is formed on the transparent insulating substrate 1.
After the semiconductor layer 102a is formed and patterned, the gate insulating film 105a is formed thereon (FIG. 2).
(A)). The gate insulating film 105a is also the layer 111 below the active layer of the second TFT.

Next, the gate electrode 109a is formed (FIG. 2B). Then, the semiconductor layer 10 of the second TFT
2b is formed and patterned (FIG. 2C). Then, the gate insulating film 105b is formed. The gate insulating film 105b is a layer 112 that becomes an interlayer insulating layer of the first TFT.
However (Fig. 2 (d)).

Next, the implantation amount and the acceleration energy are adjusted and implanted so that impurities such as phosphorus are just introduced into the low resistance semiconductor layer of the second TFT on the entire surface, and the implantation is performed. 103b and 104b are formed (FIG. 3A). Similarly, impurities such as boron are the first TF.
As just introduced into the low resistance semiconductor layer of T,
The implantation amount and the acceleration energy are adjusted and the implantation is performed to form the low resistance semiconductor layers 103a and 104a (FIG. 3).
(B)). In this way, the low resistance semiconductor layers 103a and 104 of different conductivity types are used without using a mask material.
a, 103b and 104b are formed (FIG. 3C).

In the present embodiment, the implantation amount of phosphorus into the low resistance semiconductor layer of the second TFT is 5 × 10 ¹⁵ / cm ² ,
The acceleration energy is 80 to 100 keV, and the implantation amount of phosphorus into the low resistance semiconductor layer of the first transistor is 5 × 10 5.
¹⁵ / cm ² , acceleration energy is 80 to 150 keVke
It was V.

After that, an interlayer insulating film is formed, contact holes are formed, and source / drain electrodes are formed. CM
The OS TFT circuit is completed (FIG. 10). As described above, when two types of TFTs having a CMOS structure are formed, different semiconductor layers serving as channel layers are formed in different layers, thereby performing different implantation of impurities without using a mask material. It is possible.

4 (a), (b) and (c) show the case where the impurity implantation step is performed in the order of boron and phosphorus, which is the reverse of the above. In this case, in the first TFT, since the acceleration energy of phosphorus to be injected later is low, phosphorus does not penetrate through the low resistance semiconductor layer, so that crystal damage is small and phosphorus is activated. It has the advantage that it requires less heat.

FIGS. 5A and 5B show a case where boron and phosphorus are simultaneously implanted in the impurity implantation step,
In this case, there is an advantage that the injection step may be one step.
In this method, since the atomic weight of phosphorus is about three times the atomic weight of boron, even if ions are simultaneously implanted with the same acceleration energy, phosphorus is implanted into the low resistance semiconductor layer of the first TFT, Boron is injected into the low resistance semiconductor layer of the second TFT, so that different impurities can be implanted separately.

As described above, the CMO by the TFT
In the case of forming two TFTs having channel layers of different conductivity in the S structure, by forming semiconductor layers to be channel layers in different layers at different levels, it is unnecessary in the impurity implantation step. The TFTs of both channels can be efficiently formed without forming a mask material for not injecting impurities into the place.

The structure and manufacturing method of the liquid crystal display device according to one embodiment of the present invention have been described above, and the effects thereof will be described below. FIG. 6 shows a comparison between the structural example (a) of the present invention and the structural example (b) of the conventional method. Figure 6
As can be seen from the comparison between FIG. 6A and FIG.
When it is necessary to connect the source electrode and the drain electrode of the two types of TFTs that compose the above, it is necessary to directly connect the n-type low resistance semiconductor layer and the p-type low resistance semiconductor layer to the p-type low resistance semiconductor layer.
Since an n-junction is formed, it is general to connect some kind of metal between them.

In such a case, in the conventional structure in which the semiconductor layers are in the same layer, there is a problem such as a short circuit unless the n-type low-resistance semiconductor layer and the p-type low-resistance semiconductor layer are in direct contact with each other, for example, 5 μm. There has occurred. However, since the semiconductor layers can be insulated via the insulating film as in the present invention, the semiconductor layers can be arranged close to each other (for example, 1.25 μm), and high integration can be achieved. Especially when applied to the peripheral drive circuit of a liquid crystal display device,
It is possible to narrow the frame.

Further, in the CMOS structure of the liquid crystal display device of the present invention, since the active layers of the two TFTs are at different levels, there is an advantage that the film quality and film thickness of each active layer can be controlled independently.

For example, when different impurities are ion-implanted into the p-channel and the n-channel during channel doping,
Ion implantation can be performed in the state of a solid film, that is, before patterning the active layer. When ion implantation is performed after patterning the active layer, the subsequent laser annealing is performed.
The shape of the active layer collapses during the curing, but such a problem does not occur at all when the solid film is used.

In some cases, the active layer of the TFT needs to be formed of doped polysilicon. In this case, the active layer of the first TFT and the active layer of the second TFT are different from each other in impurity. Due to the doped polysilicon,
It is possible to form each independently.

Furthermore, the active layer of the first TFT and the second TF
The optimum film thickness may differ from the active layer of T, but even in such a case, each film thickness can be controlled independently.

Furthermore, since the Cs electrode can be shared with the gate electrodes of the respective TFTs, the impurity introducing step for Cs becomes unnecessary. The pixel TFT may have an LDD structure in order to reduce the leak current (current that flows when the TFT is OFF), or may be a multi-gate (double-gate) TFT having a plurality of gate electrodes.

In the above embodiments, the coplanar type TFT has been described, but various modifications such as application to an image sensor or an X-ray sensor are possible without departing from the scope of the present invention.

[0051]

As described above, according to the present invention,
When forming two types of TFTs having different conductivity, since the semiconductor layers to be the channel layers are formed on the layers of different levels, a mask material is formed to prevent impurities from being injected into unnecessary locations. It is possible to separate the impurities without doing so, and it is possible to efficiently form both channel TFTs.

[Brief description of drawings]

FIG. 1 is a sectional view showing a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the thin film transistor shown in FIG.

FIG. 3 is a cross-sectional view showing a manufacturing process of the thin film transistor shown in FIG.

4A to 4C are cross-sectional views showing another example of a manufacturing process of the thin film transistor shown in FIG.

FIG. 5 is a cross-sectional view showing still another example of the manufacturing process of the thin film transistor shown in FIG.

FIG. 6 is a cross-sectional view showing a thin film transistor having a CMOS structure according to the present invention and a thin film transistor having a conventional CMOS structure in comparison.

FIG. 7 is a cross-sectional view showing a thin film transistor according to a conventional technique.

FIG. 8 is a cross-sectional view showing a manufacturing process of the thin film transistor of FIG.

FIG. 9 is a cross-sectional view showing a manufacturing process of the thin film transistor of FIG.

10 is a CMOS TFT obtained by the process shown in FIG.
Sectional drawing which shows a circuit.

[Explanation of symbols]

1 ... Substrate, 1001, 101, 111 ... Base insulating film, 1
002a, 1002b, 102a, 102b ... Channel region, 1003a, 1003b, 103a, 103b ...
Source region, 1004a, 1004b, 104a, 10
4b ... Drain region 1005a, 1005b, 105
a, 105b ... Gate insulating film, 1006a, 1006
b, 106a, 106b ... Source electrode, 1007a, 1
007b, 107a, 107b ... Drain electrode, 100
8, 108a, 108b ... Interlayer insulating film, 112 ... Interlayer insulating film, 1009a, 1009b, 109a, 109b ...
Gate electrode.

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Claims (3)

(57) [Claims] 1. A transparent insulating substrate, a first semiconductor film selectively formed on the transparent insulating substrate, and a first conductivity type first channel region formed in the first semiconductor film. ,
The first drain region and the first source region of the second conductivity type formed on both sides of the first channel region respectively, and the first semiconductor film and the first drain region formed on the transparent insulating substrate. An insulating film, a first gate electrode formed on a portion of the first insulating film on the first channel region, and formed on the first insulating film on the transparent insulating substrate. A second semiconductor film, a second channel region of the second conductivity type formed in the second semiconductor film, and a second channel of the first conductivity type formed on both sides of the second channel region.
Second drain region and second source region, a second insulating film formed to cover the gate electrode and the second semiconductor film, and the second channel of the second insulating film. A second gate electrode formed on a portion on the region, the first channel region, the first drain region, the first source region, and the first gate region. The electrode constitutes a first thin film transistor, and the second channel region, the second drain region, the second source region, and the second gate electrode constitute a second thin film transistor. The first insulating film is the first
Forming a gate insulating film of the thin film transistor of
2. The thin film semiconductor device according to claim 1, wherein the insulating film forms a gate insulating film of the second thin film transistor and an interlayer insulating film of the first thin film transistor. 2. The thin film semiconductor device according to claim 1, wherein the first and second semiconductor layers are made of polycrystalline silicon. 3. A liquid crystal display device using the thin film semiconductor device according to claim 1 in a drive circuit.