JP3441140B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device using a nonvolatile memory cell in which a charge storage layer and a control gate are laminated.

[0002]

2. Description of the Related Art Recently, as a kind of semiconductor memory device, a floating gate (charge storage layer) is formed on a semiconductor substrate via an insulating film.
A non-volatile semiconductor memory device (EEPROM) using a non-volatile semiconductor memory cell in which a control gate and a control gate are stacked has attracted attention. In this EEPROM, the memory cells are arranged in a matrix form by arranging the memory cells at each intersection of the word line and the bit line. At this time, a word line is generally formed by the control gate, and a bit line is formed by contacting the Al wiring with the drain portion of each cell. However, in the EEPROM in which memory cells are connected in a matrix, various problems occur due to miniaturization.

For example, a NAND cell type EEPROM will be described below as an example. NAND cell type EEPRO
M is a NAND cell configured by connecting a plurality of memory cells in series, and the control gate of each memory cell is
The word line is shared by the memory cells on the adjacent sides with the element isolation interposed therebetween. In addition, wiring is connected to the drain side of each NAND cell via a selection transistor,
This wiring is shared in the direction orthogonal to the word line to form a bit line. Further, the source side of each NAND cell is connected to the source line in the direction parallel to the word line via the selection transistor.

Here, the NAN forming the matrix
In the D cell array, the contact portion (bit line contact portion) to the drain of each NAND cell is located directly beside the NAND cells adjacent in the word line direction. It is necessary to provide a margin in the contact portion in anticipation of the PEP shift, and the diffusion layer region of the contact portion must be increased. For this reason, the diffusion layer regions of the adjacent bit line contact portions become closer than the space between the adjacent bit lines, and the breakdown voltage between the adjacent NAND cells in the word line direction determines the rate of breakdown due to the breakdown voltage in this portion. However, there is a drawback that it becomes difficult to miniaturize the element isolation region.

Such a problem similarly occurs in another semiconductor memory device in which a plurality of memory cells are connected in series to form a memory cell unit, for example, a NAND type DRAM cell. For example, regarding the bit line contact position of a NAND type DRAM cell, as shown in FIGS. 3, 13, and 14 of Japanese Patent Laid-Open No. 4-147490, conventionally, adjacent bit line contacts are arranged in the word line direction. Are arranged in parallel with.

In the NAND cell type EEPROM, each NAND cell belongs to the same column to share a bit line, and those belonging to the same row share a source line to form an array. . At this time, in the conventional case, there is no element isolation region in the portion of the common source line, and the structure is such that the source diffusion layers of the source side select transistors of the NAND cells belonging to the same adjacent row are connected. The element isolation region is divided by the common source line.

In such a structure, the edge of the element isolation region may reach the source side select transistor,
This has been a cause of lowering the withstand voltage of the select transistor. FIG. 6 shows a conventional NAND cell array, but if the bent portion of the common source line is sagged as indicated by the broken line in the figure, this portion will be applied to the source side select transistor. In order to prevent this, increasing the distance between the common source and the gates of the source side select transistors leads to a reduction in the degree of integration.

Further, even when the phase shift method is used in the process of forming the resist pattern for forming the element isolation region, the phase shifter is abnormally arranged at the common source line, and thus the phase shift method is difficult to use. was there.

[0009]

As described above, in the conventional NAND cell type semiconductor memory device in which the arrays are arranged in a matrix, the withstand voltage between the memory cells is rate-controlled between the adjacent bit line contacts. There is a problem that it is difficult to reduce the element isolation region between the memory cells (in the word line direction).

Further, the element isolation region separating the memory cells from each other is interrupted at the common source line, and the NAN
When the D cell is used, the edge of the element isolation region sometimes touches the source side select transistor, which has been a cause of lowering the withstand voltage of the select transistor.

The present invention has been made in consideration of the above circumstances, and an object thereof is a semiconductor capable of reducing an element isolation region between memory cells in the word line direction and improving the degree of integration. A storage device is provided.

[0012]

[0013]

In order to solve the above problems, the present invention employs the following configurations.

That is, the present invention provides a semiconductor memory device in which a plurality of nonvolatile memory cells having a charge storage layer and a control gate stacked on a semiconductor substrate are connected in series to form a NAND cell unit. bit line contact connected to the diffusion layer of the selection transistor, a wiring serving as a bit line is formed by connecting directly to the diffusion layer, it is laid out alternately shifted on the bit line direction in adjacent ones, the selection transistor Gate of
If the intersection of the pole and the bit line is
Tsu in the door line direction by shifting alternately been laid, the same bit
The bit line contact and
It is characterized in that they are shifted in the same direction .

[0015]

Further, according to the present invention, in a semiconductor memory device in which a plurality of memory cells are connected in series on a semiconductor substrate to form a NAND cell unit, a bit line connected to a diffusion layer of a selection transistor of the NAND cell unit. The contact is formed by connecting a wiring to be a bit line directly to the diffusion layer, and is laid out so that adjacent ones are alternately shifted in the bit line direction.
The intersection of the gate electrode and the bit line is adjacent
Are laid out alternately with each other in the bit line direction.
The bit line contacts associated with the same bit line and
The intersecting portions are shifted in the same direction .

The preferred embodiments of the present invention are as follows. The memory cell may be a non-volatile memory cell or another memory cell such as DRA.
It may be M, especially a NAND type DRAM cell.

[0018]

According to the present invention, by arranging the bit line contact portions so as to be shifted in the bit line direction for each cell,
The distance between contacts becomes longer and the breakdown voltage between contacts improves. Therefore, the element isolation region between the memory cells in the word line direction can be reduced, and the degree of integration can be improved.

This means is particularly effective when used in a NAND cell. That is, by shifting the contact portion, the length of the NAND cell in the bit line direction increases,
The length in the word line direction of the element isolation region that realizes the same breakdown voltage is shortened. Therefore, by shifting the bit line contact portion, the area of the element isolation region increases in the bit line direction and decreases in the word line direction. For NAND cells,
Since a plurality of memory cells are connected in series, the length in the bit line direction is significantly longer than that in the word line direction. The area reduction is much larger. Therefore, NA
In the entire ND cell array, the area of the element isolation region can be greatly reduced. This NAND cell may be a NAND type EEPROM, or may be another cell such as NAN.
A cell such as a D-type DRAM may be used.

[0020]

[0021]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 shows the N according to the first embodiment of the present invention.
FIG. 3 is a plan view showing an array configuration of an AND cell type EEPROM. In the figure, 1 is a bit line, 2 is a bit line contact, 3
Is a source line, 4 is a memory cell, 5 is a drain side selection transistor, and 6 is a source side selection transistor.

In the memory cell 4, a floating gate (charge storage layer) FG made of p-type polysilicon is formed on a semiconductor substrate via a tunnel oxide film (for example, 10 nm), and a gate oxide film (for example, film thickness) is formed thereon. The control gate CG made of polysilicon is formed with a thickness of 20 nm).
The control gate CG becomes a word line. Eight memory cells 4 are connected in series, and select transistors 5 and 6 are connected before and after the memory cells 4 to form one NAND cell.

Then, a contact (bit line contact) 2 is made to the drain portion of the upper selection transistor 5,
Al wiring is formed in a direction orthogonal to the word line, and this is referred to as bit line (BL) 1. The source portion of the lower select transistor 6 is connected to the source line 3 parallel to the word line.

Here, in this embodiment, the bit line contacts 2 are not aligned in the word line direction but are alternately shifted in the bit line direction. By doing in this way, the distance between each contact is
It can be realized with a smaller element isolation region. For reference, FIG. 7 shows a plan view of an array of a conventional NAND type EEPROM. As shown in this figure, the bit line contacts 2 are aligned in the word line direction.

The cell reduction in the case of the configuration of this embodiment will be estimated. First, the element isolation width is L1, NAND
The length of the cell in the bit line direction is L2, and the width of the cell is L3. In the conventional NAND cell array, the area S1 of one NAND cell including the element isolation region is S1 = (L1 + L3) .times.L2 as shown in FIG. In the NAND cell array of this embodiment, as shown in FIG. 1, S2 = (L1 cos θ + L3) × (L2 + L1 sin θ). Therefore, L1, L2, L3, and θ are, for example, L1 =
1.8 μm, L2 = 16 μm, L3 = 0.7 μm, θ =
If the angle is 45 °, the area difference between the present embodiment and the conventional example is S1−S2 = 40.0−34.0 = 6.0, which is reduced by 6.0 μm ² .

In the above description, L1 in the conventional example is the length between the adjacent bit lines, and L1 in the example is the length connecting the contact centers of the adjacent bit lines. However, for more accurate estimation, the L1 in the conventional example is used. L1 'is the length between adjacent bit line contacts,
L1 ′ in the embodiment may be calculated as the shortest length between the edges of the adjacent bit line contacts. (Embodiment 2) FIG. 2 shows an E according to a second embodiment of the present invention.
FIG. 3 is a plan view showing an array configuration of EPROM. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the control gates CG and the selection gates SG are alternately bent so that the bit line contacts 2 are alternately shifted. With such a configuration, the distance from the bit line contact 2 to the selection gate SGD can be made equal in each NAND cell (the resistance from the contact to the selection transistor is equal), which is effective in uniformizing the cell characteristics. Is.

In the present embodiment, instead of using the common source line (diffusion layer) 3 as the source line, a source contact is provided to connect the sources adjacent in the word line direction, as will be described later in the embodiment. ing. Of course, also in this case, the common source line 3 may be provided as in the first embodiment.

The layouts of the first and second embodiments are also suitable for applying the self-aligned contact process. Also, in the first and second embodiments, NA
Although the ND cell is used, the present invention is not limited to this and can be applied to an EEPROM using a non-volatile memory cell. The embodiment of the present invention can be applied to the NAND type cell having the configuration disclosed in Japanese Patent Laid-Open No. 4-147940 described in the above-mentioned conventional technique. (Embodiment 3) FIG. 3 shows an NA according to a third embodiment of the present invention.
FIG. 4A is a plan view showing an array configuration of an ND cell type EEPROM, and FIGS. 4A and 4B are cross-sectional views taken along arrows AA ′ and BB ′. Further, FIG. 5 is an equivalent circuit of a NAND cell.

In this embodiment, four memory cells M1 ...
M4 is connected in series in such a manner that the source and drain diffusion layers are shared by adjacent ones to form a NAND cell. Such NAND cells are arranged in a matrix to form a NAND cell array.

The drain side at one end of the NAND cell is connected to the bit line BL via the select gate SGD, and the source at the other end is connected to the common source line (ground line) composed of polysilicon wiring or the like through the select gate SGS. ing. The control gates CG1 to CG4 of each memory cell are connected to the bit line BL.
The word lines WL are arranged in a direction intersecting with.

In this embodiment, four memory cells form one NAND cell, but in general, 2 n (n = 1, 2, ...) Memory cells form one NAND cell. can do.

A specific memory cell structure is shown in FIG.
This is as shown in (b). A p-type well 11 'is formed on the n-type silicon substrate 11, and memory cells are arrayed in the p-type well 11'. The peripheral circuit will be formed in a p-type well different from the memory cell. Four memory cells and two select gates are formed in a region surrounded by the element isolation insulating film 12 of the p-type well 11 '.

Each memory cell has five p-type wells 11 '.
1st gate insulating film 13 ₁ consisting of a thermal oxide film of ˜20 nm
Is the floating gate 14 by a first layer polysilicon 50~400nm formed through a (14 ₂ to 14 ₅₎ is formed, the second consisting of a thermal oxide film 15~40nm on this
100 to 400n formed through the gate insulating film 15
control gate 16 (16
_{1 to} 16 ₅ ) are formed. The n-type layer 19 serving as the source / drain diffusion layer of each memory cell is shared by adjacent ones, and four memory cells are connected in series.

At the end of the NAND cell on the source side, the gate electrode 14 formed of the first-layer polycrystalline silicon is formed on the p-type well 11 'with the gate insulating film 13 ₂ made of a thermal oxide film of 5 to 40 nm interposed therebetween. Select gate with ₁ (SG _D )
And a select gate (SG _S ) having a gate electrode 14 ₆ is formed. Here, the gate insulating film 13 ₂ may be the same as the first gate insulating film 13 ₁ . Wirings 16 ₁ and 16 made of the second polycrystalline silicon are used for the gate electrodes 14 ₁ and 14 _6.
6 are stacked. The gate electrode 14 ₁ and the wirings 16 ₁ and 14 ₆ and 16 ₆ are connected by through holes at predetermined intervals to reduce the resistance.

Here, the floating gate 14 _{2 of} each memory cell is
-14 ₅ and the control gate 16 _{2-16 5,} and the gate electrode 14 ₁ of the selection gate, 14 _6, lines 16 _1, 16 _6,
The channel length direction is patterned and aligned using the same etching mask. The n-type layer 19 serving as a source / drain diffusion layer is formed by ion implantation of arsenic or phosphorus using these electrodes as a mask.

The CVD insulating film 1 is formed on the substrate on which the elements are formed.
7, a common source line 20 is formed of third-layer polycrystalline silicon, and is connected to the source diffusion layer by a contact hole 21. Furthermore, the bit line 18 is covered with a CVD insulating film 17 'and covered with an Al film.

The operation of the NAND cell array thus constructed is exactly the same as the conventional one. However, in the structure of this embodiment, the reliability of the source side select gate can be improved as compared with the conventional case.

In the conventional case, as shown in FIG. 6, the element isolation region separating the NAND cells is divided by the common source line. In the actual case, the part where the element isolation region is cut off by the common source line is rounded like a broken line, and this rounded part is applied to the source side select gate, which deteriorates the breakdown voltage. This tendency becomes remarkable as the element is miniaturized and the distance from the source side select gate to the common source line is shortened.

On the other hand, in the case of this embodiment, since the element isolation region is not divided by the common source line 20, the above problem does not occur and the breakdown voltage of the source side select gate is improved as compared with the conventional one. To be done. Further, in this embodiment, since the element isolation regions are continuous without being divided, a resist pattern for forming the element isolation regions can be formed in a pattern close to lines and spaces.
Therefore, the phase shift method can be effectively used, and the pattern accuracy can be improved.

In this embodiment, the third polycrystalline silicon line is used as the common source line, but this is not the same as the second layer Al.
A wire or the like may be used, or the first layer Al wiring may be used by changing the material of the bit line. In the embodiment, the NAND
Although the cell is used, the present invention is not limited to this and can be applied to an EEPROM using a non-volatile memory cell.

[0042]

As described above in detail , according to the present invention, the bit line contacts in the memory cells are laid out by alternately arranging adjacent bit lines in the bit line direction so that the element isolation regions between the memory cells can be separated from each other. It is possible to realize a semiconductor memory device capable of reducing the size and improving the degree of integration.

[0043]

[Brief description of drawings]

FIG. 1 is a plan view showing an array configuration of an EEPROM according to a first embodiment.

FIG. 2 is a plan view showing an array configuration of an EEPROM according to a second embodiment.

FIG. 3 is a plan view showing an array configuration of an EEPROM according to a third embodiment.

FIG. 4 is a view of the NAND cell of FIG. 3 taken along arrows AA ′ and BB ′.
Sectional view of.

5 is an equivalent circuit diagram of the NAND cell of FIG.

FIG. 6 is a plan view showing an array configuration of a conventional NAND cell.

FIG. 7 is a plan view showing an array configuration of a conventional NAND cell.

[Explanation of symbols]

1 ... Bit line (BL) 2 ... Bit line contact 3 ... Source line 4 ... Memory cell 5 ... Drain side selection transistor 6 ... Source side selection transistor CG (CG1 to CG8) ... Control gate FG ... Floating gate (charge storage layer) SG (SGD, SGS) ... Selection gate

Continuation of the front page (56) Reference JP-A-5-198822 (JP, A) JP-A-5-275659 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21 / 8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] 1. A semiconductor memory device in which a plurality of nonvolatile memory cells, each having a charge storage layer and a control gate stacked on a semiconductor substrate, are connected in series to form a NAND cell unit, wherein diffusion of a selection transistor of the NAND cell unit is performed. The bit line contact connected to the layer is formed by connecting a wiring to be a bit line directly to the diffusion layer, and is laid out by alternately arranging adjacent ones in the bit line direction alternately with the gate electrode of the selection transistor. With the bit line
The intersections do not alternate between adjacent ones in the bit line direction.
And the bit line contact and the bit line contact relating to the same bit line.
A semiconductor memory device, wherein the intersections are shifted in the same direction . 2. In a semiconductor memory device in which a plurality of memory cells are connected in series on a semiconductor substrate to form a NAND cell unit, a bit line contact connected to a diffusion layer of a selection transistor of the NAND cell unit is a bit line contact. Wirings to be lines are formed so as to be directly connected to the diffusion layer, and adjacent ones are laid out by alternately shifting in the bit line direction, and the gate electrodes of the selection transistors and the bit lines are arranged .
The intersections do not alternate between adjacent ones in the bit line direction.
And the bit line contact and the bit line contact relating to the same bit line.
A semiconductor memory device, wherein the intersections are shifted in the same direction .