JP3339564B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a highly integrated semiconductor device comprising fine elements capable of supporting a wide range of power supply voltages and power supply types.

[0002]

2. Description of the Related Art In recent years, portable electronic information devices such as laptop personal computers and electronic organizers, solid-state recorders for recording audio without using a magnetic medium, and solid-state cameras (electronic still cameras) for recording images have been developed. Representative portable electronic media devices are beginning to appear on the market. For these portable electronic devices to become widespread, the key is to realize an ultra-high-integrated circuit (hereinafter abbreviated as ULSI) capable of battery operation or information retention operation (battery backup) using a battery. On the other hand, as a large-capacity auxiliary storage device for realizing a higher-performance computer, there is a growing need for a semiconductor disk that can be accessed at a higher speed than a magnetic disk. The semiconductor disk requires an ultra-large-capacity memory LSI capable of holding information by a battery.

The following are required for ULSI used in these applications. (1) Wide power supply voltage range (1 to 5.5)
Operation in V). Thus, various power supplies, for example, 5 which is a standard power supply voltage of the current TTL compatible digital LSI
V, or 3.3 V, which is one of the standard power supply voltage candidates for future TTL compatible digital LSIs, and 3 to 3.6 V, which are typical output voltages of primary batteries using lithium or the like.
One chip can cope with a typical output voltage of 1.2 V, which is a typical output voltage of a secondary battery using cadmium and nickel.

(2) Response to time-dependent changes (short-term or long-term) of the power supply voltage. Thus, there is no fear that a malfunction may occur even if the voltage of the battery changes over time or a voltage change occurs due to power supply switching at the time of transition between the standard operation and the battery backup operation.

(3) Reduction of power consumption during operation or battery backup operation. As a result, the battery can be operated for a long time even with a small battery.

(4) Reduction of transient current. Thereby, the transient fluctuation of the battery voltage can be reduced, and malfunction can be prevented.

An example of a microprocessor product that operates over a wide power supply voltage range is described in page 148 of the NEC Handbook of 4-Bit Microprocessors. The product model name is μPD7507SC. The operating power supply voltage range of this microprocessor is 2.2 to 6.0V. Further, information of the data memory can be held at a minimum of 2V. Similarly, in a static memory,
Generally, the recommended operating power supply voltage is 5 V, and 2 V when information is retained (retention).

As an example of a dynamic memory for battery backup, an example in which current consumption at the time of information retention (refresh) is reduced is described in IEE Journal of Solid State Circuits, Vol. 1
No. 12, pp. 18 (1988) (IEEE Jounal
of Solid-State Circuits, Vol.23, No.1, pp.12
-18, February 1988). In this case, the standard operation power supply voltage and the power supply voltage for holding information are both 5V.

[0009]

The above-mentioned microprocessors and static memories have a wide operating power supply voltage range of 2 to 5 V.
Because it is designed around 5V, for operation outside the allowable power supply voltage fluctuation range (usually ± 10%),
The operating speed (corresponding to the maximum clock frequency in the case of a microprocessor and the access time in the case of a static memory) is not guaranteed, and the operating speed is usually significantly reduced particularly at a low power supply voltage. In addition, power supply voltage dependence of operating speed varies depending on the product.
The operation speed must be matched to the slowest operation speed of the LSIs constituting the system. If the operation is performed at a voltage other than 5 V, the required performance cannot be obtained, and the system design at a low power supply voltage becomes extremely difficult. In addition, these LSIs
Has a minimum operating power supply voltage of 2.2 V, and thus cannot cope with all of the various types of power supplies described above, and is constrained by the system configuration.

When the above-mentioned dynamic memory is incorporated into a system, its minimum power supply voltage is 4.5 V, which makes it more difficult to cope with various types of power supplies. In particular, since there is no difference between the standard operating power supply voltage and the power supply voltage at the time of retaining information, the configuration of the power supply switching circuit becomes very complicated, and it becomes difficult to retain information.

The miniaturization of semiconductor elements has been rapidly progressing, and a certain degree of system has been integrated on one chip by using a processing technique of 0.5 μm or less. It is becoming possible to configure a so-called system LSI. In such a system LSI, each of the LS
It is required that the operating power supply voltage range and operating speed of the I block match. However, as described above, the combination of the conventional LSIs alone would make such a system LSI difficult.
Could not be configured.

An object of the present invention is to make use of element performance suitable for various types of power supply voltages, low power consumption, and fine processing.

[0013]

According to a typical configuration of the present invention, a first circuit block which operates at a first voltage defined by a difference between a first potential and a second potential and includes a plurality of circuits; First
A first bias voltage determined on the basis of a potential; and a voltage generating circuit for generating a second bias voltage determined on the basis of the second potential. A first MISFET of the first conductivity type, a second MISFET of the first conductivity type, and a third MIS of the second conductivity type, wherein the source / drain paths are connected in series
And a fourth MISFET of the second conductivity type. The gate of the second MISFET is supplied with the first bias voltage and the third MISFET.
The semiconductor device is configured such that the second bias voltage is supplied to the gate of the semiconductor device.

[0014]

The first bias voltage based on the first potential is applied to the second MISFET, and the second bias voltage is applied to the third MISFET.
Since the second bias voltage based on the potential is applied,
Even when the first voltage fluctuates, the fluctuation of the logic level is suppressed, and the operation speed of the circuit is not impaired. Further, even when the first voltage is higher than the breakdown voltage of the first to fourth MISFETs, the first to fourth MISFETs are not destroyed.

[0015]

FIG. 1 is an embodiment for explaining the basic concept of an LSI chip according to the present invention. In FIG. 1, reference numeral 1 denotes an LSI chip which generally indicates an LSI chip having an information storage function or an information processing function, such as a random access memory (RAM) such as a dynamic type or a static type, a serial access memory (SAM), or a read only memory. (ROM) such as a memory LSI, a logic LSI such as a microprocessor (MPU), a memory management unit (MMU), a floating-point arithmetic unit (FPU), and a system LSI integrating a plurality of them. Any type of LSI chip may be used. The constituent elements may be a bipolar transistor, a MIS transistor, a combination of these elements, or a material other than silicon, for example, an element of gallium arsenide. Reference numeral 2 denotes an example of a power supply circuit that detects a drop in the external power supply voltage and shifts to a battery backup state. With such a power supply circuit, it is possible to prevent loss of necessary information stored in the LSI chip even if VEXT drops due to a momentary interruption of commercial power. Among them, 3 is a power supply voltage drop detection circuit, SW is a switch for preventing a current from flowing from a battery to an external power supply terminal when information is retained, 4 is a switch control signal, B is a battery, and VBT is its voltage. And
In the information holding mode, the entire chip operates using this battery as a power source. D is a diode for preventing current from flowing into the battery during normal operation. With this power supply circuit, VEXT is applied to the power supply terminal (PAD1) of the chip during normal operation and VBT during information retention.

In this example, the difference between the normal operation and the information holding operation is detected by the detecting means on the LSI chip.
Here, 5a and 5b are main circuit blocks, 5 is a set of them, and 6 is a power supply voltage conversion circuit for converting the power supply voltage VCC input from outside the chip into the power supply voltages VCL1 and VCLn of each circuit block. In FIG. 6, 6a and 6c denote conversion circuits for normal operation, and 6b and 6d denote conversion circuits for information retention. In general, the operating voltage and operating current of the circuit can be smaller during information retention than during normal operation. Therefore, there is no problem even if the current consumption of the voltage conversion circuit that supplies the power supply voltage is reduced to lower the driving capability. . As a result, coupled with the reduction in current consumption of the main circuit block, L
The current consumption of the entire SI chip can be significantly reduced. In this example, a method of switching between two voltage conversion circuits has been described, but the number of conversion circuits may be three or more. Further, the output voltage and the current consumption may be changed by using one voltage conversion circuit.

For SW6a and SW6c, VCC is VCL1 or VCLn.
Is a switch for directly applying the power supply voltage VCC to the circuit block when the voltage drops to a value substantially equal to. By using the switch, the voltage conversion circuit can be turned off, and the current consumption can be further reduced. Note that, in the above example, an example in which a power supply voltage conversion circuit is configured by a switch and a plurality of voltage conversion circuits has been described; however, a single voltage conversion circuit may be used as long as a similar effect is obtained. In FIG. 1, reference numeral 9 denotes a circuit for generating a reference voltage VL. The internal power supply voltages VCL1 and VCLn are generated based on this voltage. Reference numeral 8 denotes a circuit for generating a signal PD indicating the information holding operation state. There are several methods for generating the PD. Here, a method is used in which the power supply voltage VCC and the reference voltage VCX are compared, and the PD is output when the former is smaller than the latter.

Reference numeral 10 denotes a circuit for generating a limiter enable signal LM. When the power supply voltage is higher than the internal power supply voltage and the voltage conversion circuit (voltage limiter) is operated, the high voltage (“1”) is used. ) Is output. In the latter case, the power supply voltage is applied directly to the circuit block, and at the same time, the voltage conversion circuit is not operated and the current consumption is reduced. In the example shown in FIG.
CC is compared with the reference voltage VLX, and LM is output when the former is larger than the latter. The output voltage and current consumption of the power supply voltage conversion circuit can be switched by the two signals PD and LM. 7 is an input / output buffer,
Reference numeral 11 denotes an input / output bus for exchanging control signals and data with the outside of the chip. Numeral 12 denotes an internal bus inside the chip for exchanging control signals and data between circuit blocks. The input / output buffer also serves as a level conversion circuit, and can exchange control signals and data even when the logic signal amplitude inside the chip does not match the external logic signal amplitude. In addition, in the information holding operation state, since there is no need to exchange control signals and data between the outside and the inside of the chip, the input / output buffer is turned off by the information holding state signal PD.

FIG. 2 is a diagram showing an example of the relationship between the power supply voltage VCC and the internal power supply voltage VCL. In the figure, the horizontal axis is the power supply voltage V
CC and the vertical axis correspond to the internal power supply voltage VCL. Here, the standard power supply voltage is 3 to 3.6 V, and the power supply voltage when information is held is 1
The reference voltage VCX for switching between standard operation and information retention is set to 2.5 V. The minimum value of the standard power supply voltage VCC (min) and the maximum value of the power supply voltage VBT (ma
x) and the reference voltage VCX, if the relationship of VBT (max) <VCX <VCC (min) is established, the values may not be the values shown here. Although the internal power supply voltage VCL at the time of the standard operation is set to 1.5 V, an appropriate voltage value according to the operation performance of the circuit may be set within a range not exceeding the power supply voltage VCC. In this example, the value of VLX is set to 1.5 V in order to directly apply the power supply voltage VCC to the internal circuit at a power supply voltage of 1.5 V or less.

In this LSI chip, the power supply voltage VCC
FIG. 3 shows an example of the time change of each of the internal power supply voltage VCL and the two control signals LM and PD in the case where. Here, a case is considered in which the power supply voltage VCC decreases to 3.5 V to 1 V from time t0 to t3, and increases from 1 to 3.5 V from time t4 to t7.
T1 to t when the power supply voltage VCC becomes smaller than VCX = 2.5V
During period 6, the signal PD becomes high voltage ("1"), and the chip enters the information holding state. Also, when the power supply voltage VCC is VLX =
During the period from t2 to t5 when the voltage is lower than 1.5 V, the signal LM is at a low voltage ("0"), and the power supply voltage VCC is directly applied to the chip. It should be noted that the voltage values shown here are just examples, and other voltage combinations can be similarly applied.

FIGS. 4 and 5 show an example of a method and a circuit configuration for generating the limiter enable signal LM. The signal LM may be changed from a high voltage ("1") to a low voltage ("0") when the power supply voltage VCC is reduced and becomes equal to the internal power supply voltage VCL for the first time. In this example, a voltage β × proportional to the power supply voltage VCC
The comparison circuit compares VCC (0 ≦ β ≦ 1) with the reference voltage VL, and outputs a high voltage (“1”) when the former is large and outputs a low voltage (“0”) when the former is small. . By inputting a voltage between a high voltage and a low voltage using a voltage proportional to the power supply voltage VCC in this manner, the voltage amplification factor of the comparison circuit can be increased, which is convenient in circuit operation. . For example, when β = 0.5 and VL = 0.75V,
When VLX = 1.5 V and the power supply voltage VCC is 1.5 V or more, the limiter enable signal LM becomes high voltage ("1").
, And the voltage conversion circuit operates. Here, the power supply voltage V
The voltage proportional to CC can be generated by resistance division or the like.

FIGS. 6 and 7 show the information holding state signal P
An example of a method for generating D and a circuit configuration will be described. Basically, it can be constituted by a circuit similar to the LM generation circuit described above. In this case, a voltage α × VCC proportional to the power supply voltage VCC
(0 ≦ α ≦ 1) is input to the inverting input terminal of the comparison circuit.
For example, when α = 0.5 and VL = 0.75V, VCX = 2.
When the power supply voltage VCC becomes 2.5 V or less, the information holding state signal PD becomes a high voltage ("1") and enters the information holding state. Here, the voltage proportional to the power supply voltage VCC is generated by resistance division of the resistors R1 and R2. The resistors R1 and R2 may be formed using any of an impurity diffusion layer and polysilicon formed in a semiconductor substrate, and a channel resistance of a MIS-FET.

FIG. 8 shows an embodiment in which the present invention is applied to an LSI including a static memory as a part thereof.
In the figure, 5c is a memory cell array of a static memory,
Reference numeral 5d denotes a circuit block such as a logic circuit that does not need to hold information, and its power supply voltage is VCL2 and VCL1. The memory cells are four N-channel MOS-FETs T6 to T9
And two resistance elements R7 and R8. Assuming that the resistance value is R, the current value flowing per memory cell is VCL2 / R. Therefore, it is desirable to lower the voltage value as much as possible within a range where noise margin (noise margin) can be secured when information is held. As shown in FIG. 9, in this example, VCL2 in the standard operation is set to 1.5 V, and VCL2 in the information holding example is set to 1 V. The logic circuit block 5d includes an inverter, a logic gate, and the like. In the figure,
T11 and T13 with arrows indicate P-channel MOS-FETs, and other T10 and T12 indicate N-channel MOS-FETs.
When information is held, these logic circuits do not need to be operated, so that there is no need to supply a power supply voltage. Therefore,
Here, VCL1 at the time of standard operation is 1.5 V, V
CL1 is set to 0V. Internal power supply voltages VCL2 and VCL1
Is supplied by the power supply voltage conversion circuit 6e or the P-channel MOS-FET T1 operating as a switch. The power supply voltage conversion circuit is connected to the differential amplifier A1, the resistor R3 provided for controlling the operating current of the differential amplifier, two N-channel MOS-FETs T3 and T4, and the inverting input terminal of the differential amplifier. , And three resistors R4 to R6, a P-channel MOS-FET T5, and a P-channel MOS-FET T2 operating as a switch. When the power supply voltage is high and the internal power supply voltage drops from VCC, the limiter enable signal LM becomes high voltage ("1"). At this time, T1 is cut off, and at the same time, T3 is turned on, a bias current is supplied to the differential amplifier circuit A1, and a voltage proportional to the non-inverting input voltage VL is output. Conversely, when the signal LM is at a low voltage ("0"), T3 is cut off, and no bias current is supplied to the differential amplifier circuit. Therefore, the power supply voltage VCC is directly output as the internal power supply voltage. During the information holding operation, the information holding signal PD becomes high voltage ("1"). At this time, the transistor T2 is cut off, and the power supply to the circuit block 5d is stopped. On the other hand, T4 is cut off, and the value of the bias current of the differential amplifier circuit is determined by the resistor R3. In the information holding state, the current consumed by the memory cell array is very small, and can be regarded as a substantially constant DC current in time. Therefore,
The load driving capability of the differential amplifier circuit may be much smaller than that in the standard operation, and there is no problem in operation even if the bias current is significantly reduced. At the same time, T5 is made conductive,
By increasing the amount of feedback of the differential amplifier circuit, the internal power supply voltage during the information holding operation is reduced. As a result, the current consumption of the entire chip when information is held can be significantly reduced. In this example, VL = 0.75V, R4 =
R6 = 3R5. At this time, the value of VCL2 is 1.5 V during standard operation and 1.0 V when information is held.

FIG. 9 shows the power supply voltage VCC and the internal power supply voltage VCL2.
And an example of the relationship between VCL1 and VCL1. In the figure, the horizontal axis represents the power supply voltage VCC, and the vertical axis represents the internal power supply voltage VCL. Here, as in the example of FIG. 2, the standard power supply voltage is 3 to 3.6 V, the power supply voltage for information retention is 1 to 2 V, and the reference voltage VCX for switching between the standard operation and the information retention is 2.5 V. And Internal power supply voltages VCL2 and VCL1 during standard operation
Is 1.5 V, and the internal power supply voltage VCL2 when information is held is 1 V. However, an appropriate voltage value according to the operation performance of the circuit may be set within a range not exceeding the power supply voltage VCC.

In this LSI chip, the power supply voltage VCC
FIG. 10 shows an example of the time change of each of the internal power supply voltages VCL2 and VCL1, and the two control signals LM and PD, when the time varies. Here, the power supply voltage VCC drops to 3.3 to 2 V from time t0 to t2, and the time t3
It is assumed that the power supply voltage VCC rises to 2 to 3.3 V from to t5. During the period from t1 to t4 when the power supply voltage VCC becomes smaller than VCX = 2.5 V, the signal PD becomes high voltage ("1"), and the chip enters the information holding state. In this time range, the power supply voltage VCC does not become lower than 1.5 V, so that the signal LM remains at the high voltage ("1").

According to the above-described embodiment, a static memory or a static memory capable of operating at a high speed in a standard operation and retaining information with a minimum necessary power when retaining information is used. L included in
SI can be realized. In the above embodiment, an example using a static memory cell with a high resistance load has been described.
CM consisting of S inverter and two selection transistors
OS type memory cell, two NAND gates or N
The present invention can be similarly applied to a case where a storage circuit is formed by a latch circuit using an OR gate or the like.

FIG. 11 shows an embodiment in which the present invention is applied to a dynamic memory. In the figure, 5e is 1.5V
A dynamic memory that operates with the following power supply voltage,
One memory cell is composed of an N-channel MOS-FET T18 and a storage capacitor CS1. 13 is a memory cell array, 14 is a row address buffer, 15 is a column address buffer, 16 is a row address strobe (RAS) input buffer, 17 is a column address strobe (CAS) input buffer, 18 is A write enable (WE) input buffer, 19 is a data input buffer, 20 is a data output buffer, 21 is a clock generation circuit for generating a control clock based on a row address strobe (RAS) signal, and 22 is a column address. A clock generation circuit for generating a control clock based on a strobe (CAS) signal, 23 a write clock generation circuit, 24 a refresh (RFSH) signal generation circuit, 25 a refresh address generation circuit, 26 a refresh address and an external input Switch the address It is a mux. In the dynamic memory, information is stored by storing charges in the storage capacitor CS1, so that a so-called refresh operation of periodically reading out signal charges and performing rewriting, even when information is held, is required. Some of the peripheral circuits need to be operated. In addition, in order to ensure a sufficient noise margin, it is necessary to ensure the same signal charge amount as in the standard operation even when information is held. So, in this example,
As shown in FIG. 12, the internal power supply voltage at the time of information holding and at the time of standard operation is kept at 1.5 V (constant) without changing. When information is held, there is no need to perform input / output with the outside of the chip.
Cut off. Further, the multiplexer is controlled by a signal PD, and when information is held, the address is switched to an address output from a refresh address generation circuit. At the time of the refresh operation, the signal RFSH becomes a high voltage ("1"). This signal is input to the refresh address generation circuit, and sequentially increases or decreases the refresh address. At the same time, the RFSH activates the clock generation circuit 21 to generate a clock required for refresh. The internal power supply voltage VCL is supplied by a power supply voltage conversion circuit 6f and a P-channel MOS-FET T14 operating as a switch. The power supply voltage conversion circuit includes a differential amplifier circuit A2, a resistor R9 provided for controlling the operating current of the differential amplifier circuit, and three N-channel MOS-FETs T15 and T1.
6, T17, and two resistors R10 and R11 provided to control the amount of feedback to the inverting input terminal of the differential amplifier circuit. When the power supply voltage is high and the internal power supply voltage drops from VCC, the limiter enable signal LM becomes high voltage ("1"). At this time, T14 is cut off, and at the same time, T15 conducts, a bias current is supplied to the differential amplifier circuit A2, and a voltage proportional to the non-inverting input voltage VL is output. Conversely, when the signal LM is at a low voltage ("0"), T15 is cut off, and no bias current is supplied to the differential amplifier circuit. Therefore, the power supply voltage VCC is directly output as the internal power supply voltage. During the information holding operation, the information holding signal PD becomes high voltage ("1"). At this time, T16 is cut off, and the value of the bias current of the differential amplifier circuit is determined by the resistor R9. The current consumption is small in the information holding state and during the period when the peripheral circuit is not operating. Therefore, the load driving capability of the differential amplifier circuit may be much smaller than that in the standard operation, and there is no operational problem even if the bias current is significantly reduced. At the time of the refresh operation, the signal RFSH is fed back to the voltage conversion circuit 6 to turn on T17, and the bias current of the differential amplifier circuit is set to a value similar to that at the time of the standard operation. By doing so, a power supply current necessary for charging / discharging the data lines and operating the peripheral circuits can be supplied during the refresh operation. Therefore, even when information is held, the current consumption of the entire chip can be significantly reduced without lowering the noise margin. In this example, VL = 0.
Although VCL = 1.5 V is obtained by setting 75 V and R10 = R11, other combinations of voltage values and resistance values may be used.

In this LSI chip, the power supply voltage Vcc
FIG. 12 shows an example of a time change of each of the internal power supply voltage VCL, the two control signals LM and PD, the refresh signal RFSH, and the bias current value of the differential amplifier circuit when the time varies. Here, the power supply voltage VCC drops to 3.3 to 2 V from time t0 to t2, and the time t3 to t2
It is assumed that the power supply voltage VCC rises to 2 to 3.3 V over 5. During the period from t1 to t4 when the power supply voltage VCC becomes smaller than VCX = 2.5 V, the signal PD becomes high voltage ("1"), and the chip enters the information holding state. In this time range, the power supply voltage VCC does not become lower than 1.5 V, so that the signal LM remains at the high voltage ("1"). During the information holding period, during the refresh operation, the same bias current IB1 as in the standard operation flows, and otherwise the value IB2 is sufficiently small.

In the above-described example, the row address and the column address are temporally switched from the same address bus. Although the so-called address multiplex system is used, the present invention can be similarly applied by using a general system in which all addresses are fetched simultaneously. Also,
Japanese Patent Application Nos. 63-148104 and 63-222317
By using a dynamic memory that drives the plate to reduce the voltage amplitude of the data line as described in the above section, a memory with lower power consumption can be realized.

FIGS. 13A and 13B show an example of the timing of the refresh signal RFSH when information is held. Here, an example is shown in which all memory arrays are refreshed in 4096 cycles. By reducing the power supply voltage to, for example, 1.5 V or less, the current consumption of the entire memory can be significantly reduced. Therefore, even for a large-capacity memory of about 64 Mb, the refresh cycle needs to be increased from 4096. And make the system easier to configure. After the transition to the information holding state, a concentrated refresh is performed in the first 4096 cycles, that is, the signal RFSH is generated in a relatively short cycle TC1. This is because refresh control during standard operation is R
This is because it is unrelated to the internal refresh by FSH. By performing such initialization, the risk that the specification of the refresh cycle is not satisfied before and after the state transition can be avoided. In FIG. 13A, the signal RFSH is generated at a constant cycle TC2 after the concentrated refresh. On the other hand, in FIG. 6B, the concentrated refresh is repeated at the cycle TC3, and the cycle of the signal RFSH during the concentrated refresh is set to the same value TC1 as the first concentrated refresh. This value may be another value, but it is more convenient to set the same value in view of the configuration of the signal generating circuit.

FIG. 14 shows an example of the chip temperature dependency of the refresh cycle TC2 in the example of FIG. The relationship between chip temperature and information retention time is, for example,
EE Transactions on Electron Devices, Vol. 35, No. 8, 1257-
1263 (1987) (IEEE Transactions on
Electron Devices, Vol. 35, No. 8, pp. 1257-1
263, August 1987).
According to this, the change in the information retention time when the chip temperature changes from 0 to 100 ° C. is about three digits. Therefore, by changing the refresh cycle TC2 as shown in FIG. 14, it is possible to match the actual information holding characteristics. In the information holding state, since the power consumption of the chip is extremely small, there is almost no difference between the ambient temperature and the chip temperature. Therefore, by using at low ambient temperature,
The refresh cycle can be extended, and the power can be further reduced. Accordingly, a dynamic memory suitable for being mounted on a portable electronic device or the like using a battery as a power supply can be provided. An oscillation circuit having temperature dependence as shown in FIG. 14 is described in Japanese Patent Application Laid-Open No. Sho 60-13688.

FIG. 15 shows an example when a refresh failure occurs in the example of FIG. 13B. In the figure, the horizontal axis is the refresh cycle, and the vertical axis is the cumulative failure frequency. Only one bit is defective with respect to the refresh cycle TC3. If only a small part of the memory is bad,
There is a so-called defect remedy technique in which a defective memory cell is repaired by replacing it with a spare memory cell provided on a chip in advance. This technology, for example,
EEE Journal of Solid State Circuits, Vol. 16, No. 5, 479-48
7 pages (1981) (IEEE Journal of Solid-State)
Circuits, Vol.16, No.5, pp.479-487,19
81). This technique can be similarly applied to a refresh failure as shown in FIG. However, the conventional defect remedy technique requires a spare memory cell, and thus has a disadvantage of increasing the chip area. FIG. 16, FIG. 17, and FIG. 18 show examples of the refresh failure remedy technique using no spare memory cell. This means that only the memory cells that become defective in the refresh cycle TC3 in FIG. 15 are refreshed in a shorter cycle, for example, TC4. Hereinafter, description will be made with reference to FIGS. FIG. 16 shows an example of the timing of the refresh signal RFSH at the time of holding information when this defect remedy technique is used. Here, it is assumed that the address 1 has a refresh failure. As shown in the figure, during the period from one concentrated refresh to the next concentrated refresh, addresses 1
Is refreshing. In this case, the current consumption can be significantly reduced as compared with the case where all the addresses are refreshed in the short cycle TC4. It is necessary that 4096 × TC1 ≦ TC4 ≦ TC3 be satisfied between each refresh cycle. FIG. 17 shows an example of a circuit configuration for generating a refresh address and a refresh signal RFSH, and FIG. 18 shows the operation timing. In FIG. 17, OSC
Are oscillators for generating clock φ0, DV1, DV4, DV3
Is a clock φ1 having a period that is an integral multiple of the clock φ0,
frequency dividers for generating φ4 and φ3, 30 a 13-bit synchronous counter, 31 a refresh address generator, 32 a refresh signal (RFSH) generator,
I1 indicates an inverter, G1 indicates an AND gate, and G2 indicates an OR gate. The counter operates according to the clock φ1, and a high voltage (“1”) is applied to the Reset terminal.
The counting is started from a state where the counter outputs are all reset to a low voltage ("0"). When the output reaches 4097, the output Q12 becomes a high voltage ("1") and the counting stops. In the figure, reference numeral e denotes a counter enable signal. During the operation of the counter, since e is at a high voltage ("1"), the outputs Q0 to Q11 of the counter are output to the outputs ar0 to ar11 of the refresh address generation circuit. After the counter stops, e
Becomes a low voltage ("0"), and defective addresses aS0 to aS11 are output to ar0 to ar11. Similarly, during the operation of the counter, the clock φ1 is activated, and after the counter is stopped, the clock φ1 is activated.
Are output from the refresh signal generation circuit. Thus, during the operation of the counter, the period TC1 is 409.
Intensive refresh is performed six times, and after the counter stops, the period T
Only defective addresses can be refreshed by C4. Here, an example in which only one defective address is rescued has been described, but the present invention can be similarly applied to a case where a plurality of defective addresses are rescued.

According to the above-described embodiment, a dynamic memory or a dynamic memory capable of operating at a high speed in a standard operation and retaining information with a minimum necessary power in retaining information is used. L included in
SI can be realized. Further, even with respect to the power supply voltage fluctuation which has been a problem in the conventional dynamic memory, the external power supply voltage is reduced by operating the internal circuit at a low voltage such as 1.5 V as shown in FIGS. Even if it changes greatly, it can be operated stably.

In the embodiments described so far, the difference between the standard operation state and the information holding operation state is detected by the detecting means provided on the LSI chip. However, the operation state may be controlled from outside the chip. Absent. FIG. 19 shows another embodiment of the present invention in which the transition to the information holding state is externally controlled. Among them, 4b is an information holding state signal inputted from outside the chip, 1B is an LSI chip having an information storage function or an information processing function like the LSI chip of FIG. 1, and PAD3 is for receiving the information holding state signal. Each shows a bonding pad. The difference from the LSI chip of FIG. 1 is that there is no need to provide a detecting means and a means for generating an information holding state signal on the chip. This chip may be designed separately from the LSI chip shown in FIG. 1, or one chip may be designed and divided by switching of bonding or master slice of aluminum wiring.

FIG. 20 shows a case where the LSI chip shown in FIG. 19 is operated using a battery B as a power supply. The voltage value of the battery is distributed over a wide range such as 1 to 3.6 V depending on the type. Therefore, it is more convenient that the system can be controlled from the outside, as compared with a method of detecting the transition to the information holding state by a voltage change. FIG. 21 shows the dependency of the internal power supply voltage VCL on the power supply voltage VCC. In this example, the standard power supply voltage range is set to 1 to 3.6 V, and the standard power supply voltage range is set to 1.5 to 3.0 V.
At 6V, VCL = 1.5V, and at 1-1.5V, VCL = VCC. By doing so, 1-3.
A change in the internal power supply voltage can be suppressed over a wide power supply voltage range such as 6 V, and an LSI in which the operation performance such as the operation speed, the current consumption, and the operation margin hardly depends on the power supply voltage can be realized. In addition, since it is possible to shift to the information holding state as needed without changing the power supply voltage, unnecessary power consumption is suppressed according to the state of the system, and the operation time of the electronic device operated by the battery is extended. can do.

FIG. 22 shows an example of the configuration of an LSI in which the battery backup circuit shown in FIGS. 1 and 19 is incorporated into a chip, and the power supply is switched on the chip. In this figure, 1C is an LSI chip having an information storage function or an information processing function, like the LSI chip of FIG. 1, 40 is a power supply switching circuit, 41 is a power supply drop detection circuit, and SL and SB.
Is the switching signal generated by the power drop detection circuit, SW40
Reference numerals a and SW40b denote switches for switching the power supply in accordance with the switching signals SL and SB, and PAD4 denotes a bonding pad for applying a battery voltage. As described above, by performing power supply switching on a chip, it is not necessary to mount a battery backup circuit on a system (board), the number of components can be reduced, and manufacturing cost and mounting density can be improved. Further, since a power supply switching circuit according to the characteristics of the LSI can be mounted, the user does not need to worry about the transient fluctuation of the power supply voltage which is a problem at the time of power supply switching, so that an easy-to-use chip can be provided. FIG.
Shows a specific configuration example of the power supply switching circuit 40. In the figure, 42 and 43 are differential amplifier circuits, and 44 and 45.
, T19 and T20 are P-channel MOS-FETs corresponding to switches for switching the power supply, and 46 is the output of the power supply switching circuit. Hereinafter, the operation of this circuit will be described.
Voltages γVCC and γVBT proportional to VCC and VBT are applied to the non-inverting input and the inverting input of the differential amplifier circuit 42, respectively.
Similarly, voltages γVBT and γVCC proportional to VBT and VCC are applied to the non-inverting input and the inverting input of the differential amplifier circuit 43, respectively. Here, γ is a proportional constant that satisfies 0 ≦ γ ≦ 1, but it is desirable that γ be a value that can provide a sufficient voltage gain and output amplitude of the differential amplifier circuit. A proportional voltage can be obtained by resistance division. The outputs 44 and 45 of the differential amplifier circuits 42 and 43 are applied to the gates of T19 and T20. First, consider the case where VCC> VBT. At this time, the output 44
Is a high voltage (Vcc) and the output 45 is a low voltage (~ γV
CC-VT) is output, T19 is turned off, and T20 is turned on. Therefore, VCC is output as VINT. Similarly, when VCC <VBT, the output 44 has a low voltage (ＶγV
BT-VT), and a high voltage (VBT) is output to the output 45, and T19 is conductive and T20 is non-conductive. As a result, VBT is output as VINT. This circuit is VCC
The same operation is performed even when one of VBT and VBT is 0V. Therefore, even when only one of the power supplies is supplied, the supplied voltage is output as it is as the power supply voltage of the internal circuit.
FIG. 24 shows an example of the VCC dependency of VINT for the case where VBT = 1.5V. VINT when VCC> 1.5V
= VCC, VCC <1.5V, VINT = 1.5V is obtained. As shown in the figure, VINT changes continuously, and no kink that adversely affects the operation of the LSI is generated. As shown in the above embodiment,
Since the power supply switching circuit can be constituted by a relatively simple circuit, even if it is mounted on one LSI, the increase in the chip area is small. Here, an example in which a MOS-FET is used is shown, but the present invention can be similarly realized by using another type, for example, a bipolar transistor.

In the above embodiment, the basic concept of the LSI chip in which the main LSI circuit block operates at 1.5 V or less has been described. Hereinafter, a dynamic memory will be mainly described, and a more detailed embodiment will be described. In general, it has been considered that a dynamic memory is more difficult to operate at a low voltage than other logic LSIs and static memories. The first reason is that the signal charge amount, which is the product of the storage voltage and the storage capacitance, is reduced by lowering the voltage, and the signal-to-noise ratio is reduced. Therefore, there is a noise margin for noise charges generated by irradiating alpha rays emitted from a small amount of radioactive material contained in packages and metal wiring, and noise charges caused by thermal and non-thermal leak current flowing into memory cells. (Margin) has been considered difficult to secure. These problems can be solved by one of the following two methods.

(1) A circuit that can obtain a memory cell storage signal voltage (for example, low voltage = 0 V and high voltage = 3 V) comparable to that of a conventional memory cell even at a low power supply voltage (for example, 1.5 V). In this case, the storage capacity of the memory cell may be approximately the same as the conventional value (for example, 30 to 40 fF (femto farad)).

(2) Instead of keeping the conventional circuit system, the storage capacity of the memory cell is increased almost in inverse proportion to the power supply voltage. For example, when the power supply voltage is 1.5 V, the storage capacity of the memory cell is set to 60 to 80 fF. Of the above methods, regarding (1), in addition to the word line and the data line,
Japanese Patent Application Nos. 63-148104 and 63-2223 disclose a method of accumulating a signal amplitude larger than the amplitude of a data line in a memory cell by driving a plate of the memory cell.
17. As for (2), a technology for dramatically increasing the storage capacity as compared with the conventional technology is disclosed in Japanese Patent Application No. Sho 60-26.
7113 and Symposium on VSI Technology, Digest of Technical Papers, pp. 29-30 (1988) (1988 Symposi
um on VLSI Technology, Digest of Technical Pap
ers, pp. 29-30, 1988).

By applying these techniques, it is possible to secure the accumulated signal charges required for stable operation. A second problem for low-voltage operation is to simultaneously realize high-speed operation and low current consumption. A third problem is to realize an element or a circuit that enables integration of a low-voltage operation circuit and a high-voltage operation circuit on the same chip. The third problem becomes particularly problematic when the ratio between the voltage values of the high-voltage power supply and the low-voltage power supply is twice or more. By forming two types of elements for high voltage and low voltage on one chip,
An example of solving the above problem is disclosed in Japanese Patent Application No. 56-57143. According to this technique, a circuit can be configured with elements optimal for each of a low-voltage power supply and a high-voltage power supply, but there is a disadvantage that the LSI manufacturing process becomes complicated.
In the following embodiments, means for overcoming the second problem and operating even when the minimum power supply voltage is 1 V and a method for solving the third problem without complicating the manufacturing process will be described. Thus, the operating power supply voltage of the dynamic memory can be reduced to about 1 to 1.5 V, and the dynamic memory or an LS including the dynamic memory as a part thereof can be used.
High integration, high speed, and low power consumption of the I chip can be realized at the same time. Further, specifications required in the battery operation or the battery backup operation can be satisfied.

First, means for overcoming the second problem will be described. The complementary MOS-FET (Complem
Although an example using an entary MOS (CMOS) is shown, a bipolar transistor, a junction FET, or an element other than silicon may be used as long as a similar effect is obtained. FIG. 25A shows the relationship between the gate-source voltage VGS of the N-channel MOS-FET and the drain current ID. This relationship can be divided into (i) a square root region where the square root of ID is approximately proportional to VGS, and (ii) a subthreshold region where ID is proportional to the exponential function of VGS in a region where VGS is smaller than VGS. In the figure, VT1 is a so-called gate threshold voltage at which the drain current starts flowing when the current-voltage characteristic can be approximated by the square root, ignoring the region (ii). VT0 is another definition of the gate threshold voltage at which the drain current can be regarded as substantially zero in terms of circuit operation. Gate width 1
Assuming 0 μm, the drain current when VGS = VT0 is about 10 nA, and the drain current when VGS = VT1 is about 1 μA. The difference between VT1 and VT0 is about 0.2V
(VT1> VT0). VGS-VT1 is related to the actual current driving capability of the MOS-FET, and VT0 is related to the static current in the standby state. In the following example, the threshold voltage of the element used in the main circuit of the LSI is set so that VT1 = 0.3V (therefore, VT0 is about 0.1V). This allows the MOS-FET to be driven at half the power supply voltage (for example, 0.5 V).
Can be operated, and all the circuits can be operated up to the power supply voltage = 1 V. In addition, the standby current of the entire chip can be suppressed to about 10 μA.
Further, even if the threshold voltage varies by about ± 0.1 V due to variations in various manufacturing processes, the circuit operation at the power supply voltage = 1 V is realized and the standby current of the entire chip is reduced by 10%.
It can be suppressed to 0 μA or less. Power supply voltage = 1V
However, the channel length =
0.3 microns. FIG. 25 (b) shows two N channels.
It shows the channel length dependence of the gate threshold voltage VT1 for the MOS-FETs (Case I, Case II). Here, Case
I is a general condition of a conventional dynamic memory (hereinafter abbreviated as DRAM), a condition for applying a substrate bias voltage,
seII indicates the characteristics of the device used in the present invention corresponding to the condition where no substrate bias voltage is applied. In Case I, V
When BS = -1V, in Case II, the gate threshold voltage VT1 is set to 0.3V when VBS = 0V. The case II device has the following three problems.

(1) It is difficult to shorten the channel because the variation of the gate threshold voltage with respect to the variation of the channel length is large and the controllability is inferior to Case I.

(2) The substrate bias voltage is generated by a substrate bias voltage generation circuit provided on the chip.
The voltage value fluctuates due to manufacturing variations, and the value greatly fluctuates with time depending on the number of operating circuits. Since the gate threshold voltage is greatly modulated by the substrate bias voltage, the specification of the gate threshold voltage required for low-voltage operation cannot be satisfied with high accuracy.

(3) Since the substrate bias voltage is 0 V when the power is turned on, the gate threshold voltage is lower than 0.3 V, for example, 0 V due to the substrate effect.

At the same time, since the substrate is almost in a floating state, the substrate voltage transiently rises due to capacitive coupling with VCC, and the gate threshold voltage becomes negative. As a result, the MOS-FET of the peripheral circuit becomes conductive, and a large transient current flows. In the present invention, the substrate voltage is set to VSS = 0.
Since the gate voltage is fixed to V, an LSI chip having excellent controllability of the gate threshold voltage and having a small transient current at power-on can be provided. Furthermore, since the fluctuation of the substrate voltage during the operation of the circuit can be made almost zero, the capacitive coupling noise from the substrate voltage can be greatly reduced. If another means for setting the threshold voltage with high accuracy is used, the substrate bias voltage may be applied as in the conventional case.

FIG. 26 shows a gate oxide film thickness tOX, an electrical channel length (effective channel length) Leff, a gate threshold voltage VT1, and a gate oxide film thickness tox of elements used in a main circuit of a dynamic memory operating at a minimum power supply voltage of 1 V. VT0 is shown. Here, the values shown in parentheses indicate the range of variation due to manufacturing variations and the like.

FIG. 27 shows a part of a sectional structure of a dynamic memory chip of the present invention. The following three reasons apply a negative voltage to the substrate in the conventional dynamic memory.

(1) When a negative voltage due to ringing or the like is applied to the input or output from the outside, electrons serving as minority carriers are injected into the substrate. The electrons diffuse in the substrate, and a part of the electrons reach the charge storage portion of the memory cell, thereby deteriorating the refresh characteristics. The injection of the minority carrier into the substrate is prevented.

(2) By applying a negative voltage to the substrate, the junction capacitance between the n − diffusion layer and the p substrate is reduced, and the load capacitance is reduced. Thus, high-speed operation and low power consumption of the circuit are achieved.

(3) By applying a negative voltage to the substrate, the depletion layer below the channel expands, and the potential of the channel portion is less likely to be modulated by the substrate voltage.
As a result, the gate threshold voltage is less affected by the fluctuation of the substrate voltage. In other words, the substrate effect coefficient of the gate threshold voltage is reduced, which is convenient for the operation of some circuits of the dynamic memory. Of these, with regard to (3), the effect of applying the substrate voltage has been diminished along with the tendency of the CMOS-LSI to have a double well structure. Therefore, it is important to solve (1) and (2). Japanese Patent Application Laid-Open No. 62-119958 discloses a substrate structure in which a plurality of substrate voltages can be applied to a CMOS-LSI. By combining this structure with the low-voltage LSI according to the present invention, the above-described object can be achieved, and a low-voltage LSI with excellent noise resistance, high speed, and low power consumption can be configured. Hereinafter, embodiments of the present invention will be described with reference to the cross-sectional views of the substrate structure of the present invention. In FIG. 27, the impurity concentration of the P-type silicon substrate is about 1
× 1015cm + 3. Two types of N wells (N1, N2) and one type of P well formed by two different processes are formed in the substrate. The impurity concentration of each well is, for example, about 1 × 10 16 cm + 3 for the N2 well and about 5 × 10 16 cm + 3 for the N1 well and the P well, but these values may be changed according to the dimensions of the element. In the figure, 5
Reference numeral 0 denotes a thick oxide film (with a thickness of about 500 nm) for electrically separating active regions, 51 denotes a first polysilicon electrode for forming a storage capacitor, and 52 denotes a gate electrode of a MOS-FET. The second polysilicon electrodes 53 and 54 are N-type impurity diffusion layers (with an impurity concentration of about 2) formed in a self-aligned manner using these thick oxide films and polysilicon electrodes as masks.
.Times.10 @ 20 cm + 3), 55, 56, and 57 are P-type impurity diffusion layers (impurity concentration of about 2.times.10@20
cm + 3). The P substrate is fixed to the ground potential (VSS) by the diffusion layer 56. The storage capacity of the memory cell and the select transistors TN3 and TN4 are formed in a P-well electrically separated from the substrate by an N2 well. The second substrate potential VBP2 is applied to the P well by the diffusion layer 57. The N2 well has N1 electrically connected thereto.
A second N-well potential VBN2 is applied by the well and the diffusion layer. An N-channel MOS-FET TN1 of a peripheral circuit operated at VBS = 0 V is provided with a P-channel MOS-FET in a P substrate.
TP1 is formed in each of the N1 wells. Further, the N-channel MOS-FET TN2 of the peripheral circuit is formed in a P well different from the memory cell array and electrically separated from the P substrate. In this way, when a negative voltage such as an input / output circuit or a voltage higher than the voltage of the N-well may be input from the outside, an independent substrate voltage corresponding to the amount of overshoot or undershoot is applied. Can be applied. As described above, electrically separating the P well in which the memory cell array is formed from the P substrate has the following effects.

(1) By biasing the P well of the memory cell array to a negative potential, the data line capacity can be reduced and the signal-to-noise ratio can be improved.

(2) The N2 well covering the memory cell array serves as a barrier for minority carriers diffusing in the substrate. As a result, the collection of noise charges in the storage capacitor unit can be suppressed, and noise resistance is improved.

As described above, by using the substrate structure as shown in FIG. 27, the stable operation of the memory cell array and the high speed and low power consumption of the peripheral circuit can be realized at the same time. In the above description, the case where the P substrate is used has been described, but the same effect can be expected even if the N substrate is used. However, in the battery operation and battery backup operation targeted by the present invention,
Use in an environment where the power supply voltage fluctuates greatly must be considered. When an N substrate is used, the highest voltage VCC of the system is applied to the N substrate. Therefore, when the power supply voltage greatly fluctuates, the potential of the N substrate also fluctuates, and noise is induced in each part of the circuit by capacitive coupling with the N substrate. For these reasons, the structure using the P substrate shown in FIG. 27 is suitable for the purpose of the present invention.

FIGS. 28 to 30 show an example of an LSI circuit having an information holding function capable of further reducing the voltage according to the present invention. FIG. 28 shows an example of a peripheral circuit.
In the figure, reference numeral 60 denotes a circuit block which operates at the power supply voltage VCL1, and 6
Reference numeral 1 denotes a circuit block operated at the power supply voltage VCL2, VBP1 denotes a substrate bias voltage of the N-channel MOS-FET of the circuit block 61, and VBN1 denotes a substrate bias voltage of the P-channel MOS-FET of the circuit block 61. The circuit block 60 does not need to be operated when information is held, and VCL1 = 0 V when information is held. The circuit block 61 is required to operate even when information is held, and the value of VCL2 is constant regardless of the operation state. In order to operate the circuit up to the power supply voltage = about 0.5 V, the threshold voltage VT1 is set to 0 to
It needs to be about 0.1V. At this time, even when the circuit does not operate and the gate-source voltage is 0 V, the MOS-
A current of about 1 μA flows through the FET, and 10
It becomes a large current value of mA. In order to reduce the current consumption when information is held, it is necessary to reduce this static current. Generally, the operation speed may be slower at the time of information holding than at the time of the standard operation. Therefore, in this example, by controlling the substrate voltage, the threshold voltage of the MOS-FET at the time of information retention is more difficult to conduct than at the time of standard operation (the threshold voltage of the N-channel MOS-FET is higher and P Channel MOS-FET
Is lower). FIG. 29 shows N
Example of the configuration of the circuit for generating the substrate voltage VBP1 of the channel MOS-FET,
FIG. 30 is an operation timing chart thereof. Although the case where VCL2 = 1.5 V is described here for convenience, as described above, it is particularly effective when the power supply voltage is as low as about 0.5 to 1 V. In FIG. 29, reference numeral 62 denotes an everter I.
A ring oscillator constituted by 2 to I3 and a NAND gate G3, 63 is two diode-connected MOS-FETs T4
0, a charge pump circuit composed of T41 and a capacitor CB1, T42 and T43 are N-channel MOS-FETs T44 are P-channel M
OS-FETs are shown. During standard operation, ie P
When D is low voltage ("0"), the ring oscillator and the charge pump circuit do not operate. At the same time, the MOS-FET T44 conducts, and since the node N1 is at a high voltage ("1"), the MOS-F
ETT 42 becomes conductive and VBP1 becomes the ground potential. On the other hand, when information is held, that is, when the PD is at a high voltage ("1"), the MOS-FET T43 conducts and the node N1 becomes the same potential as VBP1, so that the MOS-FET T42 is cut off. At the same time, the ring oscillator and the charge pump circuit operate, and V
A negative voltage is output to BP1. Note that a substrate bias voltage is always applied to the memory cell array. As described above, by operating the substrate bias voltage when operating with a low-voltage power supply of 1 V or less, high-speed operation can be realized during standard operation and low power consumption can be realized when information is held. Although the description is omitted here, the present invention can be similarly applied to a circuit for generating VBN1.

In the following description, a specific circuit configuration of a low-voltage dynamic memory using the above-described substrate structure will be described. FIG. 31 shows a circuit configuration of the dynamic memory. In the figure, MA1 and MA2 are memory cell arrays, DA1 is a dummy cell array, W0 to Wm are word lines,
D0, D0￣, Dn, Dn￣ are data lines, DW0, DW1 are dummy word lines, XD is a word line selection circuit, DWD is a dummy word line selection circuit, and T52 to T55 control the connection between the left mat MA1 and the sense amplifier. Left select transistor, SHRL is the select signal, and T56 to T59 are the right mat M
A right mat selection transistor for controlling the connection between A2 and the sense amplifier, SHRR is the selection signal, PR0 to PRn are precharge circuits for setting the data line voltage to the potential P when not selected, φP￣ is a precharge signal, SA0 to SAn is a sense amplifier for amplifying a small signal voltage on the data line, CS
N and CSP are the common source drive signal of the sense amplifier, C
D is a common source drive circuit, YG0 to YGn are Y gates for connecting data lines and common I / O lines, YDEC is a Y address selection circuit, Y0 to Yn are Y selection signals, and DiB is a common I according to input data. A data input buffer for driving the / O line and a data output buffer DoB for amplifying and outputting the signal current of the common I / O line. As described above, the value of the storage capacitance CS2 of the memory cell is about 60 to 80 fF, and the value of the data line capacitance is about 250 to 300 fF. As a result, the read signal voltage when the amplitude of the data line is 1.5 V is about 150 mV, and a signal voltage sufficient for the operation of the sense amplifier can be obtained.

FIG. 32 shows voltage waveforms at various portions during data reading when the power supply voltage is 1.5 V. In addition,
The following description is for a read operation from a memory cell,
Consider the case where word line W0 is selected. The precharge voltage of the data line and the voltage of the opposite electrode (plate) of the cell storage capacitor are set to 0.75 V, which is half of the power supply voltage.
As a result, (1) the capacitive coupling noise generated at the time of charging / discharging or precharging the data line is minimized,
(2) The storage capacitance is increased by minimizing the voltage applied to the insulating film forming the storage capacitance and making the insulating film thinner. In order to write a high voltage (1.5 V) to a memory cell, a word line W0 and a left mat selection signal SHR are used.
2.2 V is applied to L, and transistors T50 and T5
2 operates in the unsaturated region. M of Y gate
The common I / O line is set to 1.2 V so that the OS-FET operates in the saturation region. A current detection type amplifier described in Japanese Patent Application No. 63-141703 is suitable as an amplifier for a signal on the common I / O line that operates even at such a low power supply voltage. Using this type of amplifier, (1) the voltage level of the common I / O line can be increased to near the power supply voltage, and (2) the signal amplitude of the common I / O line can be reduced (for example, 50 mV). , Y
The operation margin when reading the signal by applying the selection signal Y0 can be increased. When writing to the memory, the I / O line is connected to the data input buffer DiB as in the conventional case.
This can be achieved by driving with. At the time of holding the information, it is not necessary to read the information to the outside, so that the Y selection signal Y0 remains at the low voltage ("0") as shown by the broken line in the figure. Further, it is not necessary to operate the Y address selection circuit, the data input buffer, the data output buffer, and the like.
Further, the drive capability of the common source drive circuit of the sense amplifier is reduced, and the time change rate of the data line voltage is reduced. As a result, the value of the peak current accompanying the charging and discharging of the data line is reduced when information is held. By performing such control, even if a power supply having a high internal impedance such as a battery is used, it is possible to prevent the LSI from malfunctioning due to a transient drop in the power supply voltage. Below,
The following important circuits for realizing such a low-voltage dynamic memory will be described.

(1) 1/2 VCL generation circuit.

(2) Word line drive circuit.

(3) Common source drive circuit.

FIG. 33A shows a circuit configuration of a 1/2 VCL generating circuit. In the figure, T60 and T62 are N-channel MOS-
FETs, T61 and T63 are P-channel MOS-FETs, and R20 and R21 are resistors for setting a bias current. The ratio of the resistance values is selected so that the voltages at the nodes N4 and P are substantially half of VCL2. The capacitances CD1 to CD4 are speed-up capacitors provided so as to follow the fluctuation of the power supply voltage. CD1 値 CD between these values
2. CD3 ≒ CD4 holds. The substrate and source of each transistor are connected so that the threshold voltage does not increase due to the substrate bias effect. At this time, the absolute value of the threshold voltage VT1 of each transistor is about 0.3V. If the substrate is connected to the highest voltage of the system instead of the source, the absolute value of the threshold voltage VT1 becomes larger than 0.5V due to the substrate bias effect, so that the power supply voltage VCL2 = 1V
Will not work. As described above, in a circuit operating at a low voltage, the manner of applying the substrate voltage defines the minimum power supply voltage. When the substrate structure shown in FIG. 27 is used, the connection between the substrate and the source can be easily performed. FIG. 33 (b) shows an N-channel MOS-FET T60,
It shows a sectional structural view of T62. 65 is an n-diffusion layer for applying a potential of an N2 well, 66 is a p-diffusion layer for applying a potential of a P well, and 67 and 68 are N-channel MOS-Fs.
An n- diffusion layer serving as a source and a drain of the ET. P-diffusion layer 66 for applying MOS-FET substrate voltage by external wiring
Is connected to the source. The highest voltage of the system, here VCL2, is applied to the N2 well. As shown in this example, since the MOS-FET can be formed in a P-well electrically separated from the substrate, it is not affected by the body effect of the threshold voltage and is suitable for low-voltage operation. A circuit can be configured. Note that the present embodiment is not limited to the example shown here, and the present embodiment can be similarly applied to a circuit that operates a differential amplifier circuit and other sources at a voltage higher than the ground potential.

FIG. 34A shows the circuit configuration of the word line drive circuit, and FIG. 34B shows the operation timing thereof. In the figure, T82 is a memory cell transistor, CS3 is a storage capacitor,
T80 and T81 are N-channel MOS-FETs. This circuit is generally called a self boost circuit. A selection signal of the word line selection circuit is input to S. This voltage level is a high voltage (for example, 1.5 V) when selected and a low voltage (0 V) when not selected. Therefore, node N7
VCL-VT0 (VT0 is the threshold voltage of T81) when selected, and 0 V when not selected. After the selection signal is determined, a pulse voltage (for example, 2.2 V) higher than the power supply voltage is applied to X so that the memory cell transistor can be sufficiently turned on. When not selected, the MOS-FET T80 does not conduct, but when selected, due to the coupling of the gate capacitance of T80,
Node N7 is boosted to a high voltage. In order to output the pulse voltage applied to X as it is to the word line, the voltage of the node N7 is higher than the pulse voltage applied to X, for example, 2.2 + VT1 (VT1
Needs to be boosted to the threshold voltage of T80). When the substrate potential of the MOS-FET is set to the ground potential, the threshold voltage rises due to the body effect, so that it is difficult to obtain a predetermined amplitude on the word line especially with a low-voltage power supply having a VCL of 1.5 V or less. Here, in order to make the threshold voltage of the MOS-FET sufficiently low, the substrate potential is connected to the drain of the signal drive side (in this example, the selection signal S or the pulse voltage X) (here, for convenience, The drain was defined as the terminal to which the signal drive was applied). The cross-sectional structure diagram of this MOS-FET,
The equivalent circuits are shown in FIGS. 35 (a) and (b), respectively. The cross-sectional structure of the element is exactly the same as that shown in FIG. 33 (b), but the connection is different. Since the potential of the P well coincides with the potential of the drain, this is equivalent to the connection of a bipolar transistor having a drain as a collector and a base and a source as an emitter, as shown on the left side of FIG. . Actually, since the collector and the base are connected, the bipolar transistor operates as a diode, and is represented by an equivalent circuit as shown on the right side of FIG. Therefore, when the drain is higher than the source voltage, the MOS-FET whose substrate voltage is positively biased with respect to the source and the diode DL are connected in parallel. Conversely, when the drain is lower than the source voltage, the diode DL is connected. Is reverse biased and cut off, and only the MOS-FET connected to the drain whose substrate voltage is on the low voltage side operates. Therefore, the threshold voltage in the former case is lower than that in the latter case, and the MOS-FET becomes easier to conduct. At the same time, when the voltage difference between the drain and the source is 0.7 V or more, the diode conducts.
Further, the current easily flows. Therefore, in FIG. 34 (b), the MOS-FETs T80, T8
The threshold voltage of 1 can be set to a low value, and the drive signal X can be output to the word line as it is even at a low power supply voltage. Such an asymmetric characteristic is particularly effective when applied to a self-boosting circuit or the like.However, even when applied to a rectifier circuit used for a charge pump circuit of a pass gate or a substrate bias voltage generating circuit, for example,
Similarly, operation with a low voltage power supply is improved.

FIGS. 36A and 36B are diagrams showing one embodiment of the configuration of the common source drive circuit. Same figure
In (a), T85 and T86 are N driving a common source.
The channel MOS-FET, G5, is an AND gate. At the time of the standard operation, the signal PD # becomes a high voltage ("1"), and both T85 and T86 conduct in synchronization with the input of the common source drive signal φCS. On the other hand, when information is held, PD # goes low ("0"), and only T85 conducts with respect to the input of φCS. Therefore, by appropriately selecting the conductance of T85 and T86, the operation speed can be prioritized in the standard operation, and the peak current can be reduced instead of sacrificing the operation speed in the information holding. In FIG. 36 (b),
T90 is an N-channel MOS-FET that drives a common source, T9
1, T93 and T94 are N-channel MOS-FET, T92 is P-channel
MOS-FET, G6 is NAND gate, G7 is AND gate,
R25 indicates a resistor for supplying a bias current to T94. At the time of the standard operation, the signal PD becomes low voltage ("0"), and T93 is cut off. In synchronization with the input of φCS, the voltage of the node N8 becomes VCL and drives T90. When information is held, the signal PD becomes high voltage ("1"), and T92 is cut off. T93 conducts in synchronization with the input of φCS, and the voltage of the node N8 matches the gate voltage of T94. At this time, since a current mirror circuit is constituted by T90 and T94, the drive current of the common source is (VCL-VT1).
/ R25. Here, the proportional coefficient is determined by the ratio of the channel conductance of T90 and T94. By using such a drive circuit, when information is held, it is driven with a constant controlled current, so that stable operation is realized without causing a transient drop in the power supply voltage due to the internal impedance of the battery can do. Note that, other than the current mirror circuit shown here, other means may be used as long as the drive current can be controlled at the time of holding information.

With the substrate structure, element constants, and circuit configuration as described in the above embodiments, a dynamic memory that guarantees operation at the minimum power supply voltage = 1 V can be realized. Further, in addition to the circuit configuration of the I / O lines and the Y gate shown in FIG. The method of improving is disclosed in
1-1142594 and JP-A-61-170992. By applying this method, it is possible to realize a memory circuit that operates stably without being affected by element variations even at a low power supply voltage of about 1 V.

The configuration example of the main LSI circuit block that operates at a low internal power supply voltage of 1.5 V or less has been described above using a memory as an example. In addition, in order to realize the LSI chip as shown in FIG. 1, it is necessary to realize a circuit that operates at a high external power supply voltage (for example, 3 to 5 V). Such circuits include at least the following:
(1) Reference voltage generation circuit, (2) Voltage conversion (drop) circuit, (3) Input circuit, (4) Output circuit.

As shown in FIG. 26, a main LSI circuit block which operates at a low internal power supply voltage of 1.5 V or less has a state-of-the-art processing technology (for example, a gate length of 0.3) for the purpose of securing an operation speed. (Corresponding to a micron or less). In such a fine element, the gate breakdown voltage and the drain breakdown voltage are reduced, and a high external power supply voltage (for example, 3 to 5) is used.
Operation in V) becomes difficult. In this regard, for example, IED Technical Digest,
386-389 (1988), (IEDM Te
Chemical Digest, pp. 386-389, 1988). Considering long-term reliability, 1
The voltage that can be applied to the 0 nm gate oxide film is about 4V. Therefore, it can be applied to the gate oxide film. The maximum electric field intensity Emax is a value of about 4 MV / cm. Approximately Em
It can be considered that the value of ax does not depend on the gate oxide film thickness and does not substantially change (actually, when the gate oxide film is thinned, it tends to be somewhat large). Applying this value to the device shown in FIG. 26 (gate oxide film thickness tox = 6.5 nm),
The maximum voltage that can be applied to the gate is 2.7V. Therefore, this element is connected to a high external power supply voltage (for example, 3 to 5 V).
Can not work with The following two methods can be considered to solve this.

(1) As mentioned in the above description, in addition to the element used at the internal power supply voltage, an element operating at the external power supply voltage and having a thicker gate oxide film is integrated on the same chip.

(2) It is composed only of elements used at the internal power supply voltage. At this time, a circuit is devised so that the external power supply voltage is not directly applied to the element.

The method (1) is described in Japanese Patent Application No. 56-57143. However, this method complicates the manufacturing process of the LSI, and increases the manufacturing cost. Further, since many steps are inserted at the time of forming a gate oxide film, which is the most important in element formation, there is a problem that the probability of introducing impurities or defects is increased and the reliability of the element is reduced. Hereinafter, an example of realizing a circuit that operates at a high external power supply voltage by the method (2) will be described. In the following example, an example in which a complementary MOS-FET (CMOS) is used will be described. However, for example, a bipolar transistor or a junction transistor may be used, or these may be used in combination with a MOS-FET. In this case, the present invention can be similarly applied to a case where a semiconductor material such as gallium arsenide other than silicon is used.

FIG. 37A shows an example of the configuration of an inverter circuit according to the present invention. In the figure, T100 and T102 are N-channel MOS-FETs, T101 and T103 are P-channel MOS-FETs, in1,
in2 is the first and second common mode input terminals, out1 and out, respectively.
Reference numeral 2 denotes a first and second in-phase output terminals, Out denotes a third output terminal, and Vn and Vp denote bias power supply voltages for N-channel and P-channel MOS-FETs, respectively. Vn and Vp have, for example, an external power supply voltage dependency as shown in FIG. In this example, when VCC ≧ 2V, Vn
= 2V, Vp = Vcc -2V. This allows the output terminal o
Since the voltage of ut1 is at most Vn−VTN, the maximum voltage applied to the gate oxide film of the transistor T100 is Vn−
Limited to VTN. Similarly, the maximum voltage applied to the gate oxide film of the transistor T101 is VCC-Vp- | VTP |
Is limited to Here, VTN is the gate threshold voltage of T102 and VTP is the gate threshold voltage of T103. Two output terminals out1, out2
Signal levels are 0-Vn-VTN and VCC-Vp- |
VTP | ~ VCC, which are the inputs of the next inverter
1 and 2 are respectively driven. Further, 0 to Vcc, that is, full amplitude can be output to the third output Out.

FIG. 38 (b) shows the voltage at each node and the maximum voltage applied to the gate oxide film of each transistor when this inverter forms an inverter train. With this circuit configuration, for example, Vn = Vp = 1
In the case of / 2Vcc, the maximum voltage applied to the gate oxide film in any transistor is 1 / 2Vcc, and the maximum voltage applied simultaneously between the drain and the source is 1 / Vcc.
It is limited to 2VCC + VTN or 1 / 2VCC + │VTP│. Actually, from the viewpoint of securing the operation margin of the inverter, Vn and VCC-
Vp is preferably kept constant. Also, it is desirable that the channel conductance of T102 and T103 be larger than the channel conductance of T100 and T101, respectively, so that a large voltage is not applied between the drain and the source even when the output voltage changes transiently during switching. .

As described above, with this configuration, it is possible to realize a circuit that operates without deteriorating element characteristics up to a power supply voltage that is about twice the maximum voltage of the element. In addition,
In the example shown in FIG. 37 (a), the substrate potential of the N-channel MOS-FET is set to the lowest voltage of the system, that is, VSS, and the P-channel MOS-FET
The substrate potential of the FET is connected to the highest voltage of the system, that is, VCC, but if the substrate of each transistor is connected to the source using the above-mentioned substrate structure, the fluctuation of the threshold voltage due to the body effect is suppressed. And a circuit which operates even at a lower power supply voltage can be realized. Therefore, by applying the present invention, it is possible to provide an LSI that operates stably even with a power supply voltage of 5 V using only a MOS-FET using a thin oxide film of about 6.5 nm.

FIG. 39 (a) shows an inverter array (inverter chain) in which a plurality of stages of inverters whose substrate and source are connected to each other and whose operation characteristics are improved at a low power supply voltage are connected.
This is an example of the configuration. As with the conventional CMOS inverter train,
The connection can be made as it is without placing a level conversion circuit between the inverters. This makes it possible to configure a driver circuit that requires a large load driving capability, such as an output buffer. Assuming that the number of stages n is even, the input and output waveforms are as shown in FIG. In this example, VCC = 4V, Vn = 2V,
Vp = 2V. In this circuit, the amplitude of the output signal for driving the next-stage inverter is substantially constant (1.7 V) regardless of the power supply voltage. For this reason, the drive capability of the MOS-FET that charges and discharges the gate capacitance of the next-stage inverter does not depend on the power supply voltage, and the delay time from input to output (t
1-t0) becomes substantially constant regardless of the power supply voltage. Therefore, for example, the access time of the memory LSI is 1.5 to 5
Since there is almost no change even in a wide power supply voltage range of V, it is possible to provide an LSI chip which is convenient for configuring a system.

FIGS. 40A and 40B show examples of the configuration of the bias voltage Vn and Vp generating circuit shown in FIG. 37B. In the drawing, T114 to T117, in which the channel portion is indicated by a thick line, are N-channel MOS-FETs having a high threshold voltage, T112 and T113 are MOS-FETs for supplying a bias current, and 72 generates gate voltages of T112 and T113. Bias generators CN1 and CP1 for setting an optimum bias current are decoupling capacitors.
The value of the bias current is set by the resistance R30 and the ratio of the channel conductance of T113 and T112. An N-channel MOS-FET having a high threshold voltage is formed by forming a gate oxide film and then introducing a P-type impurity by ion implantation using a resist as a mask. In this example, the value of the threshold voltage is 1 V. Further, by using the above-described substrate structure and connecting the substrate to the source, fluctuation in threshold voltage due to the substrate effect is eliminated, and setting accuracy is improved. In addition, MOS-FET T112, T
113 operates as a current source. With this configuration, when the power supply voltage VCC is 2 V or more, the value of Vn becomes approximately twice the value of the high threshold voltage (about 2 V), and when VCC is 2 V or less, it becomes substantially equal to the power supply voltage VCC. Similarly,
When the power supply voltage VCC is 2V or more, the value of Vp is approximately VCC-2V, and when VCC is 2V or less, almost 0V
become.

FIG. 40B shows another example of the configuration of the bias voltage generating circuit. Although only the Vn generation circuit is shown here, the Vp generation circuit can be similarly configured. In the figure, T123 is an N-channel MOS-FET having a high threshold voltage, T121 is a P-channel MOS-FET supplying a bias current, and T120 and R
31 is a bias generation circuit for generating a gate voltage of T121 to set an optimum bias current, CN1 is a decoupling capacitor, and R32 and R33 are resistors. Assuming that the value of the threshold voltage of T123 is VTE, the value of Vn is VTE × (R32 + R33) /
It becomes R33. Therefore, by changing the ratio between R32 and R33, the value of Vn can be set to an arbitrary value equal to or higher than VTE. Thus, a bias voltage having the characteristics shown in FIG. 37B can be generated. Note that the resistor shown in this example may use any of a channel of a MOS-FET, an impurity diffusion layer, and a wiring layer such as polysilicon.

By the way, in a normal LSI, after the final manufacturing process, a voltage higher than the voltage used in the normal operation is intentionally applied to each transistor in the circuit, and a transistor which is originally liable to fail due to a gate oxide film defect or the like. An early aging test is performed to ensure reliability. FIG. 41A is a diagram showing one embodiment of how to apply the bias voltages Vn and Vp suitable for the aging test.
In this example, at a power supply voltage higher than where the magnitude relationship between Vn and Vp is reversed (4 V in this example), Vn = Vp = 1.
/ 2 VCC. In this way, during the aging test, Vn and Vp increase in proportion to the power supply voltage. Further, by reducing the value to half of the power supply voltage, for example, the maximum voltage is substantially equal between the transistors shown in FIG. 38 (a) to prevent stress from being concentrated on some transistors. I have.

FIG. 41B shows an embodiment of the configuration of the circuit for generating the bias voltages Vn and Vp. In the figure, reference numeral 72 denotes a maximum value output circuit which compares the voltages of two nodes N9 and N10 and outputs the maximum value, T140 and T141 denote N-channel MOS-FETs having a high threshold voltage, and R36 denotes a MOS-FET. R38 and R39 are for dividing the power supply voltage to obtain 1/2 Vcc.
R39. The maximum value output circuit is a differential amplifier circuit A10.
And A11, P-channel MOS-FET T142, T143, node N1
It is constituted by a resistor R37 provided to prevent the impedance to the ground side of 1 from becoming infinite. The operation of the maximum value output circuit is described in, for example, IEE Journal of Solid State Circuits, Vol. 23, No. 5, pp. 1128-1132 (19).
88) (IEEE Jounal of Solid-State Circuits,
Vol.23, No.5, pp.1128-1132, October
1988). A substantially constant voltage (2 V in this example) is input to the node N9 regardless of the power supply voltage. On the other hand, half the value of the power supply voltage is input to the node N10. Therefore, when the power supply voltage is 4 V or less, 2 V which is the maximum value of these two voltages is output to node N11, and when the power supply voltage is 4 V or more, 1/2 VCC is output. A circuit for generating the bias voltage Vp can be similarly configured. In this example, the case where the voltage value of the node N9 is 2 V is considered, but it may be set to an appropriate value in accordance with the maximum applicable voltage of the gate oxide film.

Japanese Patent Application No. 63-125742 discloses a MOS-FET.
2 shows a constant voltage generating circuit using the difference between the threshold voltages of the above. FIG. 42 shows an example of the configuration of a constant voltage generation circuit which is improved from the above and operates even with an external power supply voltage higher than the voltage that can be applied to the gate oxide film. In the figure, reference numeral 75 denotes a part newly inserted for this purpose, and T151 denotes N
A channel MOS-FET, T152, is a P-channel MOS-FET.
Thus, similarly to the inverter described above, the maximum applied voltage of any transistor in the circuit can be reduced to about half of the external power supply voltage. The value of the constant voltage generated by this circuit is two N-channel MOS-FETs as described in Japanese Patent Application No. 63-125742.
Difference VT1 between threshold voltages T149 and T150 (T149) -VT1
(T150). T149 is a transistor having a high threshold voltage as shown in FIG. In this example, VT1 (T149) = 1.05 V, VT1 (T150) = 0.3
As V, an output voltage Vref = 0.75V is obtained.

FIG. 43 shows a configuration example of the differential amplifier circuit according to the present invention. In the figure, T161 and T162 are two N-channel MOS-FETs for inputting a differential signal, and T160 is an N-channel MOSFET for supplying a bias current to a differential amplifier circuit.
S-FET, B1 is a signal for setting its bias current,
T163 and T164 are two P-channel MOS-FETs constituting a current mirror type load. In a normal differential amplifier circuit, the nodes N13 and N15 and the node N14 and the output out2 are connected. In this case, circuit blocks indicated by reference numerals 76 and 77 in the figure are added, and an external voltage higher than a voltage that can be applied to the gate oxide film is added. It works with power supply voltage.

In FIG. 43 (a), 76 is defined as two N-channel M
OS-FET T165 and T166, and P-channel MOS-FET T1
67. This allows the transistor
The maximum voltage applied to the drains (N13, N14) of T161 and T162 is Vn-VTN1 and the minimum voltage applied to the drain (out2) of transistor T164 is Vp.
+ | VTP1 |. Here, VTN1 and VTP1 represent the threshold voltages of the N-channel and P-channel MOS-FETs, respectively. As Vn and Vp, the bias voltages having the power supply voltage dependency shown in FIGS. 37B and 41A can be used as they are, as in the previous embodiment. Now, when the differential amplifier circuit shown in FIG. 43A operates as a small signal amplifier circuit, that is, when there is no large difference between the two input levels and both the transistors T161 and T162 operate in the saturation region, The voltage at node 14 is approximately Vn-VTN1. Therefore, even if the transistor T167 is omitted as shown in FIG.
No large voltage difference occurs between the gate and the drain of T164. When used only as a small signal amplifier circuit, the circuit system shown in FIG. 43 (b) having a simple configuration is suitable. The signal level of the output out2 of these differential amplifier circuits is equal to the signal level of the output out2 of the inverter shown in FIG. 37 (a), and the output of the differential amplifier circuit can directly drive the input in2 of the inverter. It is convenient to form a circuit by combining them. In the above configuration example of the differential amplifier circuit, the input In
When the voltage levels of (+) and In (-) are equal to or lower than Vn-VTN1, a large voltage gain is obtained. Conversely, when operating at an input voltage level higher than Vp + | VTP1 |, an N-channel MOS-FET and a P-channel MOS-FET constituting a differential amplifier circuit are used as a P-channel.
Each channel is replaced with a lower voltage level (the signal level of the output out1 of the inverter shown in FIG. 37A).
The configuration may be such that the output is obtained. Again,
The same effect as in the case of the above configuration can be obtained. Next, an example in which this differential amplifier circuit is applied to an LSI chip circuit will be described.

FIGS. 44 to 46 show examples in which the present invention is applied to a VL (reference voltage) generating circuit which is a reference of the internal power supply voltage VCL. 44, reference numeral 80 denotes a VL (reference voltage) generation circuit corresponding to 9 in FIG. 1, A15 denotes a differential amplifier circuit,
R50 and R51 are resistors for setting the amplification factor. The VL generation circuit includes a constant voltage (Vref) generation circuit 81 described with reference to FIG. 42, an aging voltage (VA) generation circuit 82 for generating a voltage higher than a voltage at the time of standard operation during an aging test, A maximum value output circuit 83 that compares Vref and VA and outputs the larger voltage;
A switch 84. Since the voltage characteristic of the aging test is not required at the time of information holding, the maximum value output circuit is deactivated and the switch is closed to directly output Vref. By the way, in this example, Vr
ef = 0.75V, VA = 1 / 5VCC, and the power supply voltage is 3.
The aging test state is set when the voltage is 75 V or more. That is, when the power supply voltage is 3.75 V or less, VL = 0.75 V, and when the power supply voltage is 3.75 V or more, VL =
1/5 VCC is output. When R50 = R51, the amplification factor is set to 2, and when the power supply voltage is 3.75 V or less, VC
When L = 1.5V, 3.75V or more, VL = ２Vcc
Is applied to the circuit as an internal power supply voltage.

FIG. 45 shows the dependency of each voltage on the external power supply voltage VCC.
Shown in Thereby, the power supply voltage of the internal circuit is 1.5 V in the standard operation state (for example, the power supply voltage is 3 to 3.6 V),
In the aging test state (for example, when the power supply voltage is 5.3 V), 2.1 V is obtained. FIG. 46 shows a more detailed configuration example of the VL (reference voltage) generation circuit. In FIG.
0 is a maximum value output circuit, and T179 is an N-channel MOS-FET that operates as a switch. The maximum value output circuit is composed of two operational amplifier circuits 90a and 90b, P-channel MOS-FETs T177 and T1 driven by the outputs of the respective differential amplifiers.
78, a P-channel MOS-FET T177 for relaxing the voltage applied to the gate oxide film of T177 and T178, and an N-channel MOS-FET for lowering the impedance of the output terminal N22 to the ground.
And FET T175. Here, the two differential amplifiers 90a and 90b are the same as those shown in FIG. The configuration of the maximum value output circuit is basically the same as that shown in FIG. With this configuration, it is possible to obtain a maximum value output circuit that operates with a power supply voltage higher than the maximum applicable voltage of the gate oxide film. In the information holding state, the transistor T179 is turned on to output Vref as VL. In addition, current consumption is reduced by disabling the maximum value output circuit.

FIG. 47 is a circuit diagram showing the structure of the limiter and the limiter described in FIG.
2 shows a configuration of an enable signal (LM) generating circuit.
43, A12 and A13 are single-ended type differential amplifier circuits having the same configuration as that shown in FIG. 43 (a), and 95 has two outputs of the differential amplifier circuit as inputs and a large equal to the power supply voltage difference. 1 shows a double-ended differential amplifier circuit that outputs a signal. The double-ended differential amplifier circuit is a P-channel MOS-FET T180 driven by two inputs.
, T181, P-channel MOS-FETs T184 and T185 for relaxing the voltage applied to the gate oxide film, two cross-coupled N-channel MOS-FETs T182 and T183, and the voltage applied to the gate oxide film And N-channel MOS-FETs T186 and T187 for alleviating the power loss, and speed-up capacitors CC1 and CC2 provided to accelerate the speed at which the output is inverted. Among them, the speed-up capacitor determines the response speed of the circuit, and the basic operation is not impaired even if omitted depending on the application.

The operation will be described below with reference to the operation timing chart shown in FIG. In the following description, the case where the internal power supply voltage VCL in the standard operation state is 1.5 V (VL
= 0.75V). As shown in the figure, when the external power supply voltage VCC decreases from 4 V to 1 V, the voltages of the outputs (nodes N25 and N26) of the differential amplifier circuits A12 and A13 at time t0 when half the voltage of VCC crosses 0.75V. Is inverted. As a result, the transistor T180 shifts to the cutoff state, T181 shifts to the on state, and the node N28
Voltage rises to VCC. In synchronization with this, node N3
The potential of 0 is Vn-VTN1 (VTN1 is the threshold voltage of T187)
And the potential at the node N29 and further at the node N27 is pulled down to the ground potential. As a result, the voltages at the outputs N27 and N28 of the double-ended type differential amplifier circuit are inverted to 0V and VCC = 1V, respectively. FIG. 48 schematically shows the operation, but actually, a series of these operations are performed in a sufficiently short time as compared with a change in the power supply voltage. Therefore, a change in the power supply voltage does not adversely affect the circuit operation. Further, by consciously providing a capacitance in the power supply wiring in the chip, a change in the power supply voltage can be controlled, and the influence on the circuit operation can be suppressed to a lower level. In the above, the case where the external power supply voltage is decreased has been described. Conversely, the same operation is performed when the external power supply voltage is increased.

Now, the LSI chip according to the present invention is replaced with another L chip.
When a system is configured using an SI or a semiconductor element, it is necessary to match input / output levels of signals exchanged between them. There are the following two standard input / output levels in an LSI that operates on a single power supply (generally, 5 V). (A) TTL level, (b) C
MOS level.

Among them, at the TTL level, the value of the high voltage (“1”) output (VOH) must be 2.4 V or more. Therefore, when the power supply voltage is used at 2.4 V or less, it is necessary to use a CMOS level or to set a new input / output level standard. Conventional LSI and T
When configuring a system together with a TL logic circuit or the like, it is important to ensure compatibility with the input / output levels described above. Compatibility eliminates the need for a level conversion circuit, reduces the number of components, and reduces the cost of the system. In addition, circuit performance such as noise resistance and speed has been improved,
Maximum performance can be demonstrated. Therefore, an embodiment of the present invention having an input / output circuit configuration that maintains compatibility with the conventional input / output level will be described below. According to the present invention, the following three product specifications can be realized using one chip without design change.

(1) TTL at the time of standard operation (for example, when the power supply voltage VCC is 4.5 to 5.5 V or 3 to 3.6 V)
Input and output at the level. If necessary, a decrease in VCC (for example, when the power supply voltage VCC is 1.0 to 2.5 V) is detected in the chip, and information is held (battery backup).

(2) When the power supply voltage VCC is, for example, 1.0 to
It operates at 5.5V, and inputs and outputs are at CMOS level. If necessary, lower VCC (for example, when power supply voltage VCC is 1.0 to
2.5V) is detected in the chip, or information is held (battery backup) by an external control signal or the like.

(3) When the power supply voltage VCC is, for example, 1.0 to
It operates at 5.5V, and the chip automatically switches the input / output level according to the value of the power supply voltage. For example, power supply voltage VCC
When the power supply voltage is 2.5 to 5.5 V, input / output is performed at the TTL level, and when the power supply voltage is 1.0 to 2.5 V, input / output is performed at the CMOS level.

FIG. 49 (a) shows a case in which switching by wiring or bonding is performed using one chip.
FIG. 49 (b) shows an example of realizing two products of (2) and (2).
Examples of products that automatically detect a change in the value of the power supply voltage and switch input / output levels are shown. FIG.
1A, 1 is an LSI chip, 5 is an LSI circuit block operating at an internal power supply voltage (for example, 1.5 V), PA
DT is an input / output pad for TTL level, PADC is CMO
Input / output pads for S level, IB1 and OB1 are TTL
Level input buffer and output buffer, IB2 and OB2 are CMOS level input and output buffers, and SW1 is for selecting one of the outputs of the two input buffers to be input to the low voltage operation LSI circuit block. A switch SW0 indicates a switch for selecting which of the two output buffers receives the output of the low voltage operation LSI circuit block. As a method of performing this switching in an actual LSI, there is a master slice using wiring such as aluminum. This is a method in which, when a wiring layer of aluminum or the like is formed, two types of masks for transferring a wiring pattern are prepared corresponding to the above-mentioned switches, and the masks are used properly according to products. Furthermore, two types of bonding pads corresponding to the input / output levels are provided on the LSI, and by bonding one of them, two products can be made separately. Alternatively, one bonding pad may be provided, and the connection with the input / output buffer may be switched by a master slice using wiring such as aluminum.

FIG. 49 (b) shows a method of switching the input / output level of one input / output buffer. In the figure, PADX is an input / output pad, IB3 and OB3 are input and output buffers, and 96 is an input / output level setting circuit for controlling the input / output level of each buffer according to the power supply voltage. Regarding this, a more specific configuration example will be described later. With the above configuration, the above-described three product specifications can be realized by one chip, which is convenient from the viewpoint of the cost of the product and the usability of the user. In the above example, an example of the so-called I / O common system in which input and output are performed from the same terminal has been described. However, the present invention can be applied to the case of only input or output only. Can be similarly applied. Hereinafter, a specific configuration example of each of the output buffer, the input buffer, and the input protection circuit will be described. In the following embodiment, a case will be described in which a circuit is constituted by a MOS-FET having a thin (for example, 6.5 nm) gate oxide film used for an internal circuit. The present invention can be similarly applied to a case where a MOS-FET having a kind of gate oxide film is used.

In forming the output buffer, the internal low signal amplitude (for example, 1.5 V) to the external high signal amplitude (for example, TTL level of 2.4 V, CMOS level of 5 V when the power supply voltage is 5 V, 5 V) ) Needs to be converted to amplitude. First, an example of a circuit configuration for obtaining a CMOS level output signal will be described. FIG. 50A shows an example of the configuration of an amplitude conversion circuit that receives a low signal amplitude in1 of an internal circuit and outputs a high signal amplitude Out. In the figure, 98
Is the inverter circuit shown in FIG.
Are the two inputs corresponding to in2 and in1 in FIG. 37 (a), Out is the output of the inverter, T190 is an N-channel MOS-FET driving N32, T191 is the gate of T190 by limiting the maximum voltage of the node N32. An N-channel MOS-FET for relaxing the voltage applied to the oxide film, T192 similarly indicates a P-channel MOS-FET for limiting the minimum voltage of the node N31, and R65 indicates a resistor. Among them, the transistor T190 and the resistor R65 constitute an inverter circuit having a resistive load.
By using a resistive load, two outputs on the low voltage side and the high voltage side can be obtained from one input on the low voltage side.

Next, the operation of this circuit will be described with reference to FIG. In the following example, it is assumed that the power supply voltage is 5 V and the bias voltages Vn and Vp are both 2.5 V. When the input in1 is at 0V, the transistor T190 is cut off, and the node N31 is pulled up to 5V by the resistor R65. The node N32 is connected to Vn (2.
5V) (2 V), which is lower by the threshold voltage (for example, 0.5 V) of the transistor T191. Therefore, the voltage of the output Out of the inverter 98 is 0V. When the input in1 rises from 0V to 1.5V at time t0, the transistor T190 conducts and the node N31
Is higher than Vp (2.5 V) by the absolute value (for example, 0.5 V) of the threshold voltage of the transistor T192 (3 V).
Node N32 is pulled down to 0V and output Out rises to 5V. At time t1, the input in1 changes from 1.5 V to 0
Similarly, when the voltage falls to V, the output Out also changes from 5V to 0V. Thus, with this circuit configuration,
For an input signal amplitude of 1.5 V, an output signal amplitude of 5 V required in the output buffer is obtained. Further, in this circuit, a voltage of only about 2.5 V at the maximum is applied to any transistor. Therefore, a circuit that can operate stably with a power supply voltage of 5 V even with a MOS-FET using a thin gate oxide film (for example, 6.5 nm). Can be configured.

FIG. 51 (a) shows another configuration example of an amplitude conversion circuit which receives complementary low amplitude signals in1 and in1 お よ び and outputs a high signal amplitude Out, and FIG. 51 (b) shows the operation timing thereof. ing. In the figure, reference numeral 102 denotes a double-ended input / double-ended output differential amplifier circuit having the same configuration as that shown in FIG.
Shows the same inverter circuit as that shown in FIG. The double-ended output differential amplifier circuit used here does not conduct current in a steady state, so that a circuit with lower power consumption can be realized as compared with the above-described example. The substrate (back gate) of each transistor constituting the inverter of the final output stage is biased to minus (−2 V) in the N channel and to plus (7 V) with respect to the power supply voltage (5 V) in the P channel. Thus, for example, even if an undershoot or overshoot due to impedance mismatch appears in the output, it is possible to prevent the PN junction from being biased in the forward direction. Therefore, it is possible to prevent the injection of minority carriers into the substrate (refreshing characteristics deteriorate when the minority carriers diffuse to the charge storage node of the memory cell), and prevent latch-up caused by turning on the parasitic thyristor. As described above, according to the present invention, a circuit that outputs a high-amplitude signal (for example, 5 V) at the CMOS level from a low-amplitude signal (for example, 1.5 V) of the internal circuit can be easily configured.

In general, when configuring a system, the outputs of a plurality of LSIs are connected to one data bus, and only the output of the selected LSI drives the bus.
In order to perform such control, it is desirable to make the output impedance of an unselected LSI infinite. Conventional LSIs have three output (tri-state) characteristics, namely, high voltage, low voltage, and no driving (the output impedance is infinite) as output levels. In order to obtain such characteristics, it is necessary to control whether the output is driven (low impedance) or not (infinite impedance). The signal for this control is generated from any of an externally input output enable signal (Output Enable = OE) and a chip select signal (Chip Select = CS). In a conventional output circuit, a tri-state characteristic is realized by taking a logic of these signals and output data, and driving a final-stage transistor by a signal obtained as a result. In the case of configuring a similar output circuit in the present invention, there may be a configuration in which a logic circuit is operated at a low power supply voltage and a logic circuit is not used for a circuit operated at an external power supply voltage. However, in this case, the number of stages of the amplitude conversion circuit and the inverter between the logic circuit and the output increases, and for example, the delay time from the OE signal to the output increases, or the timing for driving the high-voltage transistor is increased. There is a disadvantage in that a difference occurs in the timing of driving the transistor on the low voltage side and a large current flows transiently. On the other hand, if a logic circuit can be constituted by an external power supply voltage, the degree of freedom in design is further increased, which is preferable also from the viewpoint of circuit performance. Hereinafter, an embodiment in which a logic circuit is configured by an external power supply voltage will be described. Note that this logic circuit is also effective as means for generating control signals for various circuits that operate on the external power supply voltage, in addition to the output buffer.

FIG. 52 shows a configuration example of a two-input NAND circuit according to the present invention. The A input of FIG. 52 (a) is the same as FIG.
In1A and in2A, B input is in1B and in2B
Respectively. Of each input signal, in1A and in2
A, in1B and in2B correspond to in1 and in2 in FIG.
Similarly, changes in phase. In FIG. 52B, the transistors T200 and T201 are connected to the low-voltage side input signal in1A and
The transistors T202 and T203 are driven by the input signals in2A and in2B on the high voltage side. The transistors T204 and T205 correspond to T202 and T205 in FIG.
Like 203, it is provided to operate at a voltage higher than the voltage that can be applied to the gate oxide film. With this configuration, the function of the NAND gate in which the output is low only when both inputs are high is obtained. Thus, a fine transistor can be used at a high power supply voltage only by adding two transistors in addition to a normal CMOS NAND circuit. Here, the description has been given by taking a two-input NAND circuit as an example, but other
For example, a NOR circuit, an exclusive OR circuit, the above-described logic circuit having three or more inputs, a composite gate which outputs various composite logics by using outputs of a plurality of logic circuits as inputs,
The present invention can be similarly applied to sequential circuits such as a latch circuit and a flip-flop circuit.

FIG. 53 (a) shows an example of the configuration of a tri-state output buffer using this logic circuit. FIG. 53 (b) shows this simplified with a logical symbol. In the figure, G12 is a two-input NAND circuit,
G13 is a two-input NOR circuit, and T210 and T211 are N-channel and P-channel MOS-FETs constituting an output circuit. When the output enable signal OE is at a high voltage, the same data as the input do is output from the buffer at the output Do. When the OE is at a low voltage, the gate of T210 is at a low voltage and the gate of T211 is irrespective of the input data. Is fixed to a high voltage, the output Do becomes floating (impedance is almost infinite). FIG. 53 (a) is a specific configuration example of a circuit having the same function, which is configured using a fine element having a withstand voltage lower than the value of the external power supply voltage. In the figure, 112 is a NAND circuit, 113 is N
OR circuit, 114 is an output circuit, 110 and 111 are FIG.
This is the same amplitude conversion circuit as 102 in (a). The amplitude conversion circuit is a low-amplitude signal do1, oe on the low power supply voltage side from the internal circuit.
Based on 1, oe1 #, signals do2, oe2, oe2 # on the high power supply voltage necessary to operate 112 and 113 are generated. As described herein, according to the present invention, even when a fine element is used, a logic circuit that operates with an external power supply voltage exceeding its withstand voltage can be configured, and delay time and transient current of a tri-state output circuit and the like can be reduced. can do.

Next, an example of a CMOS level input circuit is shown in FIG.
4 will be described. In the figure, reference numeral 115 denotes FIG.
The inverters T220 and T221 which are the same as those shown in FIG.
A transistor X for limiting the voltage applied to the gate oxide film of 2 and T223 to the oxide film breakdown voltage or less, and X is an input signal. In this figure, a high voltage (for example, 5
V) is applied, the voltage applied to the node N40 is Vn-
VT1 (T220), that is, about 2V. Similarly, even when a low voltage (for example, 0 V) is applied to the input, the minimum value of the voltage applied to the node N41 is about 3 V, and the voltage applied to each transistor is reduced to about half of the power supply voltage. Can be. Further, since the signal amplitude of x1￣, which is one of the outputs of this circuit, is about 2 V, this can be used as it is as an input to an internal circuit that operates at a low power supply voltage.

In the above embodiments, examples of CMOS-level output circuits and input circuits have been described. Next, FIG. 55 shows an example of an input circuit and an output circuit which automatically switch between the TTL level and the CMOS level according to the value of the power supply voltage.
In the figure, PADI indicates an input pad, PAD0 indicates an output pad, IPD indicates an input protection element for preventing junction and gate destruction due to static electricity, IB5 indicates an input buffer, and OB5 indicates an output buffer. The input protection element will be described later in detail. The input buffer IB5 is
The two MOS-FETs TIN1 and TIP1 constituting the CMOS inverter, the N-channel MOS-FET TIN2 for limiting the power supply voltage of the CMOS inverter to a predetermined value or less determined by the bias voltage Vn1, and the input voltage of the CMOS inverter are similarly predetermined. N-channel MOS-FE to limit the value below
T TIN0. The output buffer OB5
Is an inverter 116 similar to that shown in FIG.
An amplitude conversion circuit 11 for generating inverter drive signals d1 and d2 based on a low amplitude signal dout from an internal circuit.
7. N-channel MOS-FET for limiting the output voltage of the inverter to a predetermined value or less determined by the bias voltage Vnt
TON2. It is needless to say that a buffer having a tri-state output characteristic can be configured by taking the logic with the output enable signal as in the case shown in FIG. In these circuits, when the value of the bias voltage Vn1 is appropriately changed in accordance with the power supply voltage, input and output can be performed at a TTL level at a high power supply voltage and at a CMOS level at a low power supply voltage.

FIG. 56 shows an example of the dependency of the value of the bias voltage Vn1 on the power supply voltage VCC. In the figure, VOL and VOH are T0 corresponding to "0" and "1", respectively.
The TL output levels VIL and VIH indicate the TTL input levels corresponding to "0" and "1", respectively. These values in a normal TTL logic gate are given by TOL =
0.4V, VOH = 2.4V, VIL = 0.8V, and VIH
= 2.0V. The value of the bias voltage Vn1 is 3 V when the power supply voltage is 2.5 V or more, and the value of the bias voltage Vn1 is 2.5 V.
When the voltage is equal to or lower than V, control is performed so that TIN0 operates in the non-saturation region, for example, Vcc + 0.5V.
First, the operation of the output buffer circuit will be described. The voltage of the node N48 is 0 when outputting a low voltage (“0”).
When it outputs V and high voltage ("1"), it becomes VCC.
Therefore, at the time of low voltage output, 0
V is output to Dout. On the other hand, the voltage value of Dout at the time of high voltage output depends on the value of the power supply voltage VCC as shown in FIG.
When VCC ≧ 3V, Vn1−VT1 (TON2), VCC <3
When V is Vcc. As a result, the power supply voltage becomes 3 V
As described above, an output voltage amplitude satisfying the TTL level output characteristics can be obtained. By limiting the output voltage to 2.5 V or less in this manner, the power supply current when charging and discharging a large load capacity can be reduced to a necessary minimum.

Next, the operation of the input buffer circuit will be described. The power supply voltage of the CMOS inverter constituted by TIN1 and TIP1 is supplied from the source terminal of the transistor TIN2. Therefore, the value is 2.5 V when the power supply voltage is 3 V or more and 0 V when the power supply voltage is 3 V or less.
On the other hand, when the power supply voltage is 3 V or more, the input voltage of the inverter is limited to 2.5 V or less, and when it is 3 V or less, the voltage input to Din is applied as it is.
With this circuit configuration, the power supply voltage is changed from 1 V to 5.5, for example.
Even if the voltage greatly changes to V, the power supply voltage of the inverter becomes substantially equal to the maximum amplitude of the input signal. If the channel conductance of the two transistors constituting the inverter is set to be substantially equal, the logical threshold voltage of the inverter will be 分 の of the power supply voltage. Therefore, the logic threshold voltage when the power supply voltage is 3 V or more is about 1.25
V and 3V, the logical threshold voltage is VCC / 2, and operates at a TTL level at a power supply voltage higher than a certain voltage (3V in this example) and at a CMOS level at a lower power supply voltage. Input buffer can be provided. As described above, according to the present invention, in an LSI having a wide operating power supply voltage range, it is possible to operate at an optimum input / output level at the power supply voltage value. Thereby, the maximum noise margin can be realized with the minimum power consumption. In the output buffer, the substrates (back gates) of the three transistors TON0, TON1, and TON2 are shared. By doing this,
When a high voltage surge is applied to the output terminal, the charge can be discharged at a high speed by a large current. This is because the clamp MOS-
As with the operation of the FET, when the substrate potential increases due to the breakdown, the parasitic bipolar transistor existing between the substrate potential and the ground potential is easily turned on. As a result, even if a fine element is used, the electrostatic breakdown voltage of the output terminal can be improved. In the above embodiment, N
Usually, the value of the substrate voltage VBP1 of the channel MOS-FET is set to a negative value (for example, -3 V) so that the PN junction is not biased in the forward direction when the input voltage becomes negative (undershoot). However, 0 V may be used as long as the forward current is allowed to flow. The N-channel MOS-FET may be formed in a P-type substrate, or may be formed in a P-well electrically insulated from the P-type substrate as shown in FIG. In the latter case, since the resistance of the P-well is lower than the resistance of the substrate, the parasitic bipolar transistor is easily turned on, and has an effect of increasing the electrostatic breakdown voltage.

In the above embodiment, it is necessary to generate the bias voltage Vn1 higher than the power supply voltage. FIG. 57 shows an example in which an input buffer is configured without using such a bias voltage.
Shown in In the figure, an input buffer IB6 is composed of two circuit blocks, IB6a and IB6b. I
B6a has the same circuit configuration as the input buffer IB5 of FIG. IB6b is a circuit that converts the output of IB6a to a voltage level convenient for driving an internal circuit. I
In B6b, T231 and T232 are two MOS-FETs constituting a CMOS inverter, T232 is a P-channel MOS-FET for raising the potential of the node N52 to the internal power supply voltage VCL when din is low, and T230 is a node N52. This is an N-channel MOS-FET for preventing a current from flowing from N52 to N51 from flowing backward when the voltage becomes high. FIG. 58 shows the dependency of the bias voltage Vn2 on the power supply voltage VCC in this circuit configuration. 3 V when power supply voltage is 3 V or more
(Constant), when the power supply voltage is 3 V or less, the power supply voltage VCC
To be equal to The operation of this circuit will be described for two cases. FIG. 59 shows that the power supply voltage VCC is 5
5 shows operation waveforms of various parts when V and the internal power supply voltage VCL are 1.5V. When the input voltage is low (for example, 0.4)
V), the voltage at the node N51 is Vn2-VT1 (TIN
5) (for example, 2.5 V), and the voltage of the node N52 is VCL (1.
5V), and a low voltage (0 V) is output to din.
When the input voltage changes from a low voltage (e.g., 0.4V) to a high voltage (e.g., 2.4V), the voltage at node N50 rises accordingly, pulling down the voltage at node N51 to 0V. The channel conductance of T230 is set larger than that of T233, and the voltage of node N52 is almost zero.
And the value of din rises to VCL (1.5V). Conversely, if the input voltage is high (eg, 2.
4V) to a low voltage (e.g., 0.4 V), the voltage at node N50 falls following it, and the voltage at node N51 drops.
Is raised to Vn2-VT1 (TIN5) (for example, 2.5 V). As a result, the voltage of the node N52 becomes VCL-VT
1 (T230) (for example, 1.2V), din
To 0V. As a result, T233 is turned on, and the voltage of the node N52 is changed from VCL-VT1 (T230) to VCL (1.5 V).
Up to In this manner, the node N52 is
, The voltage amplitude of N52 becomes the same as the power supply voltage, and a through current can be prevented from flowing through the CMOS inverter constituted by T231 and T232.

FIG. 60 shows the operation waveforms of the respective parts when the power supply voltage VCC and the internal power supply voltage VCL are both 1.5 V. When the input voltage is low (for example, 0V),
The voltage at the node N51 is Vn2-VT1 (TIN5) (for example, 1.
2V), the voltage of the node N52 becomes VCL (1.5V),
A low voltage (0 V) is output to din. When the input voltage changes from a low voltage (for example, 0 V) to a high voltage (for example, 1.5 V), the voltage of the node N50 becomes Vn2-VT1 (TIN5).
(For example, 1.2 V), and the voltage of the node N51 becomes 0
Drop to V The channel conductance of T230 is T233
, The voltage of the node N52 is also pulled down to almost 0 V, and the value of din becomes VCL (1.5
V). Conversely, when the input voltage changes from a high voltage (for example, 1.5 V) to a low voltage (for example, 0 V), the voltage at the node N50 falls to 0V following the voltage, and the voltage at the node N51 is reduced to Vn2-VT1. (TIN5) (for example, 1.2V). Thereby, the node N52
Is raised to VCL-VT1 (T230) (for example, 1.2V), and din is reduced to 0V. As a result, T233
Turns on, and raises the voltage of the node N52 from VCL-VT1 (T230) to VCL (1.5 V). As described above, even when the power supply voltage is low and the output amplitude of IB6a is equal to or less than the power supply voltage, the voltage amplitude of node N52 becomes the same as the power supply voltage. No current flows. As described above, it is possible to realize an input / output buffer that switches its input / output level according to the value of the power supply voltage without using a bias voltage higher than the power supply voltage.

Finally, the LS composed of fine elements
FIG. 61 shows a configuration example of an input protection element for protecting an element of an internal circuit from an input surge in I. In the figure, PADI is an input pad for inputting a signal, and 120 is a first protection element for releasing a high voltage due to a surge to a ground potential by using punch-through between impurity diffusion layers formed in a semiconductor substrate. , 121 are gate clamp elements for limiting the voltage of the node N60 to a predetermined voltage or lower, and R70 is a resistor for absorbing the difference between the high voltage applied to the pad and the clamp voltage. The gate clamp element is composed of two N-channel MOS-FETs T connected in series.
PD1 and TPD2, and a bipolar transistor Q1 utilizing a parasitic element. A bias voltage Vn is applied to the gate of TPD1, similarly to the above-mentioned circuit, to prevent a voltage exceeding the gate oxide film breakdown voltage from being applied to the drain of TPD2. The gate of TPD2 is grounded to prevent current from flowing through the two MOS-FETs during normal operation.

FIG. 62 shows the planar structure of the gate clamp element.
FIG. 63 shows the cross-sectional structures at A and A '. In FIG. 62, 122 and 123 are electrically insulated from each other and are electrically active regions formed in the semiconductor substrate, 124 and 125 are gate electrodes made of polysilicon or the like, and 126 to 130 are electrically connected. An impurity diffusion layer formed in an active region, or a contact hole provided through an insulating film to electrically connect a gate electrode to an upper metal wiring, and 131 to 134 are made of aluminum or the like. Are shown. In FIG. 63, reference numeral 50 denotes a thick insulating film formed by oxidizing the substrate to electrically insulate between electrically active regions in the semiconductor substrate;
39 and 140 are polysilicon forming a gate electrode, 135
To 138 are impurity diffusion layers formed in the substrate in a self-aligned manner using the insulating film or the gate electrode as a mask;
Reference numeral 141 denotes an impurity diffusion layer or a thick insulating film formed to electrically insulate the gate electrode and the upper metal wiring. In the structure shown in the figure, a terminal (node N60) to be clamped is
A ground terminal (VSS) is applied to 33 and 134, and a bias voltage Vn is applied to the wiring 133, respectively. In FIG. 63, there are three NPN parasitic bipolar transistors Q1a, Q1b and Q1c based on a P substrate. Q1 in FIG. 61 shows these as representatives. Next, the operation of this element will be described. When the voltage applied to the node N60 exceeds the reverse breakdown voltage of the PN junction formed between the impurity diffusion layer 136 and the substrate, the current due to the breakdown of the junction increases the potential of the P substrate, and the parasitic bipolar transistor Turn on the transistor. As a result, a large collector current flows between the impurity diffusion layers 136 and 135 or 138, thereby drawing out the electric charge of the node N60 and clamping the potential. Of these, Q1b and Q1c are connected in series, so that the collector current is smaller than Q1a. Therefore, the breakdown occurs effectively first, and the MOS-FET turns on the parasitic bipolar transistor, and then the parasitic bipolar transistor Q1a turns on a large collector current. As described above, by disposing an impurity diffusion layer different from the impurity diffusion layer of the transistor near the node N60 and grounding it, the effective distance between the collector and the emitter of the parasitic bipolar transistor is reduced, and the parasitic bipolar transistor is reduced. A large collector current when the transistor operates can be obtained. Thus, the configuration in which the grounded impurity diffusion layer is disposed near the terminal to be clamped can be applied not only to the input protection element but also to the output protection element. In this example, the gate clamp element is formed in the P substrate. However, the gate clamp element may be formed in a P well having a structure as shown in FIG. 27 and electrically separated from the substrate. By doing so, the resistance values of the base and the P well are increased, the parasitic bipolar transistor is easily turned on, and the clamping effect can be further enhanced. The value of the bias voltage VBP1 of the P-substrate or the P-well is usually set to a negative value (for example, -3 V). However, if a forward current is allowed to flow with respect to the input undershoot, It may be 0V. In this embodiment, an example using a P substrate has been described. However, the present invention can be similarly applied to an N substrate provided that the element is formed in a P well.

Although the present invention has been described in detail with reference to the embodiments, the scope of the present invention is not limited to these embodiments. For example, here, the memory circuit is mainly described, but as described earlier in this specification, the memory LS
I, logic LSI, or composite LS combining them
It is applicable to I or all other LSIs. In addition, the type of element used is also p-type and n-type M
LSI using OS transistor, LSI using bipolar transistor, LS using junction FET
I, a BiCMOS type LSI in which a CMOS transistor and a bipolar transistor are combined, and a material other than silicon, for example, an LSI in which elements are formed on a substrate of gallium arsenide or the like can be applied as they are.

[0106]

According to the present invention as described above, the device operates at low power consumption and at high speed by utilizing the characteristics of the device by the most advanced microfabrication technology, and operates in a battery and retains information by switching operation states. A highly integrated LSI that can operate can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram of an embodiment illustrating a basic concept of the present invention.

FIG. 2 is a diagram of an embodiment illustrating a basic concept of the present invention.

FIG. 3 is a diagram of an embodiment illustrating a basic concept of the present invention.

FIG. 4 is a diagram of an embodiment illustrating a basic concept of the present invention.

FIG. 5 is a diagram of an embodiment explaining the basic concept of the present invention.

FIG. 6 is a diagram of an embodiment illustrating a basic concept of the present invention.

FIG. 7 is a diagram of an embodiment explaining the basic concept of the present invention.

FIG. 8 is a diagram of an embodiment in which the present invention is applied to a static memory.

FIG. 9 is a diagram of an embodiment in which the present invention is applied to a static memory.

FIG. 10 is a diagram of an embodiment in which the present invention is applied to a static memory.

FIG. 11 is a diagram of an embodiment in which the present invention is applied to a dynamic memory.

FIG. 12 is a diagram of an embodiment in which the present invention is applied to a dynamic memory.

FIG. 13 is a diagram of an embodiment in which the present invention is applied to a dynamic memory.

FIG. 14 is a diagram of an embodiment in which the present invention is applied to a dynamic memory.

FIG. 15 is a diagram of an embodiment in which the present invention is applied to a dynamic memory.

FIG. 16 is a diagram of an embodiment in which the present invention is applied to a dynamic memory.

FIG. 17 is a diagram of an embodiment in which the present invention is applied to a dynamic memory.

FIG. 18 is a diagram of an embodiment in which the present invention is applied to a dynamic memory.

FIG. 19 is a view of another embodiment illustrating the basic concept of the present invention.

FIG. 20 is a view of another embodiment illustrating the basic concept of the present invention.

FIG. 21 is a view of another embodiment illustrating the basic concept of the present invention.

FIG. 22 is a view of another embodiment illustrating the basic concept of the present invention.

FIG. 23 is a view of another embodiment illustrating the basic concept of the present invention.

FIG. 24 is a view of another embodiment illustrating the basic concept of the present invention.

FIG. 25 is a view of a specific example of an element constituting the present invention.

FIG. 26 is a view of a specific example of an element constituting the present invention.

FIG. 27 is a view of a specific example of a semiconductor substrate constituting the present invention.

FIG. 28 is a diagram of a specific example for reducing power consumption when information is held.

FIG. 29 is a diagram of a specific example for reducing power consumption when information is held.

FIG. 30 is a diagram of a specific example for reducing power consumption when information is held.

FIG. 31 is a diagram of a specific example of a dynamic memory operating at a low voltage.

FIG. 32 is a diagram of a specific example of a dynamic memory operating at a low voltage.

FIG. 33 is a diagram of a specific example of a dynamic memory operating at a low voltage.

FIG. 34 is a diagram of a specific example of a dynamic memory operating at a low voltage.

FIG. 35 is a diagram of a specific example of a dynamic memory operating at a low voltage.

FIG. 36 is a diagram of a specific example of a dynamic memory operating at a low voltage.

FIG. 37 is a view of a specific embodiment of various circuits operated at a voltage higher than the gate breakdown voltage of a fine element.

FIG. 38 is a view of a specific embodiment of various circuits operated at a voltage higher than the gate breakdown voltage of a fine element.

FIG. 39 is a view of a specific example of various circuits operated at a voltage higher than the gate breakdown voltage of a fine element.

FIG. 40 is a view of a specific embodiment of various circuits operated at a voltage higher than the gate breakdown voltage of a fine element.

FIG. 41 is a view of a specific embodiment of various circuits operated at a voltage higher than the gate breakdown voltage of a fine element.

FIG. 42 is a view of a specific embodiment of various circuits operated at a voltage higher than the gate withstand voltage of a fine element.

FIG. 43 is a view of a specific embodiment of various circuits operated at a voltage higher than the gate breakdown voltage of a fine element.

FIG. 44 is a view of a specific embodiment of various circuits operated at a voltage higher than the gate breakdown voltage of a fine element.

FIG. 45 is a view of a specific embodiment of various circuits operated at a voltage higher than the gate breakdown voltage of a fine element.

FIG. 46 is a view of a specific embodiment of various circuits operated at a voltage higher than the gate breakdown voltage of a fine element.

FIG. 47 is a view of a specific embodiment of various circuits operated at a voltage higher than the gate breakdown voltage of a fine element.

FIG. 48 is a view of a specific embodiment of various circuits operated at a voltage higher than the gate breakdown voltage of a fine element.

FIG. 49 is a diagram of an embodiment showing a basic concept of a configuration of an input / output circuit;

FIG. 50 is a view of a specific example of an output circuit.

FIG. 51 is a diagram of a specific example of an output circuit.

FIG. 52 is a view of a specific example of an output circuit.

FIG. 53 is a view of a specific example of an output circuit.

FIG. 54 is a diagram of a specific embodiment of an input circuit.

FIG. 55 is a view of a specific example of an input circuit.

FIG. 56 is a view of a specific example of an input circuit.

FIG. 57 is a diagram of a specific embodiment of an input circuit.

FIG. 58 is a view of a specific example of an input circuit.

FIG. 59 is a diagram of a specific embodiment of the input circuit.

FIG. 60 is a diagram of a specific embodiment of the input circuit.

FIG. 61 is a view of a specific example of an input protection element.

FIG. 62 is a view of a specific example of an input protection element.

FIG. 63 is a view of a specific example of an input protection element.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... LSI chip, 5 ... Internal circuit part, 6 ... Voltage conversion circuit, 7 ... Input / output circuit, 8 ... Information holding state detection circuit, 9 ...
Reference voltage generation circuit, 10: limiter enable signal generation circuit, 11: external input / output bus, 12: internal input / output bus.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/407 G11C 11/408 G11C 11/417 H03K 19/0948

Claims (34)

(57) [Claims] A first potential defined by a difference between the first potential and the second potential;
A first circuit block that operates with a voltage and includes a plurality of circuits; a voltage that generates a first bias potential determined based on the first potential and a second bias potential determined based on the second potential A first MISFET of a first conductivity type, a second MISFET of the first conductivity type, wherein a source / drain path is connected in series between the first voltages.
A third MISFET of the second conductivity type; and a fourth MISFET of the second conductivity type, wherein the gate of the second MISFET is supplied with the first bias potential, and the gate of the third MISFET is the second bias. A potential is supplied, and the gate of the first MISFET has an amplitude smaller than the first voltage , and the center of amplitude shifts to the first potential side.
And the fourth MISFE
The gate of T has an amplitude smaller than the first voltage.
A second signal whose width center is shifted to the second potential side is input, and when the first signal is at a high level, the second signal is also high.
When the first signal is at a low level.
2. The semiconductor device according to claim 1, wherein the second signal is also at a low level . 2. The semiconductor device according to claim 1, wherein each of the plurality of circuits includes the first and second MISs.
A first coupling node coupling the FETs;
A second coupling node coupling a MISFET; and a third coupling node coupling the second and third MISFETs, wherein the first coupling node comprises a difference between the first potential and the first bias potential. A first output signal having an amplitude smaller than a voltage can be output; and the second coupling node can output a second output signal having an amplitude smaller than a difference voltage between the second potential and the second bias potential. Wherein the third coupling node is capable of outputting a third output signal having a larger amplitude than each of the first and second output signals. 3. The semiconductor device according to claim 2, wherein the amplitude of said third output signal is substantially equal to said first voltage. 4. The inverter circuit according to claim 1, wherein one of the plurality of circuits of the first circuit block is an inverter circuit including the first to fourth MISFETs, and connects the first and second MISFETs of the inverter circuit. First and second MIS nodes, and the third and fourth MISs
A signal having an amplitude smaller than the first voltage can be output from a second coupling node that couples FETs, and is input to the inverter circuit from a third coupling node that couples the second and third MISFETs of the inverter circuit. A semiconductor device capable of outputting a signal having a larger amplitude than the first and second signals. 5. The circuit according to claim 1, wherein one of the plurality of circuits of the first circuit block receives a third signal having an amplitude smaller than the first voltage, and receives the third signal.
An output circuit for outputting a fourth signal having a larger amplitude than the signal, the output circuit comprising: a level conversion circuit receiving the third signal; and a first inverter circuit receiving a pair of signals output from the level conversion circuit. And a second inverter circuit that receives the pair of signals output by the first inverter circuit and outputs the fourth signal, wherein each of the level conversion circuit, the first inverter circuit, and the second inverter circuit Are the first to fourth
A semiconductor device comprising a MISFET. 6. The semiconductor device according to claim 5, wherein the amplitude of said fourth signal is substantially equal to said first voltage. 7. The circuit according to claim 1, wherein one of the plurality of circuits in the first circuit block is a NAND circuit including the first to fourth MISFETs, and the NAND circuit includes Source of 1MISFET
A fifth MISFET of the first conductivity type, the source / drain path of which is connected in parallel to a drain path;
A sixth MISFET of the second conductivity type having a source / drain path inserted between a potential and one end of a source / drain path of the fourth MISFET; and a gate of the first and fourth MISFETs of the NAND circuit. Is a first input node of the NAND circuit. The first signal is input to the gate of the first MISFET, and the second signal is input to the gate of the fourth MISFET. The gates of the fifth and sixth MISFETs are the second input nodes of the NAND circuit. The fifth signal having an amplitude smaller than the first voltage is input to the gate of the fifth MISFET.
A sixth signal having an amplitude smaller than the first voltage is input to a gate of the ISFET, a first coupling node coupling the first and second MISFETs of the NAND circuit, and the third and fourth MISFs
A signal having an amplitude smaller than the first voltage can be output from a second coupling node that couples ET, and is input to the NAND circuit from a third coupling node that couples the second and third MISFETs of the NAND circuit. A semiconductor device capable of outputting a signal having a larger amplitude than the first, second, fifth, and sixth signals. 8. The device according to claim 1, wherein one of the plurality of circuits in the first circuit block is a tri-state output buffer, and the tri-state output buffer includes a NAND circuit;
A semiconductor device including a NOR circuit and an output circuit, wherein the NAND circuit, the NOR circuit, and the output circuit each include the first to fourth MISFETs. 9. The NAND circuit according to claim 8, wherein a signal having an amplitude smaller than the first voltage is input to gates of the first and fourth MISFETs included in the NAND circuit and the NOR circuit. Outputs of the NOR circuit are respectively coupled to first and fourth MISFETs of the output circuit, and a signal having an amplitude substantially equal to the first voltage can be output from a coupling node coupling the second and third MISFETs of the output circuit. A semiconductor device characterized by being performed. 10. The semiconductor device according to claim 1, wherein the semiconductor device is formed on one semiconductor chip, one of the plurality of circuits of the first circuit block includes the first to fourth MISFETs, An input circuit for receiving a signal from outside the semiconductor chip, wherein the input circuit has one end of a source / drain path coupled to a gate of the first MISFET;
A fifth MISFET of the first conductivity type, the gate of which is coupled to the gate of the SFET; one end of a source / drain path of which is coupled to the gate of the fourth MISFET, and the gate of which is coupled to the gate of the third MISFET; Sixth MIS of second conductivity type
And a signal from the outside of the semiconductor chip is coupled to the other end of the source / drain path of the fifth and sixth MISFETs. A coupling node of the first and second MISFETs of the input circuit is A seventh signal having an amplitude smaller than a difference voltage between the first potential and the first bias potential can be output, and a coupling node of the third and fourth MISFETs of the input circuit is connected to the second potential and the second MISFET. A semiconductor device capable of outputting an eighth signal having an amplitude smaller than a difference voltage between the bias signal and a bias potential. 11. The signal processing circuit according to claim 10, wherein an amplitude of a signal input to said input circuit from outside said semiconductor chip is equal to said first circuit.
A semiconductor device substantially equal to a voltage. 12. The device according to claim 1, wherein the first potential is higher than the second potential, the first bias potential is lower than the first potential, and the second bias potential is the second bias potential. A semiconductor device characterized by being higher than a potential. 13. The method of Claim 12, wherein the second with the first potential changes at the first change rate
Potential changes in the second change rate Then, the said first potential first
When a change in the first voltage, which is a voltage difference between two potentials, occurs and the first voltage is within a predetermined first voltage range, the first bias potential changes by a third change with respect to the change in the first voltage. The semiconductor device according to claim 1, wherein the second bias potential changes at a fourth rate, and the third bias rate changes at a fourth rate. 14. A method according to claim 13, wherein said first rate of change is greater than said second rate of change, said third rate of change is proportional to said first rate of change, and said fourth rate of change is equal to said fourth rate of change. 2. A semiconductor device characterized by being proportional to the rate of change. 15. The semiconductor device according to claim 13, wherein said third rate of change is substantially equal to said first rate of change, and said fourth rate of change is substantially equal to said second rate of change. . 16. The device according to claim 12, wherein when the first voltage is within a predetermined first voltage range, the first bias potential is a potential obtained by subtracting a predetermined voltage from the first potential, and 2. The semiconductor device according to claim 1, wherein the second bias potential is a potential obtained by adding a predetermined voltage to the second potential. 17. The semiconductor device according to claim 13, wherein said first voltage range is included in a voltage range in which said semiconductor device operates normally. 18. The method according to claim 13, wherein when the first voltage is in a second voltage range in which a voltage is higher than the first voltage range, a change in the first voltage is obtained.
The first bias potential changes at a fifth rate of change, the second bias potential changes at a sixth rate of change, the fifth rate of change is less than the third rate of change, and the sixth rate of change is A semiconductor device characterized by being larger than the fourth rate of change. 19. The method according to claim 18, wherein
The semiconductor device according to claim 1, wherein both of the change rates are half of the first change rate. 20. The semiconductor device according to claim 18, wherein said second voltage range is a voltage range in which said semiconductor device is subjected to an aging test. 21. The method according to claim 1, wherein the first signal is a signal having a high level and a low level between the first potential and the first bias potential, and the second signal is a signal having a low level. A semiconductor signal having a high level and a low level between a second potential and the second bias potential, wherein the first conductivity type is a P type and the second conductivity type is an N type. . 22. The method according to claim 1, wherein
The semiconductor device according to claim 1, wherein a channel conductance of the second MISFET is larger than a channel conductance of the first MISFET, and a channel conductance of the third MISFET is larger than a channel conductance of the fourth MISFET. 23. The method according to claim 1, wherein
The semiconductor device further includes a second circuit block that operates at a second voltage lower than the first voltage, wherein a thickness of a gate insulating film of a MISFET included in the first circuit block and a second circuit block are provided. A semiconductor device, wherein the thickness of the gate insulating film of the included MISFET is substantially equal. 24. The method according to claim 1, wherein
The semiconductor device further includes a second circuit block that operates at a second voltage lower than the first voltage, and the gate insulating films of the MISFETs included in the first and second circuit blocks are formed by the same manufacturing process. A semiconductor device, comprising: 25. A semiconductor device comprising: a first circuit block operated by a first voltage; and a second circuit block operated by a second voltage smaller than the first voltage, wherein the first circuit block is provided. Has an output circuit that receives a second signal output from the second circuit block and outputs a first signal having an amplitude larger than the second signal, and the output circuit receives the second signal. A level conversion circuit, a first inverter receiving an output of the level conversion circuit, and a second inverter receiving an output of the first inverter and outputting the first signal; A first MISFET having a source / drain path connected in series during one voltage,
MISFET, third MISFET, and fourth MISFE
A fifth MISFET, a sixth MISFET, a source / drain path connected in series between T and the first voltage;
A drain and a gate of each of the first and fifth MISFETs are cross-coupled, and a gate of each of the fourth and eighth MISFETs has an in-phase signal and an inverted signal of the second signal. The first inverter comprises a ninth MISFET having a source-drain path connected in series between the first voltage,
0MISFET, 11th MISFET, and 12th MISFET
And a gate of the ninth MISFET is connected to the fifth and sixth MIFETs.
Coupled to the coupling node of the SFET and the first
The gate of the second MISFET is the seventh and eighth MISFE.
A second MISFET, a fourteenth MISFET, a fifteenth MISFET, and a sixteenth MISFET having a source-drain path connected in series between the first voltage.
And a gate of the thirteenth MISFET is the ninth and tenth MISFETs.
Coupled to the coupling node of the MISFET, and the gate of the sixteenth MISFET is connected to the eleventh and twelfth
A semiconductor device coupled to a coupling node of an ISFET, wherein the first signal is output from a coupling node of the fourteenth and fifteenth MISFETs. 26. The voltage generating circuit according to claim 25, wherein the first voltage is defined by a difference between a first potential and a second potential, and wherein the semiconductor device generates a first bias potential and a second bias potential. The first bias potential is supplied to the gates of the second, sixth, tenth, and fourteenth MISFETs, and the second bias is supplied to the gates of the third, seventh, eleventh, and fifteenth MISFETs. A semiconductor device to which a bias potential is supplied. 27. The semiconductor device according to claim 26, wherein the first potential is higher than the second potential, the first bias potential is lower than the first potential, and the second bias potential is higher than the second potential. Characteristic semiconductor device. 28. An apparatus according to claim 27, wherein when said first voltage is within a first voltage range, said first bias potential is a potential obtained by subtracting a predetermined voltage from said first potential, and said second bias potential is a potential obtained by subtracting a predetermined voltage from said first potential. The semiconductor device is characterized in that the potential is a potential obtained by adding a predetermined voltage to the second potential. 29. The semiconductor device according to claim 28, wherein said first voltage range is included in a voltage range in which said semiconductor device operates normally. 30. The method according to claim 25, wherein the first, second, fifth, sixth, ninth, tenth, thirteenth,
And the fourteenth MISFET are P-type MISFETs, and the third, fourth, seventh, eighth, eleventh, twelfth, and first
The fifth and sixteenth MISFETs are N-type MISFETs. 31. The semiconductor device according to claim 25, wherein the thickness of the gate insulating film of the MISFET included in the first circuit block and the thickness of the gate insulating film of the MISFET included in the second circuit block are substantially equal. A semiconductor device characterized by being equal. 32. The MISF according to claim 25, wherein said MISF is included in said first and second circuit blocks.
A semiconductor device, wherein the gate insulating film of ET is formed in the same manufacturing process. 33. In any one of claims 1 to 32,
The semiconductor device is a microprocessor LSI. 34. In any one of claims 1 to 32,
The semiconductor device is a dynamic memory.