JP3327791B2 - Printing head and printing apparatus using the printing head - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording head and a recording apparatus using the recording head, and more particularly, to a recording head which discharges ink in accordance with an ink jet system to perform recording on a recording medium and a recording apparatus used for the recording head. .

[0002]

2. Description of the Related Art A recording head mounted on a conventional recording apparatus according to the ink jet system has a circuit configuration as shown in FIG. The electrothermal transducer (heater) of such a recording head and its driving circuit are described in, for example,
As shown in Japanese Patent No. 5594, they are formed on the same substrate by using a semiconductor process technique.

In FIG. 6, reference numeral 401 denotes an electrothermal transducer (heater) for generating thermal energy, 402 a power transistor for supplying a desired current to the heater 401, and 404 a current to each heater 401. A shift register 406 for temporarily storing image data indicating whether or not to eject ink from the nozzles of the print head;
407 is an input terminal for inputting a transfer clock (CLK) provided in the shift register 404, and 403 is image data (DATA) for each heater 401. ) Is a latch signal input terminal for inputting a latch timing signal (LT) to the latch circuit 403.
Reference numeral 9 denotes a switch for determining the timing of supplying a current to the heater 401, reference numeral 405 denotes a power supply line for applying a predetermined voltage to the heater and supplying current, and reference numeral 410 denotes a GND line into which the current flowing through the heater 401 and the power transistor 402 flows. is there.

The number of image data bits stored in the shift register 404, the number of power transistors 402, and the number of heaters 401 are the same.

FIG. 7 is a timing chart of various signals for driving the drive circuit of the recording head shown in FIG.

Next, the operation of the drive circuit of the recording head shown in FIG. 6 will be described with reference to FIG. The transfer clock (CLK) for the number of bits of the image data stored in the shift register 404 is input to the transfer clock input terminal 407. Here, it is assumed that data transfer to the shift register 404 is performed in synchronization with the rising timing of the transfer clock (CLK), and each heater 401 is turned on.
/ OFF image data (DATA) is input from the image data input terminal 406.

Here, the number of bits of image data stored in the shift register 404 is the same as the number of heaters 401 and the number of power transistors 402 for driving current.
After transferring the image data (DATA) to the shift register 404 by inputting the pulses of the transfer clock (CLK) by the number of the heaters 401, the latch signal (LT) is given to the latch signal input terminal 408 to give each heater 401. The corresponding image data is held in the latch circuit 403.

Thereafter, the switch 409 is set to "O" for an appropriate time.
If N "is set, the current flows through the power line 405 to the power transistor 402 and the heater 401 in accordance with the length of time that the switch 409 is in the ON state, and the current flows into the GND line 410 again. The heater 401 generates heat necessary for discharging ink, and ink corresponding to the image data (DATA) is discharged from the nozzles of the recording head.

The configuration described above is conventionally known, and a recording head having a configuration as shown in FIG. 8 has been proposed as an improved type.

In FIG. 8, reference numeral 502 denotes an nMOS field effect transistor (FET) which operates as a power transistor for supplying a desired current to the heater. As described above, when a MOS transistor is used as a power transistor, a voltage converter 511 is provided between the switch 409 and the power transistor 502, as shown in FIG. Is preferably converted to a higher voltage amplitude and applied to the gate of the power transistor 502 to increase the driving force of the power transistor. By thus increasing the driving force of the power transistor, the area occupied by the power transistor in the driving circuit can be reduced, thereby contributing to downsizing of the entire circuit. Also,
In FIG. 8, reference numeral 512 denotes a power supply line for applying a voltage to the voltage conversion unit 511.

When this circuit configuration is compared with that of FIG.
In the configuration shown in FIG. 6, an NPN transistor connected in Darlington is used as a power transistor. Under such a configuration, a logic circuit such as a shift register or a latch usually uses a CMOS gate, and at the same time, forms a NPN transistor.
-A CMOS process was used. However, Bi-
The CMOS process has the disadvantage that the number of masks required for the process is large and expensive. Therefore, FIG.
As shown in the figure, instead of an NPN transistor, an nMOS
By using a transistor, a power transistor can be formed using a process (CMOS process) similar to that of a logic circuit, so that a recording head can be manufactured at relatively low cost.

[0012]

However, in a recording head using a MOS transistor as a power transistor as shown in the above-mentioned conventional example, there is a problem that the recording head does not perform a desired operation due to a variation in a manufacturing process. . This will be described with reference to the current / voltage characteristic diagram of the nMOS transistor shown in FIG. FIG. 9 shows the static characteristics of the nMOS transistor and the load line due to the resistance of the heater of the recording head.

When a recording head as shown in FIG. 8 is mounted on a recording apparatus and a recording operation is performed and ink is ejected, the nMOS transistor is activated and a current flows to the heater. At this time, the voltage (Vop) applied between the drain and source of the nMOS transistor and the current (Iop) applied between the drain and source of the nMOS transistor are, as shown in FIG. (Operating point). When the voltage applied to the heater is VH, the energy generated by the heater at the time of ink ejection is (VH-Vop) * Iop.

On the other hand, in a recording head according to the ink jet system, it is desirable that the drain-source voltage (Vop) at the time of ink ejection be a small value in order to increase the electric heat exchange efficiency. Therefore, at the operating point of the nMOS transistor, it is desirable to design the nMOS transistor to operate in the triode region. At this time, the drain current (I
DS) and the drain-source voltage (VDS) can be expressed as in equation (1).

IDS = (W / L) · μn · Cox [(VG−VTH) · VDS− (1/2) VDS ² ] (1) where W: gate width, L: gate length, μn: Electron mobility, Cox: gate oxide film thickness, VG: gate voltage, VTH:
The threshold voltage.

It is known that among the factors that change the characteristics of the nMOS transistor, the influence of the process variation of the gate length (L) is the largest. For example,
When manufacturing an nMOS transistor having a gate length (L) of 3 ≦ L, it is common to use a mirror projection aligner (MPA) as an aligner used for the manufacture. A process variation of 1.0 μm may occur.

As is apparent from the equation (1), the gate length (L) is inversely proportional to the drain current (IDS).
Further, since the ratio of dimensional change due to process variation to the design value (L0) is large, the static characteristics of the nMOS transistor are greatly affected. FIG. 9 shows a static characteristic when the gate length (L) is larger than the design value (L0) by a broken line, and a static characteristic when the gate length (L) is smaller than the design value by a dotted line.

According to such a characteristic change, when the gate length (L) becomes larger than the design value (L0) (L> L)
In (0), both the voltage applied to the heater of the nMOS transistor and the current flowing through the heater are reduced, and the energy generated from the heater is reduced. Conversely, when the gate length (L) becomes smaller than the design value (L0) (L <L
0), the driving force of the nMOS transistor improves, the voltage applied to the heater and the current flowing to the heater both increase, and the energy generated from the heater increases.

Therefore, if the energy generated from the heater is smaller than the design value, there is a problem that the ink is not ejected. Conversely, if the energy generated from the heater is larger than the design value, the ink sticks to the heater, There is a problem that the life of the device is shortened. in this way,
The driving force of the nMOS transistor changes due to variations in the manufacturing process of the recording head, and as a result, the recording operation of the recording head and its life are greatly affected.

According to the present invention, there is provided an ink jet recording head employing a MOS transistor in a driving circuit.
It is an object of the present invention to provide a recording head that operates normally even if the characteristics of a MOS transistor change due to variations in the manufacturing process, and a recording apparatus using the recording head.

[0021]

To achieve the above object, a recording head according to the present invention has the following arrangement.

That is, a heater and M for driving the heater
An OS transistor, a logic circuit for holding image data, and voltage conversion for converting a voltage amplitude of a signal based on the image data output from the logic circuit to a higher voltage amplitude and applying the voltage amplitude to a gate electrode of the MOS transistor And a correction circuit electrically connected to a voltage supply path of the voltage conversion unit and correcting a variation in drain current based on a variation in a manufacturing process of the MOS transistor.

Here, the MO in the semiconductor manufacturing process is
The variation in the gate length of the S transistor is included in the variation factor of the drain current. Then, the correction circuit suppresses the variation in the drain current of the MOS transistor by controlling the gate voltage of the MOS transistor so as to compensate for the variation in the drain current due to the variation in the gate length. Specifically, if the gate length is shorter than a design value due to a variation in the semiconductor manufacturing process, the gate voltage is lowered, while if the gate length is longer than the design value, the gate voltage is increased. Control.

Further, the recording head has a first power supply line for applying a first voltage to the heater, a second power supply line for applying a second voltage to the logic circuit, and a first power supply line for applying a second voltage to the logic circuit. And a third power supply line for applying a third voltage, and the correction circuit includes a first resistor which is a polysilicon resistor and a first nMOS transistor connected to the resistor. I have.

Here, one end of the first resistor is connected to the first power supply line, the connection point between the other end of the first resistor and the drain of the first nMOS transistor is connected to the third power supply line, and The configuration may be such that the source of one nMOS transistor is grounded.

Alternatively, a second nMOS transistor and a second nMOS transistor connected between the source of the transistor and ground.
And a source follower circuit including a second resistor connected to a first power supply line, and a connection point between the other end of the first resistor and the drain of the first nMOS transistor. May be connected to the gate of the second nMOS transistor, and the connection point between the source of the second nMOS transistor and the third resistor may be connected to the second power supply line.

The driving circuit may be a circuit formed by a CMOS process or a circuit formed by an nMOS process.

This recording head may be an ink jet recording head that performs recording by discharging ink, or a recording head that discharges ink using thermal energy, and generates thermal energy to be applied to the ink. May be provided with a heat energy converter for the purpose.

According to another aspect of the present invention, there is provided a recording apparatus using the recording head having the above configuration.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

<Schematic Description of Apparatus Main Body> FIG. 1 shows an ink jet printer IJ which is a typical embodiment of the present invention.
It is an external appearance perspective view showing the outline of composition of RA. In FIG. 1, a carriage HC that engages with a spiral groove 5004 of a lead screw 5005 that rotates via driving force transmission gears 5009 to 5011 in conjunction with forward and reverse rotation of a drive motor 5013 has pins (not shown). Guide rail 50
03 reciprocates in the directions of arrows a and b. The carriage HC includes a recording head IJH and an ink tank IT.
Integrated inkjet cartridge IJC
Is installed. Reference numeral 5002 denotes a paper pressing plate, which feeds the recording paper P to the platen 50 over the moving direction of the carriage HC.
Press against 00. Reference numerals 5007 and 5008 denote photocouplers, which are home position detectors for confirming the presence of the carriage lever 5006 in this region and switching the rotation direction of the motor 5013. Reference numeral 5016 denotes a cap member 50 for capping the front surface of the recording head IJH.
Reference numeral 5015 denotes a suction device that suctions the inside of the cap, and performs suction recovery of the recording head through an opening 5023 in the cap. Reference numeral 5017 denotes a cleaning blade. Reference numeral 5019 denotes a member which allows the blade to move in the front-rear direction. These members are supported by a main body support plate 5018. It goes without saying that the blade is not limited to this form and a known cleaning blade can be applied to this example. Reference numeral 5021 denotes a lever for starting suction for recovery of suction. The lever 5021 moves with the movement of the cam 5020 that engages with the carriage, and the driving force from the driving motor is controlled by a known transmission mechanism such as clutch switching. Is done.

The capping, cleaning, and suction recovery are configured so that desired operations can be performed at the corresponding positions by the action of the lead screw 5005 when the carriage comes to the area on the home position side. If a desired operation is performed at the timing, any of the embodiments can be applied.

<Description of Control Structure> Next, a control structure for executing the recording control of the above-described apparatus will be described.

FIG. 2 is a block diagram showing a configuration of a control circuit of the ink jet printer IJRA. In the figure showing a control circuit, 1700 is an interface for inputting a recording signal, 1701 is an MPU, 1702 is an MPU 170
ROM for storing a control program to be executed by PC 1, 170
Reference numeral 3 denotes a DRAM for storing various data (such as the print signal and print data supplied to the print head IJH). Reference numeral 1704 denotes a gate array (GA) for controlling supply of print data to the print head IJH, and includes an interface 1700, an MPU 1701, and a RAM 1703.
It also controls data transfer between them. 1710 is a recording head IJ
A carrier motor for transporting H, and 1709 a transport motor for transporting the recording paper. 1705, a head driver for driving the recording head IJH, 1706, 1707
Are the transport motor 1709 and the carrier motor 171 respectively.
0 is a motor driver for driving 0.

The operation of the above control configuration will be described. When a recording signal enters the interface 1700, the gate array 17
04 and the MPU 1701 converts the recording signal into recording data for printing. Then, the motor driver 17
06 and 1707 are driven, and the head driver 1
Print head IJH according to the print data sent to
Is driven, and recording is performed.

FIG. 3 is a circuit diagram showing a configuration of a drive circuit of the recording head IJH. In FIG. 3, the same elements as those of the recording head shown in FIGS. 6 and 8 of the conventional example are denoted by the same reference numerals, and the description thereof is omitted. Only the elements will be described.

In FIG. 3, reference numeral 111 denotes a voltage converter for converting the voltage amplitude of the digital signal from the switch 409 to a higher voltage amplitude, and supplies the voltage to the gate of the power transistor 502. Reference numeral 116 denotes a power supply line of the voltage converter 111. . The voltage conversion unit 111 includes a resistor 112 and a resistor 1
NMOS transistor 11 having a drain connected to 12
3. It is composed of a pMOS transistor 114 and an nMOS transistor 115 constituting a CMOS inverter.

Reference numeral 117 denotes a correction circuit for applying a desired voltage to the voltage converter 111. Correction circuit 117
Is a polysilicon resistor 118, an nMOS transistor 1
19, an input terminal 120 for determining the ON resistance of the nMOS transistor 119 during operation. The polysilicon resistor 118, the nMOS transistor 119, and the polysilicon gate electrode of the power transistor 502 are formed in the same manufacturing process.

The number of image data bits stored in the shift register 404, the number of power transistors 502, and the number of heaters 401 are the same.

The recording head IJH having the above-described configuration performs the same operation as the conventional recording head shown in FIG. 6 according to the timing chart shown in FIG.

That is, image data (DATA) for turning on / off each heater 401 is synchronized with the rising timing of the transfer clock.
Is entered from Here, since the number of bits of the image data stored in the shift register 404 is the same as the number of the heaters 401 and the power transistors 502 for current driving, the transfer clock (CLK) is equal to the number of the heaters 401.
Is input to transfer the image data (DATA) to the shift register 404, and then the latch signal input terminal 408
, And the latch circuit 403 holds image data corresponding to each heater.

Thereafter, when the switch 409 is turned on, a Low / Hi signal corresponding to the image data is output to the latch circuit 40.
3, and the output voltage is applied to the gate of the nMOS transistor 113 of the voltage conversion unit 111 via the switch 409.

Here, the output of the latch circuit 403 is "Lo"
At this time, the nMOS transistor 113 is turned off, so that the voltage of the power supply 116 is directly supplied to the pMOS transistor 114 via the resistor 112.
And an nMOS transistor 115. Then, since the output of the CMOS inverter becomes “Low”, “0 V” is supplied to the gate of the power transistor 502 as a voltage. That is, when the output of the latch circuit 403 is “Low (no image data or the value of the image signal is“ 0 ”)”,
The gate voltage of the power transistor 502 becomes “0 V”, no current flows through the heater 401, and printing by ink ejection is not performed.

Next, consider the case where the output of the latch circuit 403 is "Hi". Shift register 404 and latch circuit 4
Numeral 03 is usually constituted by a CMOS gate, and receives an external transfer clock (CLK), image signal (DATA),
All signals such as latch timing (LT) are 0V / 5
Since the signal has a signal amplitude of V, the power supply voltage of the latch circuit 403 is often 5 V. Therefore, when the output of the latch circuit 403 is “Hi”, the signal voltage is 5
V. This 5V voltage is applied to the switch n by way of the switch 409.
The voltage is applied to the gate of the MOS transistor 113. As a result, the nMOS transistor 113 is turned on, so that a current flows through the resistor 112.

At this time, if the value of the resistor 112 is set to a value sufficiently higher than the ON resistance of the nMOS transistor 113, the gate of the CMOS inverter is infinitely set to 0V.
Is applied and the output of the CMOS inverter becomes “H”.
Accordingly, the voltage value of the power supply line 116 appears as it is at the output voltage level of the CMOS inverter, and is supplied to the gate of the power transistor 502.

That is, the output of the latch circuit 103 is "Hi".
In the case of, the gate of the power transistor 502
When the voltage of the power supply line 116 is applied, the power transistor 502 is turned on. As a result, a current flows through the heater 401 to heat the ink and eject ink droplets to perform printing. Thus, the power transistor 102
Is applied to the power supply line 116. This voltage is generated by the correction circuit 117.

Now, in the manufacturing process of the recording head, the polysilicon resistor 1 constituting the correction circuit 117 will be described.
18 and the polysilicon electrode of the nMOS transistor 119 are formed at the same time as the polysilicon gate electrode of the nMOS transistor 502 which is a power transistor for supplying a current to the heater 401, and the electrode size is designed as described below. The correction circuit 117 operates as a circuit that suppresses a change in the ink ejection state due to a change in the driving force of the power transistor 502.

That is, when the MPA is used as the aligner as described in the conventional example, the gate length (L) of the nMOS transistor is set to a maximum of ± 0.
A process variation of 5 to ± 1.0 μm occurs. This process variation depends on exposure conditions and etching conditions, and greatly fluctuates between manufacturing lots and wafers. On the other hand, when looking at the variation within the same wafer, the above-described deviation occurs from the design value, but the relative variation within the wafer is relatively small. In other words, if the polysilicon width in a portion between wafers is 1 μm narrower than the design value, it is considered that the polysilicon width in other portions is also reduced by approximately 1 μm.

Here, it is assumed that the design value of the gate length (L) of the polysilicon of the power transistor 502 is 4 μm, which is changed to 3 μm due to process variation.

In this case, as can be seen from equation (1), M
Since the driving force of the OS transistor increases 4/3 times,
The energy generated from the heater 401 becomes larger than the design value, and there arises a problem that ink sticking occurs and the life of the heater is shortened.

At this time, the width of the polysilicon resistor 118 of the correction circuit 117 is 4 μm, and the nMOS transistor 119
Is designed to have a gate length (L) of 4 μm, and the direction of the polysilicon gate of the power transistor 502 and the nMOS transistor 119 and the direction of the polysilicon resistor 118 are manufactured in the same direction. It is considered that these values also change to 3 μm in the same wafer.

Now, the voltage of the power supply line 405 is set to 24V,
A case will be described where the voltage of the power supply line 116 is designed to be 16 V, that is, the ratio of the polysilicon resistor 118 to the ON resistance of the nMOS transistor 119 is 1: 2.

The width of the polysilicon resistor 118 ranges from 4 μm to 3 in the same manner as the gate length (L) of the power transistor 502.
Therefore, the resistance of the polysilicon resistor 118 increases 1.33 times. On the other hand, nM of the correction circuit 117
Since the gate length (L) of the OS transistor 119 changes from 4 μm to 3 μm, the ON resistance of the nMOS transistor decreases 0.75 times. As a result, the correction circuit 117
And the voltage supplied to the power supply line 116 changes from the designed value of 16 V to about 12.5 V.

This voltage is applied to the gate electrode of the power transistor 502 as described above. Since the relationship shown in equation (1) exists between the gate voltage (VG) and the drain current (IDS), when the gate voltage (VG) changes from 16 V to 12.5 V, the drain current (IDS) Becomes about 0.75 times. Therefore, when the gate length of the power transistor 502 changes, M
Although the driving force of the OS transistor increases about 1.33 times, the change in the driving force of the MOS transistor due to a change in the gate voltage (VG) is about 0.75 times. Therefore, it can be seen that the change in the driving force of the MOS transistor is about 0.998 times as a whole, and hardly changes.

As described above, when the gate length of the power transistor 502 is smaller than the design value, the power transistor 502 acts to improve the driving force of the MOS transistor.
The operation described above reduces the voltage applied to the gate electrode of the transistor, and acts to suppress the driving force of the MOS transistor. Conversely, the power transistor 502
When the gate length of the MOS transistor becomes larger than the design value, it acts to reduce the driving force of the MOS transistor, but since the voltage applied to the gate electrode of the transistor increases,
A decrease in the driving force of the MOS transistor is suppressed.

According to the present embodiment as described above,
Even if the driving force of the MOS transistor fluctuates due to the variation in the manufacturing process, the correction circuit 117 operates to compensate for the fluctuation and controls the driving force of the MOS transistor. Can be minimized. As a result, fluctuations in ink ejection due to variations in the characteristics of the power transistors constituting the circuit of the recording head are suppressed, a more stable ink ejection operation is realized, and higher-quality image recording can be performed.

Further, since a high load is not applied to the heater, it contributes to extending the life of the recording head.

In the above example, the gate length of the power transistor 502, the width of the polysilicon resistor 118,
The case where the design value of the gate length of the nMOS transistor 119 is the same has been described. In the actual manufacturing process of the recording head, the correction of the driving force of the MOS transistor in such a design is best performed, but the present invention is not limited to this, and these values are not necessarily the same design values. Needless to say, it is not necessary.

In the above example, the level shift circuit 1
Although the description has been given of the case where the transistor 17 is constituted by a polysilicon resistor and a MOS transistor, the present invention is not limited to this. Using either one element, for example, a correction circuit is constituted by a combination of a polysilicon resistor having substantially the same width as the gate length of the power transistor and a sufficiently thick polysilicon resistor which does not affect process variations. Is also good.

Further, in the above example, the voltage converter 111
Has a circuit configuration formed by a CMOS process, but the present invention is not limited to this.
For example, as shown in FIG.
You may make it comprise only an S transistor. FIG.
, 312 is a resistor, and 313 to 315 are nMOS transistors.

As described above, the voltage conversion section 111
If a logic circuit such as a shift register or a latch is formed only of nMOS transistors, it is possible to manufacture a circuit of a recording head by an nMOS process, and the power consumption is larger than that of a CMOS circuit. However, there is an advantage that the manufacturing cost is reduced.

[0062]

[Other Embodiments] In the above-described embodiment, when ink is ejected, the nMOS transistor 113 is turned on, and a current flows from the power supply line 116 to GND. At this time, the resistance value of the resistor 118 and the ON resistance value of the nMOS transistor 119 must be sufficiently smaller than the resistance value of the resistor 112 in order to prevent the voltage change of the power supply line 116 from increasing. This way,
A large through current is generated from the power supply line 405 to GND through the resistor 118 and the MOS transistor 119, and power is consumed here.

In this embodiment, in order to reduce such power consumption, the level shift circuit 117 and the power supply line 11
6, a buffer 201 is provided, and the circuit of the recording head is configured as shown in FIG. In FIG. 5, 201 is a source follower buffer for converting input / output impedance, 202 is an nMOS transistor, and 203 is a resistor. As can be seen from the circuit configuration shown in FIG. 5, the basic operation of the circuits other than the source follower buffer 201 is as follows.
This is the same as the circuit shown in FIG.

With such a circuit configuration, the heater 401
, The drain current of the nMOS transistor 202 only needs to flow through the power supply line 116. on the other hand,
This current is controlled by the gate voltage of the nMOS transistor 202. Therefore, only the voltage output from the correction circuit 117 and applied to the gate of the nMOS transistor 202 becomes important, and the current supply capability of the correction circuit 117 may be small. Therefore, the resistance value of the resistor 118 and M
The value of the ON resistance of the OS transistor 119 can be increased. Therefore, the power supply line 405
Therefore, the current flowing through the resistor 118 and the MOS transistor 119 becomes small, and power consumption can be suppressed.

In this embodiment, when the output of the correction circuit 117 is input to the buffer 201 and the corresponding buffer output is output as the drain-source current of the nMOS transistor 202, the voltage is increased by the threshold voltage (VTH) of the nMOS transistor 202. Although a descent occurs, the basic operation is the same as in the above-described embodiment.

Therefore, according to this embodiment, unnecessary power consumption is reduced, and power consumption can be further reduced.

The above-described embodiment is particularly provided with a means (for example, an electrothermal converter or a laser beam) for generating thermal energy as energy used for performing ink ejection even in an ink jet recording system. By using a method in which a change in the state of the ink is caused by energy, it is possible to achieve higher density and higher definition of recording.

The typical structure and principle are described in, for example, US Pat. Nos. 4,723,129 and 4,740.
It is preferable to use the basic principle disclosed in the specification of Japanese Patent No. 796. This method can be applied to both the so-called on-demand type and continuous type. In particular, in the case of the on-demand type, liquid (ink)
By applying at least one drive signal corresponding to the recorded information and providing a rapid temperature rise exceeding the film boiling to the electrothermal transducer arranged corresponding to the sheet or the liquid path holding the Since thermal energy is generated in the electrothermal transducer and film boiling occurs on the heat-acting surface of the recording head, bubbles in the liquid (ink) corresponding to this drive signal on a one-to-one basis can be formed. It is valid. By discharging the liquid (ink) through the discharge opening by the growth and contraction of the bubble, at least one droplet is formed. When the drive signal is formed into a pulse shape, the growth and shrinkage of the bubble are performed immediately and appropriately, so that the ejection of liquid (ink) having particularly excellent responsiveness can be achieved, which is more preferable.

As the pulse-shaped drive signal, those described in US Pat. Nos. 4,463,359 and 4,345,262 are suitable. Further, if the conditions described in US Pat. No. 4,313,124 relating to the temperature rise rate of the heat acting surface are adopted, more excellent recording can be performed.

As the configuration of the recording head, in addition to the combination of a discharge port, a liquid path, and an electrothermal converter (a linear liquid flow path or a right-angle liquid flow path) as disclosed in the above-mentioned respective specifications, A configuration using U.S. Pat. No. 4,558,333 or U.S. Pat. No. 4,459,600, which discloses a configuration in which a heat acting surface is arranged in a bent region, is also included in the present invention. In addition, for multiple electrothermal transducers,
JP-A-59-123670 which discloses a configuration in which a common slot is used as a discharge part of an electrothermal transducer, and JP-A-59-123670 which discloses a configuration in which an opening for absorbing a pressure wave of thermal energy corresponds to a discharge part. A configuration based on 138461 may be adopted.

Further, as a full line type recording head having a length corresponding to the width of the maximum recording medium that can be recorded by the recording apparatus, the length is determined by a combination of a plurality of recording heads as disclosed in the above specification. This may be either a configuration satisfying the above requirements or a configuration as a single recording head formed integrally.

In addition to the cartridge type recording head in which the ink tank is provided integrally with the recording head itself described in the above embodiment, the recording head is electrically connected to the apparatus main body by being mounted on the apparatus main body. A replaceable chip-type recording head, which enables a simple connection and supply of ink from the apparatus main body, may be used.

It is preferable to add recovery means for the printhead, preliminary auxiliary means, and the like to the configuration of the printing apparatus described above, since the printing operation can be further stabilized. Specific examples thereof include capping means for the recording head, cleaning means, pressurizing or suction means, preheating means using an electrothermal transducer or another heating element or a combination thereof. It is also effective to provide a preliminary ejection mode for performing ejection that is different from printing, in order to perform stable printing.

Further, the recording mode of the recording apparatus is not limited to the recording mode of only the mainstream color such as black, but may be a single recording head or a combination of plural recording heads. Alternatively, the apparatus may be provided with at least one of full colors by color mixture.

In the embodiments described above, the description is made on the assumption that the ink is a liquid. However, even if the ink solidifies at room temperature or lower, it is possible to use an ink that softens or liquefies at room temperature. Or, in the ink jet method, generally, the temperature of the ink itself is controlled within a range of 30 ° C. or more and 70 ° C. or less to control the temperature so that the viscosity of the ink is in a stable ejection range.
It is sufficient that the ink is in a liquid state when the use recording signal is applied.

In addition, in order to positively prevent temperature rise due to thermal energy as energy for changing the state of the ink from a solid state to a liquid state, the temperature is positively prevented.
Alternatively, in order to prevent evaporation of the ink, an ink which solidifies in a standing state and liquefies by heating may be used. In any case, the application of heat energy causes the ink to be liquefied by application of the heat energy according to the recording signal and the liquid ink to be ejected, or to start to solidify when reaching the recording medium. The present invention is also applicable to a case where an ink having a property of liquefying for the first time is used. In such a case, as described in JP-A-54-56847 or JP-A-60-71260, the ink is held in a liquid state or a solid state in the concave portion or through hole of the porous sheet. It is good also as a form which opposes an electrothermal transducer. In the present invention, the most effective one for each of the above-mentioned inks is to execute the above-mentioned film boiling method.

In addition, as a form of the recording apparatus according to the present invention, in addition to an image output terminal of an information processing apparatus such as a computer which is provided integrally or separately, a copying apparatus combined with a reader or the like, It may take the form of a facsimile machine having functions.

Even if the present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus (for example, a copying machine, a facsimile, etc.) comprising one device Device).

[0079]

As described above, according to the present invention, even if the characteristics of a MOS transistor for driving a heater fluctuate due to, for example, a semiconductor manufacturing process, a variation in the characteristics is corrected by a correction circuit. There is an effect that the device operates stably and thereby can perform high-quality image recording.

[0080]

[Brief description of the drawings]

FIG. 1 is an external perspective view showing an outline of a configuration of an ink jet printer IJRA which is a typical embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a control circuit of the inkjet printer IJRA.

FIG. 3 is a circuit diagram showing a configuration of a drive circuit of a printhead IJH.

FIG. 4 is a circuit diagram in the case where the circuit shown in FIG. 3 is configured by an nMOS process.

FIG. 5 is a circuit diagram showing a configuration of a drive circuit of a print head IJH according to another embodiment.

FIG. 6 is a diagram showing a circuit configuration of a conventional recording head according to an ink jet system.

FIG. 7 is a timing chart of various signals for driving the printhead drive circuit shown in FIG. 6;

8 is a block diagram showing a conventional example using an nMOSFET as a power transistor of the recording head shown in FIG.

FIG. 9 is a diagram showing VDS-IDS characteristics of an nMOS transistor.

[Explanation of symbols]

 111, 311, 511 Voltage conversion unit 117 Correction circuit 201 Source follower buffer 401 Heater 402 NPN transistor 403 Latch circuit 404 Shift register 502 nMOS transistor

Claims (14)

(57) [Claims] 1. A heater, a MOS transistor for driving the heater, a logic circuit for holding image data, and a higher voltage amplitude of a signal based on the image data output from the logic circuit. Converted to voltage amplitude
A voltage conversion unit for applying a voltage to the gate electrode of the OS transistor; and a voltage conversion unit electrically connected to a voltage supply path of the voltage conversion unit, based on a manufacturing process variation of the MOS transistor.
A correction circuit for correcting variations in rain current . 2. A variation of the gate length of the MOS transistor in the semiconductor of the manufacturing process, the drain
The recording head according to claim 1, wherein the recording head is included in a current variation factor. 3. The correction circuit according to claim 2, wherein said correction circuit compensates for variation in drain current due to variation in gate length.
The recording head according to claim 2, wherein a variation in drain current of the MOS transistor is suppressed by controlling a gate voltage of the S transistor. 4. The correction circuit reduces the gate voltage when the gate length is shorter than a design value due to a variation in a semiconductor manufacturing process. On the other hand, when the gate length is longer than a design value, 4. The recording head according to claim 3, wherein the gate voltage is increased. 5. A first method for applying a first voltage to the heater.
, A second power supply line for applying a second voltage to the logic circuit, and a third power supply line for applying a third voltage to the power conversion unit. The recording head according to claim 1. 6. The recording head according to claim 5, wherein the correction circuit includes a first resistor and a first nMOS transistor connected to the first resistor. 7. The recording head according to claim 6, wherein the first resistor is a polysilicon resistor. 8. One end of the first resistor is connected to the first power supply line, and the other end of the first resistor is connected to the first nM.
7. The recording head according to claim 6, wherein a connection point of the drain of the OS transistor is connected to the third power supply line, and a source of the first nMOS transistor is grounded. 9. A source follower circuit comprising: a second nMOS transistor; and a second resistor connected between a source of the second nMOS transistor and a ground, The drain of the nMOS transistor is connected to the first
The other end of the first resistor and the first
Is connected to the gate of the second nMOS transistor at the gate of the second nMOS transistor.
Recording head according to claim 7 in which the connection point between the second resistor and the source of the OS transistor and said connected Tei Rukoto to the third power supply line. 10. The logic circuit and the voltage converter, wherein a CM
2. The recording head according to claim 1, wherein the recording head is a circuit formed by an OS process. 11. The logic circuit and the voltage converter, wherein nM
2. The recording head according to claim 1, wherein the recording head is a circuit formed by an OS process. 12. The recording head according to claim 1, wherein the recording head is an ink jet recording head that performs recording by discharging ink. 13. The recording head according to claim 1, wherein the recording head ejects ink by using thermal energy, and includes a thermal energy converter for generating thermal energy to be applied to the ink. Item 2. The recording head according to Item 1. 14. A recording apparatus using the recording head according to claim 1.