JP3324595B2 - Planar antenna device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a GPS (Global P
The present invention relates to a planar antenna device that receives a transmission radio wave from a satellite or the like by using a planar antenna element by an ositioning system or the like and generates a reception signal.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram of a conventionally known GPS antenna device. The antenna device 1 includes a planar antenna element 2 having a receiving electrode 3 formed on the front surface of a dielectric substrate and a ground electrode 4 formed on the back surface, a matching circuit 5 connected to the receiving electrode 3 line of the planar antenna element 2, A low-noise amplifier 10 including an amplifier 6, a band-pass filter 7, a high-frequency amplifier 8, and the like. The low-noise amplifier 10 generates a GPS radio wave W received by the antenna element 2 into a received signal Po via the low-noise amplifier 10. is there.

[0003]

FIG. 7 shows the conventional GP.
3 shows waveforms at various parts of the S antenna device 1.

[0004] Here, the power spectrum of the GPS radio wave shown in FIG.
, And its frequency band fw and power. In the case of GPS communication, for example, the reception frequency f
0 is 1575.42 MHz, frequency band fw is 2.04
It is set to 6 MHz or the like.

In the frequency characteristic of the antenna element shown in FIG. 7B, a waveform shown by a broken line is an ideal frequency characteristic when the reception frequency f0 and the resonance frequency f1 of the antenna system coincide with each other. Like the waveform shown by the solid line,
An error Δf between the reception frequency f0 and the resonance frequency f1 is often
Occurs. If the frequency error Δf increases, sufficient characteristics as an antenna device cannot be obtained with respect to the reception frequency, the total gain, and the like.

The output power spectrum of the received signal shown in FIG. 7 (d) shows the output waveform of the final stage circuit of the antenna device 1, and the output power is the ideal power Po0 indicated by a broken line, and Actual power Po1 indicated by solid line
As shown in FIG. 7B, the frequency characteristic greatly depends on the degree of the error in the frequency characteristic of the antenna element. The antenna characteristics include variations in the dielectric constant of the dielectric substrate and the shape of each electrode pattern constituting the antenna element, and other internal factors such as the load form of the matching circuit and the high-frequency amplifier connected thereto, and the like.
This is largely influenced by fluctuations of the overall resonance system including external factors such as a mounting state on a mobile terminal and a use state.

[0007] Also, due to recent market demands, miniaturization due to the use of a high dielectric material has been attracting attention as the antenna element. Variations in the pattern accuracy of each electrode due to this miniaturization are factors that cause the antenna characteristics to vary. Influence as. That is, the relationship between the dimensional accuracy of the electrode and the fluctuation of the resonance frequency (that is, the frequency error Δf) appears remarkably as the base material of the antenna element becomes higher in dielectric constant. In the case of miniaturization, the use of a material having a small dielectric constant tolerance or an improvement in the printing accuracy of an electrode pattern has caused a rise in product cost in terms of material cost and productivity.

Further, in order to eliminate the external influence of the antenna characteristics due to the mounting state, it is necessary to negotiate specifications for each type of mobile terminal and each customer, which requires enormous development power, and reduces the yield due to various model configurations. This has led to a decrease, an increase in inspection costs, an increase in the return rate, and the like, which have been major factors in soaring product costs. Furthermore, there is no means to prevent the influence of human factors when using the terminal in the current product configuration, and a design was made with a margin for the characteristic as a variable factor when developing the mobile terminal.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a planar antenna device which solves the problems of the conventional antenna device by automatically correcting an error between the reception frequency and the resonance frequency caused by the fluctuation of the resonance system due to the above factors. I have.

[0010]

That is, the invention according to claim 1 comprises an antenna element (2) and a low noise amplifier (10), receives a radio wave (W) from an artificial satellite or the like, and receives a received signal (W). Planar antenna device for generating Po) (1)
Wherein one or a plurality of voltages are applied between the receiving electrode (3) of the antenna element (2) and the ground electrode (4).
Capacitor conversion element (D1) directly or capacitor (C5)
And a resonance frequency correction circuit (20).
The voltage (Vz) applied to the voltage-capacitance conversion element (D1) is minutely changed at regular time intervals (t) by the resonance frequency correction circuit (20) and is obtained by the low noise amplifier (10). The received output power (Pw) is measured at regular intervals, and when the change in the received output power (Pw) is in the increasing direction, the applied voltage (Vz) is slightly changed to the same polarity as the previous time. When the change in the output power (Pw) is in the decreasing direction, the resonance frequency (f1) of the antenna element (2) is reduced by sequentially performing control to slightly change the applied voltage (Vz) to the opposite polarity to the previous time. It is characterized by successively shifting to the very vicinity of the reception frequency (f0) of the radio wave (W).

Further, according to a second aspect of the present invention, the resonance frequency correction circuit (20) is configured so that the reception output power (P
w), a power-to-voltage conversion circuit (12) for converting the amplified output of the high-frequency amplifier (11) into a voltage, and switch means ( SW1, SW2) and the capacitors (C1, C2) connected to the switch means (SW1, SW2).
2), the output voltage of the power-voltage conversion circuit (12) is alternately held in the capacitors (C1, C2) by the switching operation of the switching means (SW1, SW2), and the respective holding voltages are held. (Vc1,
Vc2) alternately.
3) and a polarity discriminating circuit (14) that includes an amplifier circuit (IC1) and a comparator circuit (IC2), and sequentially compares the switched output hold voltages to determine the polarity of the voltage change. It is a feature.

According to a third aspect of the present invention, the resonance frequency correction circuit (20) further comprises a latch circuit (IC3) for holding the determined polarity signal (Vd) of the voltage change for a predetermined period. , The voltage increase period (Tu
p) and a flip-flop circuit (IC4) for generating a voltage decreasing period (Tdw), and the voltage increasing period (Tup)
A charging constant current circuit (IS1) for turning on the medium to charge the capacitor (C4); and a discharging constant current circuit (IS2) for turning on and discharging the capacitor (C4) during the voltage reduction period (Tdw). And an applied voltage generation circuit (1
5) is provided.

According to a fourth aspect of the present invention, the resonance frequency correction circuit (20) further comprises a latch circuit (IC3) for holding the determined polarity signal (Vd) of the voltage change for a predetermined period. , The voltage increase period (Tu
p) and a flip-flop circuit (IC4) for generating a voltage decreasing period (Tdw), and the voltage increasing period (Tup)
A charging transistor circuit (Tr1) for charging the capacitor (C4) by turning on in the middle, and the voltage decreasing period (Td)
w) an applied voltage generating circuit (15) including a discharging transistor circuit (Tr2) that turns on during the discharge of the capacitor (C4).

According to the first to fourth aspects of the present invention, the manufacturing error of the antenna element, the physical environment around the antenna element, and the fluctuation of the resonance frequency of the planar antenna device due to the change thereof are sequentially reduced. It is automatically corrected, and the output power at the time of reception can always be maintained at the maximum.

Further, according to the present invention, when the power is turned on, the voltage (V) applied to the voltage-capacitance conversion element (D1) is applied.
z) is initially set to approximately 1/2 of the maximum voltage control width. For example, in the initial state, the applied voltage is set to about 1/2 of the power supply voltage Vcc and the resonance frequency f1 is set as close as possible to the reception frequency f0, so that the resonance frequency correction processing time (resonance time) during the operation of the antenna apparatus is reduced. The frequency f1 is changed to the reception frequency f0
(Time to move to the vicinity) can be shortened.

Further, according to the present invention, the output of the applied voltage generating circuit (15) is supplied through an inductor for removing a high frequency, a resistor, or a series or parallel circuit of a resistor and an inductor. Capacitance conversion element (D1)
The connection is made. As a low-pass filter for removing a high-frequency voltage generated in a circuit, a resistor or a series or parallel circuit of a resistor and an inductor can be used instead of an inductor (choke coil) as in the above configuration.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a diagram showing a circuit configuration of a planar antenna device according to the present invention, FIGS. 2 and 3 are diagrams showing an example of an applied voltage generating circuit, and FIGS. 4 and 5 show waveforms of various parts of a resonance frequency correction circuit. FIG. In order to simplify the description, the same reference numerals are used in the following description for the parts common to the related art.

As shown in FIG. 1, a planar antenna device 1 according to the present embodiment includes an antenna element 2 and a low-noise amplifier 10 composed of a matching circuit 5, a high-frequency amplifier 6, a band-pass filter 7, and a high-frequency amplifier 8. And a voltage-capacitance conversion element (for example, a varactor diode D1) connected between the reception electrode 3 and the ground electrode 4 of the antenna element 2 via a capacitor C5.
And a resonance frequency correction circuit 20 that uses the received output power Pw branched and output from the low noise amplifier 10 via the distributor 9 as a control input. Incidentally, the varactor diode D1 is a variable capacitance element whose capacitance changes according to the applied voltage Vz, and its capacitance change is inversely proportional to the applied voltage Vz, and has a property of decreasing as the applied voltage increases and increasing as the applied voltage decreases.

Hereinafter, the detailed configuration of the resonance frequency correction circuit 20 will be described.

In the resonance frequency correction circuit 20, reference numeral 1
Reference numeral 1 denotes a high-frequency amplifier that power-amplifies the reception output power Pw from the distributor 9, and reference numeral 12 denotes a power-voltage conversion circuit that converts the output power that has been power-amplified by the high-frequency amplifier 11 into a voltage. It comprises a detection circuit, a smoothing circuit, an amplifier and the like.

Reference numeral 13 denotes a sampling circuit which samples the voltage output of the power-voltage conversion circuit 12 at regular intervals and holds the voltage value. The sampling circuit 13 includes two analog switches SW1 and SW2 that perform switching operations in opposite directions (ON circuit / OFF circuit).
And the capacitors C1 and C2 connected to the load side of the analog switches SW1 and SW2, respectively. The voltage output of the power-voltage conversion circuit 12 is alternately supplied to the capacitors C1 and C2 by the switching operation of the analog switch SW1. Hold, and at the same time, the hold voltage Vc1 and Vc of each capacitor by the switch operation of the analog switch SW2.
2 is alternately switched and transmitted to the next stage.

Reference numeral 14 denotes a polarity signal Vd that compares the magnitudes of the hold voltages Vc1 and Vc2, which are sequentially switched and output, and determines the polarity of the voltage change (determines whether the voltage change at the time of switching is increasing or decreasing). This is a polarity discriminating circuit that generates an amplifying circuit composed of an operational amplifier IC1, a resistor R1, and a capacitor C3, and a comparator IC2 provided with a negative reference voltage Vref on the + input side.

Reference numeral 15 denotes an applied voltage generating circuit that controls the applied voltage Vz to the varactor diode D1 based on the polarity of the above-mentioned voltage change, and is latched by the D flip-flop IC3 that latches the polarity signal Vd for a certain period. The JK flip-flop IC4 for generating the voltage change increasing period Tup (see FIG. 5 (g)) and the voltage change decreasing period Tdw (see FIG. 5 (g)) from the polarity signal and the respective periods Tu.
It comprises constant current circuits IS1 and IS2 with switches for charging or discharging the capacitor C4 according to p and Tdw. These flip-flops IC3 and I
The code DL1 inserted in the clock CLK line of C4,
DL2 is a clock signal delay circuit for operating the flip-flop circuits at a suitable timing.

Next, a series of operations of the resonance frequency correction circuit 20 having the above configuration will be described with reference to FIGS.

First, when an error occurs in the resonance frequency of the antenna device 1 due to a change in the resonance system, the reception output power Pw increases or decreases as shown in FIG. 4C. The received output power Pw is voltage-converted by the power-voltage conversion circuit 12, and then sampled at regular time intervals t by a switching operation of the analog switch SW1 which is turned on / off in synchronization with the signal CLK of FIG. Are alternately held (charged) by the capacitors C1 and C2. The voltage waveform Vc1 of the capacitor C1 at this time is shown in FIG.
The voltage waveform Vc2 of FIG. Here, FIG.
In the case of (e), t (n) to t (n + 1), t (n +
2) to t (n + 3) are sampling periods, t (n
+1) to t (n + 2), t (n + 3) to t (n + 4).
Represents a hold period, and in the case of FIG. 4F, t (n−1) to t (n) and t (n + 1) to t (n +
2) is a sampling period, and t (n) to t (n +
1), t (n + 2) to t (n + 3)... Are hold periods.

At the same time, the hold voltages Vc1 and Vc2 of the capacitors C1 and C2 are alternately switched by the analog switch SW2 which switches in the opposite direction to the analog switch SW1 in synchronization with the signal CLK, and a series of operations is performed by the operational amplifier IC1 at the next stage. Input as a voltage waveform. For example, the hold voltage Vc2 of the capacitor C2 held immediately before is output during the hold period of the capacitor C1, and the hold voltage Vc1 of the capacitor C1 held immediately before is output during the hold period of the capacitor C2. Become. The input waveform Vi + of the operational amplifier IC1 at this time is shown in FIG.
When the input waveform Vi + is in the increasing direction as in the period t (n-1) to t (n + 4) of (h), an output Vo which instantaneously largely swings to the + power supply side at the voltage change point is obtained. Thereafter, the voltage stabilizes. Further, the period t (n + 4) to t (n +
When the input waveform Vi + is in the decreasing direction as in 5), an output Vo that instantaneously largely swings to the-power supply side at the voltage change point is obtained, and thereafter becomes stable to a constant voltage as described above. Here, FIG. 4I shows a waveform Vi- fed back to the minus side of the operational amplifier IC1.

The comparator IC2 compares the signal Vc obtained by offsetting the output Vo to the negative side of the reference voltage Vref with the voltage of the feedback waveform Vi- as shown in FIG. 5B. In the stable state, +
Since the input and the − input always generate the potential difference of the reference voltage Vref, the output Vd of the comparator IC2 becomes the H level only during the instantaneous output period greatly swinging to the + power supply side as described above. As a result, FIG. ), The polarity signal Vd indicating the increasing direction of the voltage change is obtained.

The D flip-flop IC3 latches the polarity signal Vd for one clock period to obtain a latch output Vjk shown in FIG. This latch output Vjk is J-
Since the signal is input to the JK terminal of the K flip-flop IC4, the output Vq of the JK flip-flop IC4 is output.
5 operates such that the previous state is maintained when the latch output Vjk is at the L level and inverted when the latch output Vjk is at the H level.
An increase period Tup of the voltage change and a decrease period Tdw of the voltage change shown in (g) are generated. Then, during the increase period Tup of the voltage change, the constant current circuit IS1 is turned on (at this time, the constant current circuit IS2 is turned off), the capacitor C4 is charged, and the applied voltage Vz of the varactor diode D1 is sequentially controlled in the increasing direction. At the same time, in the decrease period Tdw of the voltage change, the constant current circuit IS2 is turned on (at this time, the constant current circuit IS2
1 is turned off), the capacitor C4 is discharged, and the applied voltage Vz of the varactor diode D1 is sequentially controlled in a decreasing direction to obtain a change in the applied voltage Vz as shown in FIG.

In this embodiment, the applied voltage Vz is applied to the varactor diode D1 via the inductor (choke coil L1) for removing the high-frequency voltage. A configuration in which the voltage is applied through a resistor or a series or parallel circuit of a resistor and a choke coil may be adopted.

Further, in the present embodiment, the charging / discharging operation of the capacitor C4 has been described as the current driving by the constant current circuits IS1 and IS2 with switches. However, as shown in FIG. 2, the voltage driving is performed by the two transistors Tr1 and Tr2. Is also good. In the voltage drive type, a capacitor C4 is connected via a resistor R2.
Is performed, the response of the correction operation is delayed by the time constant, but the circuit configuration is simplified as compared with the current drive type.

As shown in FIG. 3, in the configuration of the applied voltage generating circuit 15, the power supply voltage Vcc is substantially 1 /
2, a charging voltage of the capacitor C4 when the power is turned on, that is, a voltage Vz applied to the varactor diode D1,
Can be initialized to about 1/2 of the power supply voltage Vcc, and the resonance frequency f1 can be made as close as possible to the reception frequency f0 at the start of the correction control, thereby shortening the correction time of the resonance frequency. Can be. However, in this case,
A gate circuit IC6 is provided before the constant current circuits IS1 and IS2.
During the initial setting period (Reset period) by providing the IC 7, both the constant current circuits IS1 and IS2 need to be turned off and separated from the capacitor C4.

In this embodiment, the varactor diode D1 is connected to the receiving electrode 3 via the capacitor C5. However, the varactor diode D1 may be connected directly without using the capacitor C5. However, by inserting the capacitor C5, there is an advantage that the capacitance change width with respect to the applied voltage Vz of the varactor diode D1 can be reduced, and the correction range of the resonance frequency f1 can be narrowed and set to a suitable point. The number of varactor diodes D1 to be connected is not limited to one, and a plurality of varactor diodes D1 may be connected in parallel.

As described above, in the present invention, under the control of the resonance frequency correction circuit 20, the voltage Vz applied to the varactor diode D1 is slightly changed every fixed time t, and the reception obtained by the low noise amplifier 10 is performed. The output power Pw is measured at regular intervals, and when the change in the received output power Pw is in the increasing direction, the applied voltage Vz is slightly changed to the same polarity as the previous time,
When the change of the reception output power Pw is in the decreasing direction, the operation of slightly changing the applied voltage Vz to the polarity opposite to the previous time is sequentially performed, so that the resonance frequency f1 of the antenna element 2 is shifted to the vicinity of the reception frequency f0. can do.

As a result, errors in the dimensional accuracy of each electrode pattern involved in the manufacture of the antenna element, variations in the dielectric constant of the dielectric substrate, fluctuations due to mounting on the portable terminal, fluctuations during the use of the portable terminal, and temperature characteristics Thus, it is possible to realize the planar antenna device 1 in which the error of the resonance frequency due to the fluctuation of the resonance system due to various factors is automatically and sequentially corrected, and the output power at the time of reception can always be maintained at the maximum.

Furthermore, if the above-described resonance frequency correction control can reduce the dimensional accuracy of each electrode pattern and the dielectric constant tolerance of a dielectric material related to the manufacture of an antenna element, it would be difficult to achieve an antenna device which has conventionally been difficult. Can be further reduced in size. In addition, the resonance frequency correction circuit 20 of the present invention is formed into an ASIC (Applicaton-Specific IntegratedCi
rcuit) can further promote downsizing and cost reduction. In this case, the high-frequency amplifier 8 in the last stage of the conventional circuit may be incorporated.

[0037]

As described above, in the planar antenna device according to the present invention, the voltage-capacitance conversion element is connected between the reception electrode and the ground electrode of the antenna element, and is controlled at every fixed time under the control of the resonance frequency correction circuit. When the received output power is increased, the applied voltage is slightly changed to the same polarity as the previous time, and when the received output power is decreased, the applied voltage is changed to the opposite voltage. Since the resonance frequency is sequentially shifted to the vicinity of the reception frequency by slightly changing the polarity, the resonance frequency of the planar antenna device due to the manufacturing error of the antenna element, the physical environment around the antenna element, and the change thereof. Are automatically corrected sequentially, so that the reception output power of the radio wave can always be maintained at the maximum.

As a result, the dimensional accuracy of each electrode pattern and the dielectric constant tolerance of the dielectric material, which have been a problem in the related art, can be reduced, so that the material cost can be reduced and the productivity can be improved. The size of the device can be reduced. In addition, there is no need for development work for each model or customer depending on the mounting form, reducing development man-hours, reducing specification troubles, standardizing products, etc., as well as troubles in use by end users (antenna characteristics due to approaching human bodies, etc.) Fluctuations) can be eliminated.

Also, when the power is turned on, the voltage applied to the voltage-capacitance conversion element is initially set to approximately 1/2 of the maximum control voltage width, so that the resonance frequency can be corrected and controlled in a state where the resonance frequency is as close as possible to the reception frequency. Can be started, and the correction time to the maximum output power can be shortened.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a planar antenna device according to the present invention.

FIG. 2 is a diagram illustrating another example of an applied voltage generation circuit.

FIG. 3 is a diagram illustrating an applied voltage generation circuit different from that of FIG. 2;

FIG. 4 is a diagram showing waveforms at various parts of the resonance frequency correction circuit.

FIG. 5 is a diagram illustrating a waveform of a portion of the resonance frequency correction circuit different from that of FIG. 4;

FIG. 6 is a diagram showing a circuit configuration of a conventional planar antenna device.

FIG. 7 is a diagram showing waveforms at various parts of a conventional planar antenna device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Planar antenna device 2 Antenna element 3 Receiving electrode 4 Ground electrode 10 Low noise amplifier 11 High frequency amplifier 12 Power-voltage conversion circuit 13 Sampling circuit 14 Polarity discrimination circuit 15 Applied voltage generation circuit 20 Resonance frequency correction circuit C1, C2, C4, C5 Capacitor D1 Voltage-capacitance conversion element (varactor diode) f0 Reception frequency f1 Resonance frequency IC1 Amplification circuit (Op amp) IC2 Comparison circuit (Comparator) IC3 Latch circuit (D flip-flop) IC4 Flip-flop circuit (JK flip-flop) IS1 Constant current circuit for charging IS2 Constant current circuit for discharging Po Received signal Pw Received output power SW1, SW2 Switch means (analog switch) Tr1 Transistor circuit for charging Tr2 Transistor circuit for discharging Vc1, Vc2 Hold voltage Vd Polarity signal Vz Applied voltage W Radio wave

Claims (6)

(57) [Claims] A planar antenna device (1) comprising an antenna element (2) and a low noise amplifier (10), receiving a radio wave (W) from an artificial satellite or the like and generating a reception signal (Po).
In the above, between the receiving electrode (3) of the antenna element (2) and the ground electrode (4), one or a plurality of voltage-capacitance conversion elements (D1) are connected directly or via a capacitor (C5). A resonance frequency correction circuit (20), and the resonance frequency correction circuit (20) slightly changes the voltage (Vz) applied to the voltage-capacitance conversion element (D1) every predetermined time (t). Low noise amplifier (1
The received output power (Pw) obtained in step 0) is measured at regular intervals, and when the received output power (Pw) changes in an increasing direction, the applied voltage (Vz) is slightly changed to the same polarity as the previous time. In addition, when the change of the received output power (Pw) is in the decreasing direction, by sequentially performing control to slightly change the applied voltage (Vz) to the polarity opposite to the previous time, the resonance frequency of the antenna element (2) is changed. (F1) is sequentially shifted to a position very close to the reception frequency (f0) of the radio wave (W). 2. The high-frequency amplifier (1) that amplifies the reception output power (Pw).
1), a power-to-voltage conversion circuit (12) for converting the amplified output of the high-frequency amplifier (11) into a voltage, and switch means (S) that operate inversely to each other at regular time intervals (t).
W1, SW2) and the switch means (SW1, SW2)
And capacitors (C1, C2) connected to
The output voltage of the power-voltage conversion circuit (12) is alternately held by the capacitors (C1, C2) by the switching operation of the switch means (SW1, SW2), and the respective hold voltages (Vc1, Vc2) are alternately held. A polarity discriminating circuit (13) having a sampling circuit (13) for switching and outputting, an amplifier circuit (IC1) and a comparing circuit (IC2), and sequentially comparing the hold voltages switched and outputted to determine the polarity of the voltage change ( 14. The planar antenna device according to claim 1, comprising: (14). 3. The resonance frequency correction circuit (20) further comprises: a latch circuit (IC3) for holding the determined polarity signal (Vd) of the voltage change for a certain period; and a voltage increase period (Tup) from the latch output. ) And a voltage reduction period (Tdw)
4) and turning on during the voltage increasing period (Tup) to turn on the capacitor (C
4) a charging constant current circuit (IS1) for charging the battery; and a discharging constant current circuit (IS2) for turning on and discharging the capacitor (C4) during the voltage reduction period (Tdw). The planar antenna device according to claim 1, further comprising a voltage generation circuit. 4. The resonance frequency correction circuit (20) further comprises: a latch circuit (IC3) for holding the determined polarity signal (Vd) of the voltage change for a predetermined period; and a voltage increase period (Tup) from the latch output. ) And a voltage reduction period (Tdw)
4) and turning on during the voltage increasing period (Tup) to turn on the capacitor (C
4) Charging transistor circuit (Tr1) for charging
And a discharge transistor circuit (Tr) that is turned on during the voltage decrease period (Tdw) to discharge the capacitor (C4).
3. The planar antenna device according to claim 1, further comprising: an applied voltage generation circuit configured by (2) and (3). 4. 5. The voltage-to-capacity conversion element (D1) applied voltage (Vz) is initially set to approximately ほ ぼ of the maximum voltage control width when power is turned on.
Alternatively, the planar antenna device according to claim 4. 6. An output of the applied voltage generation circuit (15) is connected to the voltage-capacitance conversion element (D1) via an inductor for removing high frequency, a resistor, or a series or parallel circuit of a resistor and an inductor. The planar antenna device according to any one of claims 3 to 5, wherein