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JP3324268B2 - Electrostatic adsorption method - Google Patents

Electrostatic adsorption method

Info

Publication number
JP3324268B2
JP3324268B2 JP7766594A JP7766594A JP3324268B2 JP 3324268 B2 JP3324268 B2 JP 3324268B2 JP 7766594 A JP7766594 A JP 7766594A JP 7766594 A JP7766594 A JP 7766594A JP 3324268 B2 JP3324268 B2 JP 3324268B2
Authority
JP
Japan
Prior art keywords
insulating film
adsorbed
equation
electrostatic
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP7766594A
Other languages
Japanese (ja)
Other versions
JPH07283297A (en
Inventor
徹夫 北林
Original Assignee
東陶機器株式会社
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Publication date
Application filed by 東陶機器株式会社 filed Critical 東陶機器株式会社
Priority to JP7766594A priority Critical patent/JP3324268B2/en
Publication of JPH07283297A publication Critical patent/JPH07283297A/en
Application granted granted Critical
Publication of JP3324268B2 publication Critical patent/JP3324268B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Jigs For Machine Tools (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体ウエハ等の被吸着
物を静電力で静電チャックの吸着面に固定する方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fixing an object to be attracted, such as a semiconductor wafer, to an attracting surface of an electrostatic chuck by electrostatic force.

【0002】[0002]

【従来の技術】減圧雰囲気において半導体ウエハにプラ
ズマエッチング、CVD、イオンプレーティング等の処
理を行なう際の半導体ウエハの固定治具として基板と絶
縁層(誘電層)との間に内部電極を設けた静電チャック
が用いられている。
2. Description of the Related Art An internal electrode is provided between a substrate and an insulating layer (dielectric layer) as a jig for fixing a semiconductor wafer when performing processing such as plasma etching, CVD, and ion plating on the semiconductor wafer in a reduced pressure atmosphere. An electrostatic chuck is used.

【0003】この静電チャックに要求される特性は、電
圧を印加している間は大きな吸着力を発生して被吸着物
の落下等を防止し、電圧印加を解除したならば直ちに吸
着力を小さくして被吸着物を容易に取外すことができる
ようにすることである。
[0003] The characteristics required of this electrostatic chuck are that, while a voltage is applied, a large suction force is generated to prevent the object to be sucked from dropping, etc., and immediately after the voltage application is released, the suction force is reduced. The object is to reduce the size so that the object can be easily removed.

【0004】そこで本発明者は静電チャックの等価回路
に着目し、この等価回路から、静電力残留時間と絶縁層
の体積固有抵抗、絶縁層の比誘電率、絶縁層または保護
膜の厚さ等を結び付けることにより、静電力が短時間で
減衰する静電チャックを提案した。(特開平5−630
62号)
Therefore, the present inventor has focused on an equivalent circuit of the electrostatic chuck, and based on the equivalent circuit, the electrostatic force remaining time, the volume resistivity of the insulating layer, the relative permittivity of the insulating layer, the thickness of the insulating layer or the protective film. We proposed an electrostatic chuck in which electrostatic force attenuates in a short time by combining the above. (JP-A-5-630
No. 62)

【0005】図1は特開平5−63062号において示
した等価回路であり、等価回路の要素であるキャパシタ
ンスC1、C2及びコンダクタンスG1、G2は、絶縁層の
体積固有抵抗をρ(Ωm)、絶縁層の比誘電率をεr
内部電極と絶縁層表面との間隔(厚さ)をd(m)、ウ
エハの面積をS(m2)、被吸着物と絶縁層表面との間
の接触抵抗をR(Ω)、被吸着物と絶縁層表面とのギャ
ップをδ(m)とすると以下の(数1)によって表わさ
れる。
FIG. 1 is an equivalent circuit shown in Japanese Patent Application Laid-Open No. 5-63062. The capacitances C 1 , C 2 and conductances G 1 , G 2 which are elements of the equivalent circuit represent the volume resistivity of the insulating layer by ρ ( Ωm), the relative permittivity of the insulating layer is ε r ,
The distance (thickness) between the internal electrode and the insulating layer surface is d (m), the area of the wafer is S (m 2 ), the contact resistance between the object and the insulating layer surface is R (Ω), If the gap between the object and the surface of the insulating layer is δ (m), it is expressed by the following (Equation 1).

【0006】[0006]

【数1】 (Equation 1)

【0007】そして、上記の静電チャックに対する電圧
の印加を解除した場合の残留静電力Fは、電圧をV、時
間をtとした場合以下の(数2)によって表わされる。
The residual electrostatic force F when the application of the voltage to the electrostatic chuck is released is expressed by the following (Equation 2) when the voltage is V and the time is t.

【0008】[0008]

【数2】 (Equation 2)

【0009】上記の(数2)において残留静電力の減衰
の早さを決めるのは2(G1+G2)/(C1+C2)の値
であり、ここで残留静電力が飽和静電力に対し98%減
衰するのに要する時間をtsとすると、tsは以下の(数
3)で表わされる。
In the above (Equation 2), it is the value of 2 (G 1 + G 2 ) / (C 1 + C 2 ) that determines the rate of decay of the residual electrostatic force, where the residual electrostatic force is the saturated electrostatic force. the time required to attenuate 98% When t s to, t s is expressed by the following equation (3).

【0010】[0010]

【数3】 (Equation 3)

【0011】ところで、被吸着物がシリコンウエハ等の
場合には接触抵抗Rが十分に大きいのでtsを以下の
(数4)でもって表わすことができる。
When the object to be adsorbed is a silicon wafer or the like, the contact resistance R is sufficiently large, so that t s can be expressed by the following (Equation 4).

【0012】[0012]

【数4】 (Equation 4)

【0013】そして、前記同様従来の静電チャックより
も残留時間が短い(60秒以下)の静電チャックとする
には下記の(数5)を満足するように絶縁層の体積固有
抵抗ρ等を設定すればよい。
As described above, in order to obtain an electrostatic chuck having a shorter residence time (60 seconds or less) than the conventional electrostatic chuck, the volume resistivity ρ of the insulating layer and the like must be satisfied so as to satisfy the following (Equation 5). Should be set.

【0014】[0014]

【数5】 (Equation 5)

【0015】[0015]

【発明が解決しようとする課題】上述したように、理論
的に(数5)を定め、この数式に合せて体積固有抵抗ρ
等を設定して実験を行ったが、全ての静電チャック試験
で良好な結果が得られなかった。この原因を検討したと
ころ、絶縁被膜(SiO2)が被吸着面に形成されている
半導体ウェハと絶縁膜が付着していない半導体ウェハ
(ベアシリコン)とでは吸着特性が異なることが判明し
た。即ち、従来の静電吸着方法では被吸着物である半導
体ウェハの表面の状態によって、最適な吸着特性が得ら
れないことがある。
As described above, (Equation 5) is theoretically determined, and the volume resistivity ρ is determined according to this equation.
The experiment was conducted by setting the above conditions, but good results were not obtained in all the electrostatic chuck tests. After examining the cause, it was found that the semiconductor wafer having the insulating film (SiO 2 ) formed on the surface to be suctioned and the semiconductor wafer having no insulating film (bare silicon) had different adsorption characteristics. That is, in the conventional electrostatic suction method, an optimum suction characteristic may not be obtained depending on the state of the surface of the semiconductor wafer which is the object to be suctioned.

【0016】[0016]

【課題を解決するための手段】上記課題を解決すべく本
発明は、静電チャックによって半導体ウェハ等の被吸着
物を吸着するに先立って、被吸着物の被吸着面に絶縁膜
が付着しているか否か、また形成されている場合にはそ
の厚みはどの程度かを測定し、絶縁膜の有無或いは絶縁
膜の厚さに応じて静電チャックの内部電極に印加する電
圧を制御するようにした。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, according to the present invention, an insulating film is attached to a surface to be attracted of an object to be attracted before the object to be attracted such as a semiconductor wafer is attracted by an electrostatic chuck. To measure the voltage applied to the internal electrodes of the electrostatic chuck according to the presence or absence of the insulating film or the thickness of the insulating film. I made it.

【0017】[0017]

【作用】被吸着物の被吸着面に絶縁膜が付着していると
吸着力が大きくなり、また通電を止めた後の残留静電吸
着力も大きくなる。
When the insulating film adheres to the surface to be adsorbed of the object to be adsorbed, the attraction force increases, and the residual electrostatic attraction force after the energization is stopped also increases.

【0018】[0018]

【実施例】以下に本発明の実施例を添付図面に基づいて
説明する。ここで、図1は絶縁膜が付着していない半導
体ウェハ(ベアシリコン)を吸着した場合の静電チャッ
クの等価回路を示す図、図2は静電チャックの内部電極
への通電波形を示す図、図3は絶縁膜が付着している半
導体ウェハを吸着した場合の静電チャックの等価回路を
示す図であり、静電チャックとしては、基板1上に絶縁
層(誘電層)2を形成し、これら基板1と絶縁層2の間
に電極3を形成し、この電極3をリード線4を介して直
流電源5に接続している。
Embodiments of the present invention will be described below with reference to the accompanying drawings. Here, FIG. 1 is a diagram showing an equivalent circuit of an electrostatic chuck when a semiconductor wafer (bare silicon) to which an insulating film is not attached is attracted, and FIG. 2 is a diagram showing waveforms of current flowing to internal electrodes of the electrostatic chuck. FIG. 3 is a diagram showing an equivalent circuit of an electrostatic chuck when a semiconductor wafer to which an insulating film is attached is attracted. As the electrostatic chuck, an insulating layer (dielectric layer) 2 is formed on a substrate 1. An electrode 3 is formed between the substrate 1 and the insulating layer 2, and the electrode 3 is connected to a DC power supply 5 via a lead wire 4.

【0019】一方、被吸着物としての半導体ウェハWは
アースと直接接続されているか、またはプラズマによる
電気的接続がなされ、特に図3に示す半導体ウェハWに
あっては、絶縁層2の吸着面(上面)と対向する被吸着
面に空気との接触等の原因により絶縁膜(SiO2)6
が形成されている。
On the other hand, the semiconductor wafer W as an object to be attracted is directly connected to the ground or electrically connected by plasma. In particular, in the case of the semiconductor wafer W shown in FIG. absolute by reason such as contact with air to be adsorbed surface facing the (upper surface) Enmaku (SiO 2) 6
Are formed.

【0020】ここで、基板1はAl23、Si34、A
lN或いはSiC等を材料とし、絶縁層2は耐侵食性、
機械強度及び電気特性を考慮すると、Al23を主成分
とし、これにTiO2或いはCr23等の遷移金属酸化
物を絶縁抵抗値の調整用として添加したものを材料とす
る。また絶縁層2の材料としては上記の他にSi34
SiC、AlN、ZrO2、SiO2・Al23またはB
Nからなるセラミックス焼結体或いはクロロプレンゴム
若しくはアクリルゴム等の有機物を材料としてもよい。
Here, the substrate 1 is made of Al 2 O 3 , Si 3 O 4 , A
lN or the SiC or the like as a material, the insulating layer 2 is resistant erodible,
In consideration of mechanical strength and electrical characteristics, the material is composed mainly of Al 2 O 3 to which a transition metal oxide such as TiO 2 or Cr 2 O 3 is added for adjusting the insulation resistance value. The material of the insulating layer 2 may be Si 3 O 4 ,
SiC, AlN, ZrO 2 , SiO 2 · Al 2 O 3 or B
A ceramic sintered body made of N or an organic substance such as chloroprene rubber or acrylic rubber may be used as a material.

【0021】そして、基板1及び絶縁層2を作製するに
は上記の材料を溶剤とともに混練し、これをシート状に
成形した後、基板となるシートの上面または絶縁層2と
なるシートの下面のいずれかにタングステン(W)等の
ペースト状電極材料を塗布し、これらシートを重ねて焼
成することで得る。
In order to manufacture the substrate 1 and the insulating layer 2, the above-mentioned materials are kneaded with a solvent and formed into a sheet, and then the upper surface of the sheet serving as the substrate or the lower surface of the sheet serving as the insulating layer 2 is formed. A paste-like electrode material such as tungsten (W) is applied to one of them, and these sheets are stacked and fired.

【0022】次に、絶縁膜が付着していない半導体ウェ
ハ(ベアシリコン)を吸着した場合(図1)と、絶縁膜
が付着している半導体ウェハを吸着した場合(図3)の
ギャップのコンデンサ成分(キャパシタンス)C1に蓄
積される電荷Q1について考察する。
Next, a capacitor having a gap between a case where a semiconductor wafer (bare silicon) to which an insulating film is not adhered (FIG. 1) and a case where a semiconductor wafer to which an insulating film is adhered (FIG. 3) is adsorbed. Consider the charge Q 1 stored in the component (capacitance) C 1 .

【0023】(ベアシリコンの場合)図1の等価回路に
図2の波形の電源を入力した場合のコンデンサ成分C1
に蓄積される電荷Q1は(数6)で表わされる。尚、T
は電圧印加時間である。
(Case of Bare Silicon) Capacitor component C 1 when power supply having the waveform of FIG. 2 is input to the equivalent circuit of FIG.
The electric charge Q 1 stored in is represented by (Equation 6). Note that T
Is the voltage application time.

【0024】[0024]

【数6】 (Equation 6)

【0025】また、マックスウェルの静電吸着理論式に
上記のQ1を代入することで以下の(数7)が得られ
る。
Further, the following (Equation 7) can be obtained by substituting the above Q 1 into Maxwell's theory of electrostatic adsorption.

【0026】[0026]

【数7】 (Equation 7)

【0027】ここで、現在知られている静電チャックに
は、絶縁層(誘電層)のコンダクタンスG2が極めて小
さいクーロン力型静電チャックと、G2が適度に大きい
ジョンセンラーベック型静電チャックがあり、それぞれ
の0≦t≦TのときのQ1を(数8)及び(数9)に示
す。
Here, currently known electrostatic chucks include a Coulomb force type electrostatic chuck in which the conductance G 2 of an insulating layer (dielectric layer) is extremely small, and a Johnsen-Rahbek type electrostatic chuck in which G 2 is moderately large. There is an electric chuck, and Q 1 when 0 ≦ t ≦ T is shown in (Equation 8) and (Equation 9).

【0028】[0028]

【数8】 (Equation 8)

【0029】[0029]

【数9】 (Equation 9)

【0030】(数8)から、クーロン力型静電チャック
の場合には、静電吸着力がexp項に従って単調減少し、
比誘電率εrが大きく、且つ体積固有抵抗ρが非常に大
きい材料を誘電体として用いれば着脱特性が良くなる
(例えば、εr>10000、ρ>1014Ωm)ことが分るが
一般にこの条件を満足する材料はない。そこで、アルミ
ナ等の比較的比誘電率が小さな材料を用いる場合には、
静電吸着力の大きさは比誘電率に支配されるので、印加
電圧を非常に大きくする必要がある。
From equation (8), in the case of the Coulomb force type electrostatic chuck, the electrostatic attraction force monotonously decreases in accordance with the exp term.
It can be seen that if a material having a large relative dielectric constant ε r and a very large volume resistivity ρ is used as the dielectric, the detachability will be improved (for example, ε r > 10000, ρ> 10 14 Ωm). No material satisfies the condition. Therefore, when using a material having a relatively small relative dielectric constant such as alumina,
Since the magnitude of the electrostatic attraction force is governed by the relative permittivity, the applied voltage needs to be extremely high.

【0031】(数9)から、ジョンセンラーベック型静
電チャックの場合には、静電吸着力がexp項に従って単
調増加し、誘電層のコンダクタンスG2が大きいときは
誘電層とウェハ間の接触抵抗R1が小さくなり、コンダ
クタンスG1は大きくなるため(数9)の括弧内はすば
やく飽和する。即ち、体積固有抵抗ρが適度に小さい場
合には比誘電率εrに関係なく着脱応答性を良くするこ
とができる。また一般にクーロン力型静電チャックより
もQ1を大きくすることが容易で、更に体積固有抵抗ρ
も任意に調整しやすいため、静電チャックを使用する温
度での良好な着脱性を示す体積固有抵抗ρを設定するこ
とが可能となる。
From equation (9), in the case of the Johnsen-Rahbek type electrostatic chuck, the electrostatic attraction force monotonically increases in accordance with the exp term, and when the conductance G 2 of the dielectric layer is large, the distance between the dielectric layer and the wafer is increased. contact resistance R 1 becomes smaller, the conductance G 1 in the parentheses for larger (9) is quickly saturated. That is, when the volume resistivity ρ is reasonably small it is possible to improve the detachable response regardless dielectric constant epsilon r. Also generally easy to increase the Q 1 than Coulombic electrostatic chuck, further volume resistivity ρ
Can easily be adjusted arbitrarily, so that it is possible to set the volume resistivity ρ that shows good detachability at the temperature at which the electrostatic chuck is used.

【0032】尚、t>Tの場合においても、クーロン力
型静電チャック及びジョンセンラーベック型静電チャッ
クについて0≦t≦Tの時と同じことが言える。
Even when t> T, the same can be said for the Coulomb force type electrostatic chuck and the Johnsen-Rahbek type electrostatic chuck when 0 ≦ t ≦ T.

【0033】以上より、絶縁膜が付着していない半導体
ウェハ(ベアシリコン)を吸着する場合には以下の(数
10)に示すような2つの効果の和による電荷が寄与し
ていると考えられる。
From the above, it is considered that when a semiconductor wafer (bare silicon) to which an insulating film is not attached is adsorbed, the electric charge due to the sum of the two effects as shown in the following (Equation 10) contributes. .

【0034】[0034]

【数10】 (Equation 10)

【0035】 (絶縁膜が付着している半導体ウェハの場合)裏面に絶
縁膜が付着している半導体ウェハにあっては、図1に示
すような等価回路で表わすことができず、図3に示す等
価回路に書き直す必要がある。そして、図3に示す等価
回路に前記図2に示した波形を入力すると、キルヒホッ
フの法則により以下の(数11)に示す連立方程式が得
られる。
(In the case of a semiconductor wafer having an insulating film adhered thereto) A semiconductor wafer having an insulating film adhered to the back surface cannot be represented by an equivalent circuit as shown in FIG. It is necessary to rewrite the equivalent circuit shown. When the waveform shown in FIG. 2 is input to the equivalent circuit shown in FIG. 3, the following simultaneous equation (Equation 11) is obtained according to Kirchhoff's law.

【0036】[0036]

【数11】 [Equation 11]

【0037】(数11)に以下の(数12)に示すよう
にx,y,z,x’,y’,z’を代入すると、(数1
3)が得られ、この(数13)をラプラス変換し、微分
公式を適用すると(数14)が得られ、この(数14)
をQ1の像関数であるXについて解くと(数15)のよ
うになり、更にラプラス逆変換することで(数16)に
示すように0≦t≦T(電圧印加中)における容量成分
に溜まる電荷Q1が求まる。また電荷Q2、Q3について
も(数17)、(数18)に示す式で求められる。
By substituting x, y, z, x ', y', z 'into (Equation 11) as shown in (Equation 12), (Equation 1)
(3) is obtained, and this (Equation 13) is subjected to Laplace transform, and a differential formula is applied, (Equation 14) is obtained, and this (Equation 14) is obtained.
The now solved for X is the image function for Q 1 (Equation 15), the capacitance component in addition to 0 ≦ t ≦ T as shown in equation (16) by Laplace inversion (in voltage application) accumulated charge Q 1 is obtained. The charges Q 2 and Q 3 are also obtained by the equations shown in (Equation 17) and (Equation 18).

【0038】[0038]

【数12】 (Equation 12)

【0039】[0039]

【数13】 (Equation 13)

【0040】[0040]

【数14】 [Equation 14]

【0041】[0041]

【数15】 (Equation 15)

【0042】[0042]

【数16】 (Equation 16)

【0043】[0043]

【数17】 [Equation 17]

【0044】[0044]

【数18】 (Equation 18)

【0045】またt>T(電圧解除後)についても以下
の(数19)によって求めることができる。尚(数1
9)にはQ1のみを示し、Q2及びQ3については同様の
ため省略する。更に、絶縁膜が付着している半導体ウェ
ハの場合の静電吸着力Fは以下の(数20)によって計
算できる。
Also, t> T (after the voltage is released) can be obtained by the following (Equation 19). (Equation 1
9) shows only Q 1 , and Q 2 and Q 3 are omitted because they are the same. Further, the electrostatic attraction force F in the case of a semiconductor wafer having an insulating film attached thereto can be calculated by the following (Equation 20).

【0046】[0046]

【数19】 [Equation 19]

【数20】 (Equation 20)

【0047】前記したように、Q1=q1C(t)+q1n(t)+
1j(t)であり、Q1を構成する3つの効果、即ちq
1C(t)、q1n(t)及びq1j(t)について以下に述べる。
尚、t=0、t=∞の場合のq1C(t)、q1n(t)及びq1j
(t)の値は(数21)に示される。
As described above, Q 1 = q 1C (t) + q 1n (t) +
q 1j (t) and the three effects that make up Q 1 , namely q
1C (t), q 1n (t) and q 1j (t) are described below.
Note that q 1C (t), q 1n (t) and q 1j when t = 0 and t = ∞
The value of (t) is shown in (Equation 21).

【0048】[0048]

【数21】 (Equation 21)

【0049】q1c(t)については、電圧印加と同時に
蓄積された電荷q1c(0)がその後振動しながら減衰
し、この電荷q1c(0)の大きさは電圧印加と同時に容
量分割された電位差がギャップのコンデンサC1の両端
に印加された時に生じる電荷を表わしている。その意味
ではq1c(0)による静電吸着力は静電チャックの等価
回路において抵抗成分を考慮しない平行平板コンデンサ
モデルの静電吸着力を表わしている。いわゆるクーロン
力型静電チャックはこのq1c(t)の効果が支配的にな
っていると考えられる。
Regarding q 1c (t), the electric charge q 1c (0) accumulated at the same time as the voltage application is attenuated while oscillating thereafter, and the magnitude of the electric charge q 1c (0) is divided by the capacitance at the same time as the voltage application. potential difference represents the electric charge that occurs when applied to both ends of the capacitor C 1 of the gap. Electrostatic adsorptive force due q 1c (0) in that sense the electrostatic attraction force of the parallel plate capacitor model without considering the resistance component in the equivalent circuit of the electrostatic chuck is Table Wa. It is considered that the so-called Coulomb force type electrostatic chuck is dominated by the effect of q 1c (t).

【0050】q1j(t)については、電圧印加時間の増加
とともに単調増加四、やがて飽和することを示してい
る。この電荷q1j(∞)の大きさは抵抗分割された電位差
がギャップのコンデンサC1の両端に印加された時に生
じる電荷を表わしている。その意味ではq1j(t)静電吸
着力は静電チャックの等価回路において抵抗成分を考慮
したジョンセンラーベック効果により生じる静電吸着力
を表わしていることになる。
Regarding q 1j (t), it is shown that the voltage increases monotonically with the increase of the voltage application time, and eventually becomes saturated. The size of the charge q 1j (∞) represents the charge generated when a potential difference which is resistance-divided is applied to both ends of the capacitor C 1 of the gap. In this sense, the q 1j (t) electrostatic attraction force represents the electrostatic attraction force generated by the Johnsen-Rahbek effect in consideration of the resistance component in the equivalent circuit of the electrostatic chuck.

【0051】q1n(t)については、本発明をなすにあた
って初めて認識された効果であり、ウェハに絶縁膜が付
着している場合に現れることが判明した。このq1n(t)
は正のピーク値を有し、q1n(t)が電圧印加に対する応
答特性に大きな影響を与える可能性がある。そして以上
をまとめると、ウェハに絶縁膜が付着している場合にに
はQ1は(数22)に示すように、q1C(t)、q1n(t)、
1j(t)という3つの効果の和として捉えることができ
る。
The effect of q 1n (t) was recognized for the first time when the present invention was carried out, and it was found that the effect appeared when an insulating film was adhered to the wafer. This q 1n (t)
Has a positive peak value, and q 1n (t) may significantly affect the response characteristics to voltage application. To summarize the above, when the insulating film is attached to the wafer, Q 1 is represented by q 1C (t), q 1n (t),
q 1j (t) can be regarded as the sum of three effects.

【0052】[0052]

【数22】 (Equation 22)

【0053】以上の理論式に基づいて計算した結果を図
4乃至図6に示す。ここで、図4は絶縁膜が付着して
ない半導体ウェーハを吸着した場合の時間とギャップの
電荷の関係の計算結果を示すグラフ、図5は絶縁膜が付
着している半導体ウェハを吸着した場合の時間とギャッ
プの電荷の関係の計算結果を示すグラフ、図6は絶縁膜
が付着している半導体ウェーハと絶縁膜が付着していな
い半導体ウェーハを吸着した場合の静電吸着力の計算結
果を比較したグラフである。尚、図4において、q
1c(t)は0であり、q1n(t)はないので、Q1はq
1j(t)と重なることになる。図6からは裏面に絶縁膜
が付着したウェハの方が、ベアシリコンのみの場合より
も静電吸着力が大きいが、静電吸着応答特性及び残留静
電吸着応答特性において若干劣ることが予想される。
FIGS. 4 to 6 show the results calculated based on the above theoretical formula. Here, FIG. 4 is adhered insulating film
Graph showing no time when the semiconductor wafer adsorbed and calculation results of the relationship between the charge of the gap, Figure 5 is the calculation result of the relationship between time and gap of the charge in the case of adsorbing the semiconductor wafer adhering insulating film The graph shown in FIG. 6 is a graph comparing the calculation results of the electrostatic attraction force when a semiconductor wafer having an insulating film attached thereto and a semiconductor wafer having no insulating film attached thereto are attracted. In FIG. 4, q
Since 1c (t) is 0 and there is no q 1n (t), Q1 is q
1j (t). From FIG. 6, it is expected that the wafer with the insulating film adhered to the back surface has a larger electrostatic attraction force than the case of bare silicon alone, but is slightly inferior in the electrostatic attraction response characteristics and the residual electrostatic attraction response characteristics. You.

【0054】以上の理論を実証するため実験を行った。
実験は印加電圧と静電吸着力との関係、電圧印加時
間と静電吸着力との関係、残留時間と残留静電吸着力
との関係について行い、静電吸着力の測定は被吸着体で
あるウェハを静電チャックに吸着させた後に、被吸着体
を垂直方向に引っ張り試験を行い、剥離する時の荷重を
測定することで行った。ここで、被吸着体としては、直
径10mmのベアシリコンウェハ及び裏面に絶縁膜が付
着したウェハを用意し、これらウェハを切り出し、ミラ
ー面に約330gの金属を導電性接着剤で裏打ちした。
また、静電チャック及び被吸着体間への電圧の印加手段
は、静電チャックの内部電極と被吸着体間にDC電圧を
所定時間印加でき、その後静電チャックと被吸着体をと
もに接地することができる装置とした。また、静電チャ
ックと被吸着体はチャンバー内に設置し、真空(約1P
a)及び大気中(温度22℃、湿度40%)での測定が
可能なようにした。
An experiment was conducted to verify the above theory.
The experiment was conducted on the relationship between the applied voltage and the electrostatic attraction force, the relationship between the voltage application time and the electrostatic attraction force, and the relationship between the residual time and the residual electrostatic attraction force. After a certain wafer was adsorbed on the electrostatic chuck, the object to be adsorbed was subjected to a tensile test in the vertical direction, and the load at the time of peeling was measured. Here, a bare silicon wafer having a diameter of 10 mm and a wafer having an insulating film adhered to the back surface were prepared as the objects to be attracted, and these wafers were cut out, and about 330 g of metal was lined on the mirror surface with a conductive adhesive.
Further, the means for applying a voltage between the electrostatic chuck and the object to be attracted can apply a DC voltage between the internal electrode of the electrostatic chuck and the object to be attracted for a predetermined time, and then ground both the electrostatic chuck and the object to be attracted. The device can be used. In addition, the electrostatic chuck and the object to be attracted are set in a chamber, and a vacuum (about 1 P
a) and in the atmosphere (temperature 22 ° C., humidity 40%).

【0055】また、印加電圧と静電吸着力との関係に
ついては、所定電圧を印加し、所定電圧印加時間(60
秒)経過後に引っ張り試験を開始し、電圧印加時間と
静電吸着力との関係については、一定の電圧(400
V)を印加し、所定電圧印加時間経過後に引っ張り試験
を開始し、残留時間と残留静電吸着力との関係につい
ては、一定の電圧(400V)を一定時間(60秒)印
加した後、静電チャックの内部電極及び被吸着体をとも
に接地し、それから所定時間経過後に引っ張り試験を開
始しするようにした。
As for the relationship between the applied voltage and the electrostatic attraction force, a predetermined voltage is applied and a predetermined voltage application time (60 hours) is applied.
Seconds), a tensile test is started, and a constant voltage (400
V), a tensile test is started after a predetermined voltage application time has elapsed, and the relationship between the residual time and the residual electrostatic attraction force is determined by applying a constant voltage (400 V) for a constant time (60 seconds), The internal electrode of the electric chuck and the object to be attracted were both grounded, and after a lapse of a predetermined time, the tensile test was started.

【0056】図7から、裏面に絶縁膜が付着したウェハ
の方が、ベアシリコンのみの場合よりも静電吸着力が大
きいことが実証され、図8から、裏面に絶縁膜が付着し
たウェハの方が、ベアシリコンのみの場合よりも静電吸
着応答特性において若干劣ることが数値的に示され、更
に図9から、裏面に絶縁膜が付着したウェハの方が、ベ
アシリコンのみの場合よりも残留静電吸着応答特性にお
いて若干劣ることが数値的に示された。
FIG. 7 proves that the wafer having the insulating film attached to the back surface has a larger electrostatic attraction force than the case of bare silicon alone. Numerically, it is numerically shown that the electrostatic adsorption response characteristic is slightly inferior to the case of bare silicon alone. Further, from FIG. 9, the wafer having the insulating film adhered to the back surface is better than the case of only bare silicon. It was shown numerically that the residual electrostatic adsorption response characteristics were slightly inferior.

【0057】そこで、半導体ウェハ等の被吸着物の被吸
着面側に絶縁膜があるか否かを検出するか、或いは被吸
着面側に付着している絶縁膜の厚さを測定し、絶縁膜の
有無或いは絶縁膜の厚さに応じて絶縁膜が付着していな
い場合の理論値よりも小さな電圧を印加するようにすれ
ば、必要な吸着力は確保したまま、通電を止めた後の残
留静電吸着力を小さくすることができる。
Therefore, it is detected whether or not an insulating film is present on the surface to be sucked of the object to be sucked such as a semiconductor wafer, or the thickness of the insulating film adhered to the surface to be sucked is measured. If a voltage smaller than the theoretical value in the case where the insulating film is not attached is applied according to the presence or absence of the film or the thickness of the insulating film, the necessary adsorbing force is secured, and after the energization is stopped. The residual electrostatic attraction force can be reduced.

【0058】ここで、絶縁膜の厚さについては絶縁膜の
シート抵抗を測定し、このシート抵抗値から絶縁膜の厚
さを算出するようにすることが考えられる。
Here, regarding the thickness of the insulating film, it is conceivable to measure the sheet resistance of the insulating film and calculate the thickness of the insulating film from the sheet resistance value.

【0059】[0059]

【発明の効果】以上に説明した如く本発明によれば、静
電チャックによって半導体ウェハ等の被吸着物を吸着す
るにあたり、前もって被吸着物の被吸着面に絶縁膜が付
着しているか否か、また形成されている場合にはその厚
みを測定し、絶縁膜の有無或いは絶縁膜の厚さに応じて
静電チャックの内部電極に印加する電圧を、絶縁膜が付
着していない場合の理論値よりも小さくしたので、必要
な吸着力は確保したまま、通電を止めた後の残留静電吸
着力を小さくすることができる。
As described above, according to the present invention, when an object to be adsorbed such as a semiconductor wafer is adsorbed by an electrostatic chuck, it is determined whether or not an insulating film has previously adhered to the surface of the object to be adsorbed. In addition, if it is formed, its thickness is measured, and the voltage applied to the internal electrode of the electrostatic chuck according to the presence or absence of the insulating film or the thickness of the insulating film is calculated based on the theory when the insulating film is not attached. Since the value is smaller than the value, it is possible to reduce the residual electrostatic attraction force after the energization is stopped while maintaining the required attraction force.

【図面の簡単な説明】[Brief description of the drawings]

【図1】絶縁膜が付着していない半導体ウェハ(ベアシ
リコン)を吸着した場合の静電チャックの等価回路を示
す図
FIG. 1 is a diagram showing an equivalent circuit of an electrostatic chuck when a semiconductor wafer (bare silicon) to which an insulating film is not attached is attracted.

【図2】静電チャックの内部電極への通電波形を示す図FIG. 2 is a diagram showing a waveform of a current applied to an internal electrode of the electrostatic chuck.

【図3】絶縁膜が付着している半導体ウェハを吸着した
場合の静電チャックの等価回路を示す図
FIG. 3 is a diagram showing an equivalent circuit of an electrostatic chuck when a semiconductor wafer to which an insulating film is attached is sucked;

【図4】絶縁膜が付着している半導体ウェハを吸着した
場合の時間とギャップの電荷の関係の計算結果を示すグ
ラフ
FIG. 4 is a graph showing a calculation result of a relationship between time and charge of a gap when a semiconductor wafer to which an insulating film is attached is sucked;

【図5】絶縁膜が付着していない半導体ウェハを吸着し
た場合の時間とギャップの電荷の関係の計算結果を示す
グラフ
FIG. 5 is a graph showing a calculation result of a relationship between time and charge in a gap when a semiconductor wafer to which an insulating film is not attached is sucked;

【図6】絶縁膜が付着している半導体ウェハと絶縁膜が
付着していない半導体ウェハを吸着した場合の静電吸着
力の計算結果を比較したグラフ
FIG. 6 is a graph comparing calculated results of electrostatic attraction force when a semiconductor wafer having an insulating film attached thereto and a semiconductor wafer having no insulating film attached thereto are attracted;

【図7】印加電圧と静電吸着力との関係の実験結果を示
すグラフ
FIG. 7 is a graph showing an experimental result of a relationship between an applied voltage and an electrostatic attraction force.

【図8】電圧印加時間と静電吸着力との関係の実験結果
を示すグラフ
FIG. 8 is a graph showing an experimental result of a relationship between a voltage application time and an electrostatic attraction force.

【図9】残留時間と残留静電吸着力との関係の実験結果
を示すグラフ
FIG. 9 is a graph showing an experimental result of a relationship between a residual time and a residual electrostatic attraction force.

【符号の説明】[Explanation of symbols]

1…基板、2…絶縁層(誘電層)、3…内部電極、4…
リード線、5…電源、6…絶縁膜、W…半導体ウエハ。
DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Insulating layer (dielectric layer), 3 ... Internal electrode, 4 ...
Lead wires, 5: power supply, 6: insulating film, W: semiconductor wafer.

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/68 B23Q 3/15 H02N 13/00 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/68 B23Q 3/15 H02N 13/00

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 絶縁層内に内部電極を設けた静電チャッ
クの吸着面に半導体ウェハ等の被吸着物を載置し、前記
内部電極と被吸着物との間に電圧を印加し静電吸着力に
よって被吸着物を吸着するようにした静電吸着方法にお
いて、前記被吸着物を吸着面に載置する前に被吸着物の
被吸着面側に絶縁膜があるか否かを検出し、絶縁膜が付
着している場合には絶縁膜が付着していない場合の理論
値よりも小さな電圧を印加するようにしたことを特徴と
する静電吸着方法。
An object to be attracted such as a semiconductor wafer is placed on an attracting surface of an electrostatic chuck having an internal electrode provided in an insulating layer, and a voltage is applied between the internal electrode and the object to attract the object. In the electrostatic adsorption method in which an object to be adsorbed is adsorbed by an adsorption force, it is detected whether or not an insulating film is present on the surface to be adsorbed of the object to be adsorbed before placing the object to be adsorbed on the adsorption surface. And a method of applying a voltage smaller than a theoretical value when the insulating film is not adhered when the insulating film is adhered.
【請求項2】 絶縁層内に内部電極を設けた静電チャッ
クの吸着面に半導体ウェハ等の被吸着物を載置し、前記
内部電極と被吸着物との間に電圧を印加し静電吸着力に
よって被吸着物を吸着するようにした静電吸着方法にお
いて、前記被吸着物を吸着面に載置する前に被吸着物の
被吸着面側に付着している絶縁膜の厚さを測定し、当該
絶縁膜の厚さに応じて絶縁膜が付着していない場合の理
論値よりも小さな電圧を印加するようにしたことを特徴
とする静電吸着方法。
2. An object to be sucked such as a semiconductor wafer is placed on a suction surface of an electrostatic chuck having an internal electrode provided in an insulating layer, and a voltage is applied between the internal electrode and the object to be electrostatically attracted. In the electrostatic adsorption method in which an object to be adsorbed is adsorbed by an adsorption force, the thickness of the insulating film adhered to the surface to be adsorbed of the object to be adsorbed before the object to be adsorbed is placed on the adsorption surface. A method for measuring electrostatic force, wherein a voltage smaller than a theoretical value in a case where an insulating film is not attached is measured in accordance with a thickness of the insulating film.
【請求項3】 請求項2に記載の静電吸着方法におい
て、前記絶縁膜のシート抵抗を測定し、このシート抵抗
値から絶縁膜の厚さを算出するようにしたことを特徴と
する静電吸着方法。
3. The electrostatic chucking method according to claim 2, wherein a sheet resistance of the insulating film is measured, and a thickness of the insulating film is calculated from the sheet resistance value. Adsorption method.
JP7766594A 1994-04-15 1994-04-15 Electrostatic adsorption method Expired - Fee Related JP3324268B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7766594A JP3324268B2 (en) 1994-04-15 1994-04-15 Electrostatic adsorption method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7766594A JP3324268B2 (en) 1994-04-15 1994-04-15 Electrostatic adsorption method

Publications (2)

Publication Number Publication Date
JPH07283297A JPH07283297A (en) 1995-10-27
JP3324268B2 true JP3324268B2 (en) 2002-09-17

Family

ID=13640181

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Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3324268B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10720858B2 (en) 2015-04-02 2020-07-21 Ulvac, Inc. Attraction device, method for producing attraction device, and vacuum processing device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001118776A (en) 1999-10-19 2001-04-27 Nikon Corp Transfer aligner, and mask holding mechanism used for that device, and manufacturing method of semiconductor element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10720858B2 (en) 2015-04-02 2020-07-21 Ulvac, Inc. Attraction device, method for producing attraction device, and vacuum processing device

Also Published As

Publication number Publication date
JPH07283297A (en) 1995-10-27

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