JP3321295B2 - Disk unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sector servo type disk drive for positioning a head based on servo information recorded on a data surface, and more particularly to a sector mark or a cylinder recorded together with servo information in a servo frame at the head of a sector. The present invention relates to a disk device that accurately detects a gray code indicating an address.

[0002]

2. Description of the Related Art In recent years, small hard disks have been mounted as external storage devices for securing storage capacity in notebook computers and portable communication terminals. Such a small hard disk uses a small disk medium of, for example, 3.5 inches or 2.5 inches, and incorporates one or two disk media in order to make the unit thin.

For this reason, unlike a conventional large-sized disk device, a dedicated servo surface for recording servo information for head positioning cannot be provided, and a sector servo system in which servo information is recorded on a data surface is employed. I have. For example, one cylinder is divided into 60 sectors, and a servo frame is recorded at the head of each sector. The servo frame includes a sector mark indicating the servo frame, a gray code for detecting a cylinder address, an index pattern (only the first sector), an AGC pattern for setting an AGC level of a read amplifier, and a servo pattern for detecting a head position. Are magnetically recorded.

[0004]

In a disk device adopting the sector servo system, the shorter the servo frame, the larger the data area in the sector. Therefore, in order to increase the storage capacity, data is recorded in the servo frame. It is desirable to minimize each pattern as necessary. vice versa,
In order to increase the accuracy of detecting patterns such as sector marks and gray codes recorded on servo frames, the recording pitch in the cylinder direction per pattern is increased. For example, the sector mark has a recording pattern of “N □ S □ NS”, and if the recording cycle determined by the reference clock is T, “1”
6T, 16T, 10T, 10T "for a total of 52T
Is required.

The gray code recorded following the sector mark has, for example, a bit width of 6T and "G12,
G11,..., G0, GH ”are recorded in gray code“ X000X000 ”, and have a length of 84T. Further, about 160T is required as a position area. This results in 196T for the entire servo frame.
Here, assuming that the interval between one servo frame is 3600T, the servo area occupies 5.4% of one track, and the storage capacity can be increased by shortening the sector mark and the gray code. However, shortening the sector mark and the gray code lowers the pattern detection accuracy, so there is a limit.

Accordingly, it is an object of the present invention to provide a disk device capable of increasing a storage capacity by shortening a recording area of a sector mark and a gray code without lowering a detection rate. On the other hand, in a disk device using a conventional sector servo system, a deviation value due to eccentricity of a disk medium is measured, and eccentricity is corrected at the time of on-track control. For the measurement of the eccentricity correction value for this purpose, an eccentricity correction command is issued every predetermined time, and the deviation value from the track center is stored in a RAM or the like. During normal on-track control, the head can always be positioned at the center of the track by performing on-track control by subtracting the previously measured deviation value from the target position.

[0007]

[0008]

[0009]

[0010]

[0011]

FIG. 1 is a diagram illustrating the principle of the present invention. Note that reference numerals of the embodiments are shown in parentheses. First, as shown in FIG. 1B, the disk device of the present invention adopts a sector servo system using a disk medium having a plurality of sector areas provided with a servo area 60 and a data area 62 on the same cylinder. The servo area (servo frame) 60 of each sector of the disk medium has at least a sector mark 66 indicating a servo area, a gray code 68 which is a code indicating a cylinder address, and a predetermined servo pattern 74 for detecting a head position. Magnetic recording.

The disk control means 24 includes the head means 14
Based on the read signal of the servo pattern 74, the head position is detected, and the read / write operation is performed by positioning the head means 14 at an arbitrary cylinder. The detection of the sector mark 66 and the gray code 68 recorded in the servo area is performed based on both the peak and the polarity of the read signal. FIG. 1 (A)
The peak detecting means 90 shown in (1) detects a time interval between the peaks of the read signals of the sector mark 66 and the gray code 68 read by the head means 14, and outputs a peak detection pulse. The polarity detection means 92 detects the polarity of the read signal of the sector mark 66 and the gray code 68 read by the head means 14 and outputs a polarity signal.

In this case, since the magnetic recording of the mark or the pattern is performed by alternately recording the N pole and the S pole, a read signal of a positive polarity is obtained by reading the N pole, for example, and the peak and the polarity are detected. Then, a read signal of negative polarity is obtained by reading the S pole, and its peak and polarity are detected, and this is repeated alternately. The sector mark detection means 96 detects the sector mark 66 based on the peak detection pulse of the peak detection means 90 and the polarity signal of the polarity detection means 92 and notifies the disk control means 24 of the detection. Therefore, the sector mark detecting means 96 includes the peak comparing means 104, the polarity comparing means 1
14 and a gate means 122. Peak comparison means 1
Reference numeral 04 compares a peak sequence, which is a time series of peak detection pulses over the reading period of the sector mark, with a peak reference sequence corresponding to magnetic recording of the sector mark, and outputs a peak match signal when the two match.

The polarity comparing means 114 compares the polarity sequence, which is a time series of the polarity signal over the reading period of the sector mark, with the polarity reference sequence corresponding to the magnetic recording pattern of the sector mark. Outputs a match signal. The gate means 122 is a peak comparing means 1
When a coincidence signal is obtained from both of the signal 04 and the polarity comparing means 114, a detection signal of a sector mark is output.

Any one of the read signals of the sector mark
Redundancy is provided so that even if one is missing, it can be detected. For this reason, the sector mark detecting means 96 performs the peak comparing means and the polarity comparing means for each of the read sequence signal corresponding to the magnetic recording of the sector mark and the read sequence signal in which one of the read signals of the magnetic recording of the sector mark is missing. Means and a gate means, and outputs a sector mark detection signal based on a coincidence signal of any one of the plurality of gate means.

In this case, there is provided a control register means 130 for selectively enabling a plurality of gate means by setting bits in the disk control means 24. This control register means 1
On the other hand, the disk control means 24 detects the first sector mark after positioning at a specific cylinder, and enables the gate means 104 which outputs a coincidence signal based on a read sequence signal coincident with the magnetic recording of the sector mark. Set the bit.

Regarding the detection of the second and subsequent sector marks, a bit is set in the control register means 130 so that other gate means for outputting a coincidence signal are also effective even if the read sequence signal is missing. For this reason, the detection of the first sector mark after entering the on-track control,
You need to match the exact pattern exactly,
Once a sector mark has been detected, even if one of the patterns is missing, it can be detected without causing a reading error.

A cylinder address detecting means (gray code detecting means) 94 for detecting a cylinder address from a gray code also receives a gray code peak detection pulse from the peak detecting means 90 and a gray code polarity signal from the polarity detecting means 92. Based on this, the gray code is detected, and at the same time, the cylinder address is determined and notified to the disk control means 24.

The cylinder address detection means (gray code detection means) 94 restores a bit string indicating a cylinder address using a status counter in addition to the peak detection pulse and the polarity signal. Status counter means 13
Numeral 8 repeatedly counts the state state based on the recording bit length N of the gray code in the reference cycle T. For example, in the servo frame of the disk medium, 6
When the gray code of “X00X00” is magnetically recorded in the cycle of T, the sequence counter 138 counts 0 to indicate the six state states 0, 1, 2, 3, 4, 5, and 0.
5 is counted repeatedly in the reference cycle (T).

This status counter means 138
Count "100,000" forcibly entering state 1 under the condition that both the peak and the polarity are correctly detected at the bit "X" portion in the gray code of T, that is, at the timing of state 0 and state 3. , And the count "000100" for the state 3 state.

That is, when the first preset means 140 detects both the peak detection pulse of the read signal of positive polarity and the polarity signal thereof, the status counter means 138 is preset to the state of the state count 0, and the second preset means 140 is set. When 142 detects both the negative read signal peak detection pulse and its polarity signal, the status counter 138 is preset to the state of state count 3.

The detection output when both the peak detection pulse of the read signal of the positive polarity and the polarity signal are obtained, or the output of the status counter means 138 in the first state is latched by the first latch means 160. A detection output when both the peak detection pulse of the negative polarity read signal and its polarity signal are obtained, or the status counter means 13
8 is output to the second latch means 164.

Finally, the first and second latch means 16
The logical sum of 0 and 164 is taken by the gate means 166 to restore the address bits. That is, in response to the normal reading of the gray code "100100" indicating the address bit 1, the first and second latch means 160 and 164 latch the state 0, 3 sequence of "11" and restore the bit 1.
Also, a gray code “00000” indicating address bit 0
0, the first and second latch means 16
0,164 latches "00" and restores bit 0.

Further, a gray code “10” indicating bit 1
Even if one of the read signals corresponding to the code “1” in “0100” is lost, bit 1 can be normally restored as long as the other is normal. First and second latch means 16
The latch sequence of 0,164 is "01" or "10"
In each case, bit 1 can be normally restored. If the gray code corresponding to the continuation of the bit 0 continues, the peak and polarity detections are not performed, so that the status counter unit 138 is placed in a free-run state and may malfunction. Therefore, a dummy code "100100" for forcibly presetting the status counter 138 is inserted in the middle of the gray code.

An advantage of the sector servo method is that eccentricity correction for thermal offset or the like can be performed for each cylinder. In the case of the servo surface servo method, servo information is purposely recorded in a guard band area or the like on the data surface, and a deviation value is measured and corrected for each data surface from the servo information. On the other hand, in the sector servo method, the eccentricity deviation value can be measured and corrected for each cylinder, and the head positioning accuracy is high.

[0026]

[0027]

[0028]

[0029]

[0030]

According to the disk device of the present invention, the following effects can be obtained. First, by detecting the sector mark and gray code recorded on the servo frame and adding the polarity detection in addition to the peak detection of the read signal, the sector mark and gray code can be reliably detected even if the recording length is short. Can be. Therefore, the pattern recording length can be reduced without lowering the detection rate, and the format efficiency of the sector servo can be increased to increase the storage capacity.

Since the eccentricity correction using the sector servo in the on-track control can be realized in real time, the accuracy of the control of the track king with respect to the temperature fluctuation can be greatly improved, and no error occurs even if the track recording density is sufficiently increased. Can be read or written. Furthermore, a sector pulse can be generated to have an arbitrary sector length without being constrained by physical sector servo information. Split recording by dividing block data, slip processing of bad sectors, and fixing during digital error test It is possible to easily generate a sector pulse at an arbitrary timing as needed, such as generation of a typical sector pulse.

[0032]

【Example】

<Table of Contents> Hardware configuration 2. 2. Servo frame 3. Detection of sector mark 4. Detection of gray code 5. Real-time eccentricity correction Variable control of sector size 2. Hardware Configuration FIG. 2 shows an example of the overall configuration of the disk drive of the present invention.
2, the disk device of the present invention includes a disk enclosure 10 and a drive controller 12. The disk device according to the present invention is, for example, a small disk device using three 2.5-inch disk media. In the disk enclosure 10, head portions 14-1 to 14-1 corresponding to six data surfaces of three disk media are provided.
4-6 are provided, and the head portions 14-1 to 14-6 are provided at the tip of the head arm, and are supported movably in the radial direction of the disk medium.

Each of the heads 14-1 to 14-6 has
Read heads 15-1 to 15-6 and write head 16-
1 to 16-6 are provided integrally. Light head 1
A magnetic head is used as 6-1 to 16-6, and an MR head using a magnetoresistive element is used as read heads 15-1 to 15-6. Read head 15-1
The head units 14-1 to 14-6 having the write heads 16-1 to 16-6 are connected to a head IC circuit 18 for head switching, and read heads 15-1 to 15- using an MR head. 6 and the like. The disk enclosure 10 includes a spindle motor 22 for rotating a disk medium, and a head unit 14.
A voice coil motor (hereinafter, referred to as "VCM") 20 for positioning -1 to 14-6 is provided.

The drive controller 12 is mounted on a printed circuit board that is integrally assembled with the case of the disk enclosure 10. The drive controller 12 is provided with an MPU 24 that functions as various processing units. The bus 58 of the MPU 24 is provided with a read-only EPROM 26 used as a program memory and a readable / writable DRAM 28.

In the EPROM 26, a start-up program (boot program) used at the time of start-up when the power of the disk drive is turned on is fixedly stored. DRAM 28
After the start-up of the disk device by the start-up program of the EPROM 26 is completed,
A control program (micro program) downloaded from the disk medium on the side is stored.

The bus 58 of the MPU 24 is further provided with an interface circuit 30 and a buffer memory 32 for data transfer. As the interface circuit 30, for example, S
The CSI is used to exchange commands and data required as an external storage device with respect to the host computer, for example, using a notebook computer equipped with the disk device of the present invention as a host computer. Further, the cache controller 31 and the cache memory 3
3 are provided.

The control of the spindle motor 22 provided in the disk enclosure 10 is performed by a PWM circuit 34 and a driver 36. The head positioning control of the VCM 20 provided in the disk enclosure 10 is performed by the DA converter 38 and the driver 40. In any case, driving of the spindle motor 22 and positioning control of the VCM 20 are performed by program control by the MPU 24.

The drive controller 12 is provided with an AGC amplifier 42, an equalizer circuit 44, a maximum likelihood detection circuit 46, an encoder / decoder 50, and a hard disk controller 52 as a read / write system. Further, a peak hold circuit 5 is used as a servo system for head position control.
4. An AD converter 55 and a servo frame demodulation circuit 56 are provided.

At the time of a read operation, the head IC circuit 18 is switched to the read head 15 by a switching signal from the hard disk controller 52, and an analog read signal from the read head 15 is input to the AGC amplifier 42. The analog read signal is amplified by an AGC amplifier 42, subjected to waveform equalization by an equalizer circuit 44, and applied to a maximum likelihood detection circuit 46 and a VFO circuit 48. VFO
The circuit 48 generates a reference clock synchronized with the read signal during the read operation.

The outputs of the maximum likelihood detection circuit 46 and the VFO circuit 48 are supplied to an encoder / decoder 50 which has been switched to the decoder side in a read state, and the read data is restored while synchronizing with the clock. And then transferred to the buffer memory 32. Then, the interface circuit 3
0, the read data is transferred to the host device.

On the other hand, in the write operation, the write data transferred to the buffer memory 32 via the interface circuit 30 is transferred via the hard disk controller 52 to the encoder / decoder switched to the encoder during the write operation. Supply 50. Encoder /
The decoder 50 performs, for example, conversion of the write data to a 2-7 run-length code or the like, addition of an ECC check code, and the like.
To supply. Servo information according to the sector servo method is recorded on a disk medium provided in the disk enclosure 10. 2. FIG. 3 shows a format for one cylinder in the disk medium of the present invention. In FIG. 3, the recording area for one cylinder, which is extended on a straight line, is divided into, for example, 60 sectors. Servo frames 60-0 to 60-59 are provided at the head of each sector, and 62-0 to 62-59. The length of one cylinder divided into 60 sectors is fixedly defined by a predetermined number of clocks using a reference clock.
It becomes 0T.

The servo frame 60-0, as shown in an enlarged manner on the lower side, has an R / W recovery area 64, a sector mark area 66, a gray code area 68, and an index area 7.
0, an AGC area 72, a servo area 74, and a gap area (pad area) 84. The length of each area can be represented using the reference clock period T. That is, R
The / W recovery area 64 has a length of 123T and the sector mark area 66 has a length of 18T, which is sufficiently shorter than the conventional case of 54T.

The index area 70 is 6T, and the index pattern is recorded only for the first servo frame 60-0 among the servo frames 60-0 to 60-59. The AGC area 72 is 45T long. The servo area 74 has a length of 96T. Since the sector servo of the present invention employs, for example, a two-phase servo method, the servo area 74 has a first field 76, a second field 78, and a third field 80 of 24T each.
In addition, servo patterns are recorded separately in the fourth field 82 and the fourth field 82.

The last gap region 84 is 18T long. Therefore, as the servo frame 60-0, 402
T is sufficient, and the recording length can be greatly reduced as compared with the related art.
This reduction in recording length is due to the fact that the polarity of the read signal, which will be described later, is detected in addition to the peak detection. The remaining servo frames 60-1 to 60-
59 is the same except that magnetic recording is performed in the index area 70.

FIG. 4 shows the servo frame 60- shown in FIG.
0 indicates a read signal. In FIG. 4, the leading R /
In the W recovery area 64, the magnetic recording of the N pole and the S pole is performed alternately at 3T intervals, and as a result, the read signal becomes the read signal of the N pole having a negative polarity, The N-pole read signal is a read signal having a positive polarity. That is, for the R / W recovery area 64, 3T
Are recorded as 41 units of magnetic recording.

The magnetic recording of the next sector mark area 66 is 6
At T, 6T, 3T, and 3T, a pattern of "N, S, N, S" is magnetically recorded. Here, if the frequency of the reference clock is 20 MHz, the clock cycle T = 0.05 μs, and therefore, the time of the 18T sector mark area 66 is 0.9 μs. The next gray code area 68 is divided into three fields of a first field 68-1, a second field 68-2 and a third field 68-3 in this embodiment. The gray code is 1 in which half bit GH is added to code bits G12 to G0 in this embodiment.
It consists of 4 bits.

The 1-bit gray code, for example, the gray code G12 is recorded in 6T,
Is recorded as "100100" over 6T. Of course, in the case of bit 0, magnetic recording of "000000" is performed. Five gray codes G12 to G8 are recorded in the first field 68-1 of the gray code area. Between the first field 68-1 and the second field 68-2, there is provided a dummy field 86 having a length of 6T in which a pseudo gray code "100100" corresponding to bit 1 is recorded.

The dummy field 86 has a function for forcibly performing preset synchronization when a bit 0 continues for a status counter used in a gray code detection circuit which will be described later. Similarly, five gray codes G7 to G3 are recorded in the second field 68-2 of the gray code area at intervals of 6T. Subsequently, the remaining four gray codes G2 to GH are recorded in the third field 68-2 via the dummy area 88 in which the dummy codes are recorded.

The index area 70 has a length of 6T. As shown in FIG. 3, only the servo frame 60-0 of the first sector has a pattern of "100100" of 6T.
Recorded at T. For other sectors, see “000
000 ". The next AGC area 72 includes the AGC amplifier 4 shown in the drive controller 12 of FIG.
The pattern used to determine the reference level of No. 2 is a pattern that is all “100” in 3T units so that amplitude information is obtained.

Next, a servo area is formed. The servo area is divided into a first field 76, a second field 78, a third field 80, and a fourth field 82, and magnetic recording of "100" at 3T is repeated eight by eight. ing. The pattern in the servo area is also magnetic recording for obtaining amplitude information. The last is a gap area 84, in which six "100" are recorded at 3T as pad patterns for providing a gap with the subsequent data frame.

FIG. 5 shows the servo area 74 shown in FIGS.
5 shows the recording state of the servo information and the generation of the position detection signal based on the read signal. FIG. 5A shows a plurality of servo frames on the innermost side of the disk medium taken out in the radial direction.
0, 01, 02, 03, etc., and increase toward the outer side. A predetermined number of cylinders on the inner side are allocated to the stop absorption area 90, and the physical cylinder addresses are all 0. The physical cylinder address 00 next to the stopper absorption area 90 becomes the original head cylinder address.

Gray code area 68 and AGC area 7
The servo area 74 following 0 is the first servo area indicated by A, B, C, and D.
To the fourth field, and finally the gap area 84
Is provided. The servo information is divided into first and second fields A and B and third and fourth fields C and D. The first field A and the second field B are recorded alternately at a track center indicated by a broken line. On the other hand, the third and fourth fields C and D are similarly recorded alternately in units of one cylinder at each track boundary indicated by a solid line.

Further, there is a disc displacement of 0.5 cylinder in the radial direction between the first field A and the third field C, and similarly, there is no radial displacement between the second field B and the fourth field D. .5 cylinder displacement. The read head 15 is controlled to be on-track at the center of the track indicated by the broken line of the cylinder address 00, for example, as shown.

The read signal obtained from the read head 15 in the state where the on-track control is performed at the cylinder address 00 has the voltages shown at points b to e in FIGS. 5B to 5E. These voltages can be obtained by the peak hold of the read signal of the read head 15. FIG. 5F shows a head position signal EN obtained from the read signals of the first field A and the second field B, and FIG. _5G shows a head position signal obtained from the third and fourth fields C and D. shows the E _Q. The head position signal E shown in FIG.
_N is obtained from the read signal E _A of the first field A by subtracting the read signal E _B of the second field B.

[0055] The head position signal E _Q in FIG. 5 (G) is,
From the detection signal E _C of the third field C fourth field D
Obtained by subtracting the detection signal E _D of. Readhead 1
5, the detection signals E _A and E _{B of} the first and second fields A and B are obtained as shown at points b and c, with the on-track control being performed at the cylinder address 00 as shown in the figure.
On the other hand, the detection signals E _C and E _D of the third and fourth fields C and D are at a constant level as shown at points d and e.

The first and second fields A and B correspond to the movement of the read head in the radial direction (vertical direction in the figure) around the track center of cylinder address 00.
Only the detection signals E _A and E _{B of} FIG.
Head position signal E _N changes as shown in (F). On the other hand, the detection signals E _C ,
E _D is constant, also a constant head position signal E _Q in this order Figure 5 (E).

Therefore, in the range of the head width of the read head 15 around the cylinder address 00,
The head detection signal EN shown in FIG. _5F is used. In contrast, when the read head 15, for example, enters the boundary of the cylinder address 00 and 01, third and fourth fields C, and the head position detection signal E _Q in FIG. 5 (G) based on the D it becomes effective.

Therefore, as shown in FIGS. 5F and 5G, the two head position signals E _N and _EQ are switched and used in accordance with the position of the read head 15 so that the head can be moved with respect to the movement of the read head 15. It is possible to obtain a head position detection signal without a dead zone that changes according to the position. The above is 2
Pattern recording and head position detection according to the phase servo method. Needless to say, the servo information of the present invention is not limited to two-phase servo, but may take any appropriate servo information recording form. 3. FIG. 6 shows an embodiment of the servo frame demodulation circuit 56 provided in the drive controller 12 of FIG. In FIG.
The servo demodulation circuit 54 includes a peak detection circuit 90 and a polarity detection circuit 92. A read signal from the equalizer circuit 44 in FIG. 2 is input to the peak detection circuit 90 and the polarity detection circuit 92. The peak detection circuit 90 detects the peak timing of the read waveform of the servo frame as shown in FIG. 4 to detect the peak detection pulse E1.

The polarity detection circuit 92 detects the polarity of the read signal shown in FIG. 4 and outputs a polarity signal E2. The polarity signal E2 is a pulse signal having a logic level 1 with a plus polarity and a logic level 0 with a minus polarity. The synchronization circuit 94 applies the VFO circuit (or oscillator) shown in FIG. 2 for each of the peak detection pulse E1 and the polarity signal E2.
Synchronization is performed using the reference clock CLK obtained from 48. The synchronized peak detection pulse E3 is supplied to a sector mark detection circuit 96, and a sector mark detection process is performed.

At the same time, the synchronized polarity signal E4 is supplied to a gray code detection circuit 98, and a gray code detection process for demodulating a bit sequence of a cylinder address from the gray code is performed. The sector mark detection signal of the sector mark detection circuit 96 is supplied to a gray code detection circuit 98,
Notify the start timing of the servo frame. Similarly,
The sector mark detection signal E5 is also given to the MPU 24,
In the MPU 24, the counter used for managing each area of the servo frame is reset to start the coefficient of the reference clock, and the value of this counter is checked.
Can be recognized. Further, the sector mark detection signal E5 is supplied to the sector pulse generation circuit 100, and generates a sector pulse E9 at an arbitrary timing based on the detection time of the sector mark.

The MPU2 is output from the gray code detection circuit 98.
4, a gray code detection signal E6 indicating the gray codes G12 to GH is output as a detection result. To the sector pulse generation circuit 100, a time setting signal E7 for determining the generation timing of the sector pulse for the built-in control register and a select signal E8 for selecting any one of a plurality of time settings are given. ing.

FIG. 7 shows an embodiment of the sector mark detection circuit 96 shown in FIG. In FIG. 7, the peak detection pulse E3 is given to the sequence latch
The pulse sequence which is a time series of the peak detection pulse E3 over the sector mark reading period is latched. FIG. 8 shows details of the peak pattern comparison unit 104 of FIG. The peak pattern comparing unit 104 includes a comparing unit 134 and a reference sequence setting unit 136. The pulse sequence S0 to S17 latched for 18T from the preceding stage sequence latch circuit 102 is input to the comparing unit 134 in parallel. The reference sequence setting unit 136 stores the reference sequence “10” for 18T shown in the sector mark area 66 of FIG.
“000010000000100100” is set in advance. The comparison unit 134 compares the detection sequences S0 to S17 from the sequence latch circuit 102 with the reference sequence of the reference sequence setting unit 136 at the read end timing of the sector mark, and outputs a sector mark detection signal E10 when they match. The remaining peak pattern comparison units 106, 108, and 110 shown in FIG. 7 also have the same configuration as in FIG.
Even if any one of the read signals in one of the magnetic recordings "N, S, N, S" is lost, a reference sequence having redundancy is stored so that the read signal can be regarded as a sector mark and detected. ing.

FIG. 9A shows the peak pattern comparing section 10.
4 shows a reference sequence stored at 4, 106, 108, 110. The sector mark is 6T, as shown in FIG.
6T, 3T, and 3T are 18T in total. Here, in order to provide redundancy for the peak shift, for example, a pulse of 6T includes a change of ± 1T. This is the pattern C in FIG. 9A, which is in the range of 5T to 7T.

3T corresponds to 2T to 4T of the pattern B of 3T ± 1T shown in FIG. 9B. Further, pattern A is 1T, pattern D is 9T ± 1T, and pattern E is 12T ± 1T.
1T, pattern F means 14T or more. Therefore, the reference sequence shown in FIG. 9A is a combination of the redundant patterns shown in FIG. 9B. Referring to FIG. 7 again, the polarity signal E4 is supplied to the sequence latch circuit 112, and a pulse sequence of the polarity signal over 18T, which is the reading period of the sector mark, is latched as in the case of the peak detection. The output of the sequence latch circuit 112 is provided to polarity pattern comparison units 114, 116, 118, and 120. These polarity pattern comparison units 114, 116, 1
18 and 120 also include a comparison unit 134 and a reference sequence setting unit 136 similar to those shown in FIG.

Polar pattern comparing sections 114, 116, 11
Reference numerals 8 and 120 store a reference sequence having the polarity pattern shown in FIG. That is, 6T, 6T, 3
Four polarity patterns corresponding to T and 3T (+) (-)
(+) And (-) are stored as the reference sequence, and the remaining polarity pattern comparison units 116, 118, and 120 store the reference sequence of the polarity pattern corresponding to the missing peak pulse.

Peak pattern comparing sections 104, 106, 1
08, 110 and the polarity pattern comparing units 114, 116, 1
Outputs of the AND circuits 18 and 120 correspond to the corresponding AND circuits 1 respectively.
22, 124, 126, and 128. For example, to the AND circuit 122, a match signal from the peak pattern comparison unit 104 in which the reference sequence of the normal pulse is set and a match signal from the polarity pattern comparison unit 114 in which the reference sequence of the normal pulse is stored are input.

When the pulse sequence of both the peak detection pulse and the polarity signal matches the reference sequence, A
The ND circuit 122 outputs a sector mark detection signal,
The signal is output as a sector mark detection signal E5 via the circuit 132. The sector mark detection circuit of the present invention basically includes a peak pattern comparison unit 104, 114 and an AND circuit 122.
Only peak pattern comparison units 106, 108, 110, polarity pattern comparison units 116, 118, 120, and AND circuits 124, 126, 128 are provided to make the detection pattern redundant.

As shown in FIG. 10, the AND circuits 124, 126, and 128 serve as a reference for peak detection and polarity detection when the first, second, third, or fourth pulse of the normal pulse is missed. If the sequence matches, a sector mark detection signal is output. AN
The D circuits 122, 124, 126, 128 are controlled by a control register 130. The control register 130 is a 4-bit register. By setting an arbitrary 4-bit code from the MPU 24 shown in FIG.
All or any of 2, 124, 126, and 128 can be made valid.

In the present invention, when the first sector mark in which the head section 14 is moved to the target cylinder position and switched to the on-track control is detected, the control register 1
30 is set to “1000”, so that only the AND circuit 122 is valid. For this reason, the sector mark detection circuit E5 is output via the OR circuit 132 only when the detection sequence matches the reference sequence which is the peak pattern and the polarity pattern of the normal pulse shown in FIGS.

After the first detection of the sector mark is completed, the detection of the subsequent sector mark is performed in the control register 1.
30 is changed to “1111” by the MPU 24 and all A
The ND circuits 122, 124, 126, and 128 are made valid. Therefore, in the second and subsequent sector mark detection, a normal sector mark detection operation can be performed even if one of the read signals is missing.

FIG. 11 shows the operation of the peak detection circuit 90, the polarity detection circuit 92 and the synchronization circuit 94 of FIG. FIG. 11A shows a magnetization pattern of a sector mark in a specific cylinder, wherein a solid line indicates a magnetization state of the N pole and a broken line indicates a magnetization state of the S pole. When the sector mark shown in FIG. 11A is read by the read head 15, a read signal E0 shown in FIG. 11B is obtained. The peak detection circuit 90 is shown in FIG.
The peak timing of the read signal E0 shown in FIG. 11B is detected to output a peak detection pulse E1 shown in FIG. This peak detection process can be obtained, for example, by differentiating the read signal E0 and then detecting a zero cross.

The polarity signal shown in FIG. 11D is the read signal E0.
Are set to the positive and negative slice levels + Vs, -Vs,
When it exceeds + Vs, it is set to logic level 1, and -Vs
By resetting to logic level 0 when it falls below
The polarity signal E2 is output. FIG. 12 shows the synchronization circuit 9 of FIG.
4 shows the synchronization of the peak detection pulse and the polarity signal according to FIG.

FIG. 12A shows a reference clock having a period T, for example, 20 MHz. The peak detection pulse E1 shown in FIG. 12B and the polarity signal E2 shown in FIG. 12C are synchronized with the rise of the reference clock.
As a result, a synchronized peak detection pulse E3 shown in FIG. 12D and a synchronized polarity signal E4 shown in FIG. 12E can be obtained, and the intervals are 6T, 6T, 3T, and 3T. . 4. FIG. 13 shows an embodiment of a gray code detection circuit 98 provided in the servo demodulation circuit 54 of FIG. In FIG. 13, the gray code detection circuit 98 is provided with a status counter 138. The status counter 138 is constituted by a shift register, and can forcibly preset data from the preset terminal P by a control signal for the load terminal L.

The status counter 138 has six shift stages corresponding to the 1-bit width 6T of the gray code, and shifts the respective shift stages from state 0, state 1, state 2, state 3, state 4, and state 5 from the top. And Based on the peak detection pulse E3 and the polarity signal E4 of the first read signal from which the reading of the servo frame has started, the status counter 138 sets “1000000”.
Preset to.

This preset is stored in the preset register 14
This is done using a value of zero. The fact that both the peak detection pulse E3 and the polarity signal E4 are obtained is detected by the AND circuit 144, and the preset operation of the status counter 138 is performed by supplying the detection signal E11 to the load terminal L via the OR circuit 150. . At this time, the AND circuit 14
Since the output signal E11 from 4 is also supplied to the AND circuit 152, 6-bit data of the preset register 140 is supplied to the preset terminal P via the AND circuit 152 and the OR circuit 156.

Accordingly, the value “100000” of the preset register 140 is preset in the status counter 138 by the preset operation of the status counter 138 based on the first read signal. After the first preset, the status counter 138 performs a bit shift with the 1T reference clock CLK thereafter, and the output of the last shift stage in state 5 is fed back to the input stage in state 0 to form a so-called ring counter. Operate.

The presetting of 6-bit data from the preset register 140 to the status counter 138 is based on the peak detection and the polarity detection of the read signal having the positive polarity. On the other hand, when the peak detection pulse E3 and the polarity signal E4 for the negative read signal obtained 3T after the positive read signal are obtained, the “000” stored in the preset register 142 is stored.
"100" is preset in the status counter 138.

The detection of the peak detection pulse E3 and the polarity signal E4 of the read signal having the negative polarity is performed by the inverting circuit 148 and A
This is performed by the ND circuit 146, and the control signal E2 is supplied to the load terminal L via the OR circuit 150 to preset the value of the preset register 142. At this time, AND
The control signal E12 of the circuit 146 enables the AND circuit 154, and can supply 6-bit data of the preset register 142 to the preset terminal P via the OR circuit 156.

That is, when the status counter 138 obtains a 6T “100100” read signal corresponding to the bit 1 gray code, the state counter 138 sets the state 0 and the state 3
At this time, the counter value in each status state is forcibly preset. on the other hand,
“000” consisting of 6T of gray code corresponding to bit 0
000 ", the peak detection pulse E3
Neither the polarity signal E4 nor the polarity signal E4 is obtained, and the status counter 138 is put into a free-run state by the reference clock CLK according to the preset synchronization.

The restoration of bits 0 and 1 based on the gray code is basically performed by using the state 0 of the status counter 138.
This is performed using the signal E13 and the state 3 signal E14.
The state 0 signal E13 sets the latch circuit 160 via the AND circuit 158. The state 3 signal E1
4 sets the latch 164 via the AND circuit 162.

The other input of AND circuit 158 has AND
The output of the circuit 144 is provided, and when the peak detection pulse E3 and its polarity signal E4 are normally obtained from the read signal, the AND gate 158 is set to the allowable state, and the set operation of the latch circuit 160 by the state 0 signal E13 is allowed. . Similarly, the other input of the AND circuit 162
The output of the circuit 146 is provided, and when the peak detection pulse E3 of the read signal having a negative polarity and the polarity signal E4 thereof are effectively obtained, the setting of the latch circuit 164 by the state 3 signal E14 is permitted.

On the other hand, for the read signal of “000000” consisting of 6T of the gray code corresponding to bit 0, the output of the AND circuits 144 and 146 is at the logical level regardless of the timing of state 0 or state 3. 1 and the preset operation for the status counter 138 is not performed, and at the same time, the latch circuits 160 and 16
4 for state 0 signal E13 and state 3 signal E1
4 is also prohibited.

Therefore, when the read signal is normally obtained for the gray code "100100" corresponding to bit 1, the sequence "11" of status 0 and status 3 of status counter 138 is latched by latch circuits 160 and 164. You. On the other hand, for the read signal of the gray code “000000” of bit 0, the sequence “00” is stored in the latch circuits 160 and 164.

The latch outputs of the latch circuits 160 and 164 are supplied to the shift register 170 via the OR circuit 166 as a bit demodulated signal E18. Shift register 17
0 has a shift stage corresponding to a 14-bit gray code, shifts by inputting a bit demodulation signal E18 input in series, and shifts the demodulated signal to a 14-bit gray code G12 to GH at the gray code reading end timing. Is supplied to the MPU 24. The shift operation of the shift register 170 is performed by the state 5 signal E15 of the status counter 138. This state 5 signal E15 is inverted by the inverting circuit 168 and
0 and 164 are reset.

Further, in the gray code detection circuit 98 of the present invention, of the 6T pattern “100100” of the gray code indicating the bit 1, the first read signal corresponding to the state 0 or the fourth stage corresponding to the state 3 Bit 1 can be normally demodulated even if one of the read signals is lost. 6T gray code recording pattern “1”
When the first positive read signal is lost at “00100” and becomes “000100”, the status counter 1
38 is not performed by the preset register 140, and the latch circuit 1 by the state 0 signal E15
The latch operation of 60 is also prohibited.

However, since the negative read signal corresponding to the next fourth state 3 is normally obtained, the presetting of the state 3 state by the preset register 142 and the setting operation of the latch circuit 164 by the state 3 signal E14 are not performed. Normally done. In this case, the latch sequence of the latch circuits 160 and 164 becomes "01", and the bit demodulation signal E18 becomes bit 1 and can be demodulated normally.

On the other hand, if the positive read signal corresponding to state 0 can be demodulated but the negative read signal corresponding to the next state 3 is lost and becomes “100,000”, the preset register for the status counter 138 140
Is performed, and the latch circuit 160 is also in the state 0.
The latch operation can be normally performed by the signal E13. However, since the peak detection pulse E3 and the polarity signal E4 cannot be obtained correctly in the state 3, the preset operation by the preset register 142 and the setting operation of the latch circuit 164 by the state 3 signal E14 are not performed. In this case, the latch sequence of the latch circuits 160 and 164 becomes "10", and the bit demodulation signal E18 from the OR circuit 166 becomes the same bit 1 as in the normal state, and can be demodulated effectively.

FIG. 14 shows the peak detection circuit 90 shown in FIG.
4 shows a processing operation for a gray code read signal by the polarity detection circuit 92. FIG. 14A shows a gray code magnetization pattern, in which 6T has a 1-bit width.
If the bit is 1 in 3T units, a magnetization pattern of “100100” is recorded for the gray codes G12, G11, G10, G9, G8,. FIG.
4 (B) is the read signal E0, and a positive read waveform is obtained for the N-pole magnetization pattern shown by the solid line, and a read waveform having a negative polarity is obtained for the S-pole magnetization pattern shown by the broken line. .

FIGS. 14C and 14D show a peak detection pulse E1 and a polarity signal E2 of the gray code read signal E0, which are used as a reference in the next synchronization circuit 94 in the same manner as shown in FIG. Synchronization is performed by the clock CLK, and is input to the gray code detection circuit 98 shown in FIG. FIG. 15 shows the operation of the gray code detection circuit of FIG. 13 when a read signal of the magnetization pattern “100100” based on the bit 1 gray code is normally obtained. FIG.
(A) is a magnetization pattern of a gray code corresponding to bit 1, and “100100” is recorded for 6T. FIG. 1 synchronized from the read signal of this gray code
A peak detection pulse E3 shown in FIG. 5B and a polarity signal E4 shown in FIG.

The status counter 138 is supplied with the preset signal E11 of the state 0 shown in FIG. 15D at the timing of the state 0 when the peak detection pulse E3 and the polarity signal E4 rise to the logic level 1;
The status counter of "100000" is preset. Further, at the timing of the peak detection pulse E3 at which a negative read signal is obtained and the polarity signal E4, the signal shown in FIG.
The preset signal E12 of the state 3 shown in FIG.

FIG. 15 (F) shows the status status of the status counter by 0-5. From the status counter 138, a state 0 output E1 shown in FIG.
3, a state 3 output E14 shown in FIG. 15 (H) and a state 5 output E15 shown in FIG. 15 (I) are obtained. As shown in FIG. 15 (J), the latch circuit 160 latches the state 0 output signal E13 at the timing of state 0, and generates a latch output E16.

The latch circuit 164 generates a latch output E17 obtained by latching the state 3 output signal E14 at the state 3 timing, as shown in FIG. As a result, the bit demodulation signal E18 from the OR circuit 166 shown in FIG. 15 (L) becomes a logic level 1 at the timing of the state 3, and this is the state 5 output E15 of FIG.
For example, at the rise timing, the data is taken into the shift register 170.

FIG. 16 shows the gray code detection operation when the leading read signal of the 6T pattern "100100" of the gray code corresponding to bit 1 is missing. That is, as shown in FIG. 16B, the pulse 172 of the peak detection pulse E3 is generated due to the lack of the leading positive polarity read signal.
Corresponding to the polarity signal E shown in FIG.
14 also loses the signal 174 extending over states 0-2.

However, the status counter 138
Is operating normally, and the state 3 output E14 is latched by the latch circuit 164 at the timing of state 3 to become the logic level 1. Finally, the bit demodulation signal E18 is demodulated as bit 1 from the OR circuit 166, and even if the leading positive read signal is lost, gray code bit demodulation can be performed without any problem.

FIG. 17 shows a gray code detecting operation when a negative read signal corresponding to the state 3 of the 1T gray code 6T pattern "100100" is missing. In this case, of the peak detection pulse E3 in FIG. 17B, the pulse 176 corresponding to the state 3 is missing, and at the same time, the polarity signal E4 in FIG. 17C also has the logical level 0 corresponding to the negative read signal. Signal portion 178 is missing, and all become logic level 1.

However, the fact that the first read signal corresponding to the state 0 is normally obtained, the signal shown in FIG.
The output signal E16 of the latch circuit 160 of FIG.
Remains at logic level 0, the final OR circuit 1
The bit demodulated output by 66 can be correctly restored to bit 1.

FIG. 18 shows a gray code detecting operation when a phase shift occurs in a read signal due to a delay element of a circuit or the like. FIG. 18A shows a peak detection pulse E3 obtained from a read signal having undergone a phase shift, in which a pulse based on a negative read signal has a phase shift of leading and leading as shown in a pulse waveform 180. In response to this phase shift, the polarity signal E4 also has a detection waveform of a polarity corresponding to the phase shift as shown in FIG.

A peak detection pulse E3 and a polarity signal E4
With the phase shift shown in FIG.
As shown in (D), the preset signal E12 is output in the state 3 at the timing of the advance phase shift, and the status counter 138 is forcibly preset to "000100" to set the count state in the state 3. As a result, the status counter 138 counts “013450” and is preset to state 0 at the timing of the next peak detection and polarity detection.

Even in such a phase shift, since the signal states of state 0 and state 3 used for bit demodulation are the same as in the normal state, the output E1 of the latch circuit 160 is output.
6 is a logic level 1 at the timing of state 0, the output E17 of the latch circuit 164 is also a logic level 1 at the timing of the shifted state 3, and the bit demodulation signal E18 finally output from the OR circuit 166 is also a shifted state. The logic level becomes 1 at the timing of 3, and the bits can be demodulated normally even if there is a phase shift.

FIG. 19 shows a gray code detection operation when the negative read signal shifts in the delay direction, contrary to FIG. That is, as shown in FIG. 19A, a shifted pulse 182 is obtained by the phase shift of the negative read signal in the peak detection pulse E3 to the delay side, and the shifted pulse 182 is correspondingly obtained. The detection of the polarity of the polarity signal E4 is also shifted.

In this case, the status counter 138 counts “0123” as shown in the status of FIG.
Since it is preset to the count state of the state 3 of “0”, the status becomes the status 3 again, and the change until the status 0 is preset by the next read signal is “0123”.
345 ". This is because state 3 occurs only twice and is otherwise the same, so that bits can be normally demodulated even if there is a shift that causes a delay phase. 5. Real-time eccentricity correction For disk devices that use the sector servo method,
At every predetermined time, an eccentricity measurement is performed in which the deviation amount of each cylinder from the track center is measured in sector units and stored in a RAM or the like. Then, during normal on-track control, on-track control with eccentricity correction for always positioning the head at the track center is performed by subtracting the previously measured eccentricity deviation value from the target position.

However, since the deviation value used for the eccentricity correction was measured at predetermined time intervals, the eccentricity correction was performed between the measurements with the previous measured value, and the amount of eccentricity due to the temperature change was measured. There was a problem that could not cope with the fluctuation of Therefore, in the disk device of the present invention,
The eccentricity deviation value is measured in the first rotation of the cylinder during on-track and stored in the RAM, and from the next rotation, on-track control with eccentricity correction using the deviation value measured last time is performed in almost real time. To make eccentricity correction possible.

FIG. 20 shows an embodiment of a disk drive according to the present invention for realizing eccentricity correction real-time processing.
4 is realized as a function by program control. FIG.
0, the MPU 24 is provided with a head positioning control unit 184 for controlling the head to follow the track center during on-track. This head positioning controller 18
4 is a head position detecting unit 185, a target position setting unit 18
6. It is composed of the addition points 188 and 190 of the position servo and the current instruction unit 192. The target position setting section 186 outputs a target position Po indicating the track center at which the head is positioned during on-track.

The target position Po is given to the addition point 188,
The deviation value with respect to the track center obtained in the previous eccentricity measurement, that is, the eccentricity correction value (Xn) _t-1 which is read out at that time, is subtracted from the register 196 and the corrected target position Po '
Is output. The addition point 190 is the corrected target position Po '
Then, the position error ΔP is obtained by subtracting the head position Pn detected by the head position detector 185 at that time.

The position error ΔP obtained at the addition point 190 is given to the current indicating unit 192, and the current indicating data including the current direction indicated by the polarity of the position error ΔP and the current value indicated by the absolute value is output to the DA converter 38. Then, a current is supplied to the VCM 20 by the driver 40 shown in FIG. 2 to drive the head, and the head is controlled so that the positional error ΔP becomes zero.

Here, the head position detecting section 185 converts the detection signal of the servo area peak-held by the peak hold circuit 54 shown in FIG. 2 into a digital signal by the AD converter 55 and fetches the servo information. For example, as shown in FIG. 5A, since the servo is a two-phase servo recorded with the first to fourth fields A, B, C, and D, as shown in FIGS. , The head position Pn at that time is detected.

The external RAM is provided with a RAM correction table 194 for storing the correction value Xn obtained by the eccentricity measurement in sector units of each cylinder. The RAM correction table 194 has, for example, a sector number 0 as shown in FIG.
The correction values X0 to X59 measured for each area are stored with the addresses of .about.59 as addresses. Of course, the RAM shown in FIG.
The contents of the correction table are created for each cylinder.

The MPU 24 is provided with a RAM access unit 195, which reads out the eccentricity correction value Xn (where n = 0 to 59) stored in the RAM correction table 194 based on the cylinder address and sector number at that time. It is set in the register 196 and used for correcting the target position Po at the addition point 188. Further, a correction value updating unit 198 is provided, and adds the currently measured head position Pn to the previous eccentricity correction value (Xn) _t-1 read out to the register 196 to obtain a new eccentricity correction value (Xn) _t . Then, it is stored in the RAM correction table 194 at the address of the corresponding sector number by the RAM access unit 195, and the eccentricity correction value is updated to a new measurement result.

FIG. 22 shows the relationship between the track center and the head position before and after the correction by the real-time eccentricity correction of the present invention. FIG. 22A shows the head trajectory 202 with respect to the track center 200 at a certain sampling point in the first rotation of the cylinder after on-track. That is, the track center 200 gently undulates due to eccentricity, whereas the head trajectory 202 is shown as a straight trajectory because it has a certain constant value. At the time of on-track, the track center 200 is at the target position Po.

Here, the first sampling time is defined as t1
Then, the previous sampling time is t0, but since this is the first eccentricity correction, the contents of the corresponding sector of the RAM correction table 194 are 0, and the register 1
The previous eccentricity correction value (Xn) _t0 of 96 is 0.
Therefore, the addition point 188 outputs the target position Po itself to the addition point 190 as the corrected target position Po ′. At the addition point 190, the position error ΔP is obtained by subtracting the detected head position Pn from the target position Po. The current instruction unit 192 outputs current instruction data based on the position error ΔP = −Pn to the DA converter 38, and performs head positioning control so that the position error ΔP becomes zero.

At the same time, the correction value updating unit 198
The head position Pn is added to the 96 previous eccentricity correction value (Xn) _t0 to obtain a new eccentricity correction value (Xn) _t1 . At this time, since the previous eccentricity correction value (X0) _t0 is 0,
The detected head position Pn itself is set as a new eccentricity correction value (Xn) _t1 by the RAM access unit 195 and the RAM.
It is stored at the address of the corresponding sector in the correction table 194.

FIG. 22B shows head positioning control at the same sampling point in the second rotation of the cylinder. For the second time, FIG.
The previous eccentricity correction value (Xn) _t0 obtained in the first eccentricity measurement of 2 (A) is read. Therefore, the addition point 1
The position error ΔP obtained by 88 and 190 is obtained as ΔP = P0− (Xn) _t0 −Pn, where Pn is the head position detected at that time, and the detection error ΔP
Is output to the DA converter 38 to perform head positioning control. In the case of FIG. 22B, the error of the head trajectory 204 with respect to the eccentrically corrected target position Po 'is 0, and as a result, the head positioning by the eccentricity correction of only the previous eccentricity correction value (Xn) _t1 is performed. It is in a state.

Of course, if a head position shift occurs in the state shown in FIG. 22B and a head position Pn that deviates from the corrected target position Po 'is obtained, positioning control based on the position error .DELTA.P added thereto is performed. . At the same time, a new eccentricity correction value (Xn) _t2 obtained by adding the newly generated head position Pn to the previous eccentricity correction value (Xn) _t1 is obtained, and the contents of the corresponding sector in the RAM correction table 194 are updated. .

FIG. 23 is a flow chart showing the operation of the head positioning controller 18 shown in FIG.
4 shows the processing operation of FIG. In FIG. 23, when the control is switched to the on-track control upon completion of the seek control, first, in step S1, the correction values (X0) of all the sectors included in the on-track cylinder in the RAM correction table 194 are determined.
Clear the contents of ~ (Xn-1). Then, step S2
Then, the sector counter n is initialized. After the initialization, in step S3, it is checked whether it is the sampling timing of the head position detection signal in each servo frame.

When the sampling timing for detecting the head position is determined, the process proceeds to step S4, where the detected head position Pn is fetched. Subsequently, in step S5, the previous eccentricity correction value (Xn) _t-1 is read from the RAM correction table 194 from the address specified by the sector counter n.
For the first rotation of the cylinder after the on-track, the previous correction value (Xn) _t-1 is 0.

Then, the process proceeds to a step S6, wherein the target position P0 is set.
, The position error is obtained using the previous correction value (Xn) _t-1 and the detected head position Pn. Then step S
In step 7, the current instruction value Id based on the position error ΔP is output to the DA converter 38, and head positioning control is performed by driving the VCM. Subsequently, in step S8, the head position Pn currently detected at the previous eccentricity correction value (Xn) _t-1
And the new eccentricity correction value (Xn) _t measured this time.
Is obtained and stored in the corresponding sector of the RAM correction table 194 in step S9 to update the eccentricity correction value.

In step S10, it is checked whether or not the sector counter n has reached the maximum sector. Until the sector reaches the maximum sector, the processing of steps S3 to S9 is repeated for each sector. If it is the maximum sector, the process returns to step S2, and the same processing is repeated from the initialization of the sector counter n. In the processing of FIG.
As the new eccentricity correction value (Xn) _t used for updating the correction table 194, the head position Pn detected at the present time is added to the previous eccentricity correction value (Xn) _t-1 as it is, but the head position Pn remains unchanged. If the update is added, disturbance components other than the steady eccentricity factor will also be added.
It is desirable to limit the head position Pn as follows.

The first method is a method in which the head position Pn is multiplied by a coefficient K having a value of 1 or less, weighted, and added. The second method is a method in which the average value of the detected head positions is obtained by combining the head positions obtained in the adjacent sectors and added. A third method is
In this method, a limit value is set for the head position to be added, and if a head position Pn exceeding the limit value is obtained, the limit value is added.

As described above, by limiting the head position,
By obtaining a new eccentricity correction value in addition to the previous eccentricity correction value, it is possible to prevent the temporary eccentricity due to disturbance from being taken into the eccentricity correction value. In the process of FIG. 23, the process is started after all the contents of the RAM correction table 194 are first cleared at the time of on-track in step S1, but this initial clear is not performed, and the previous on-track is not performed. The eccentricity correction value measured at the end of the time may be used for the first time to perform the positioning correction. As a matter of course, if the correction operation is performed by reading the correction value of the current sector, the correction is performed for the sector that has already been shifted, which causes a delay, and the correction operation is not performed normally. Therefore, the reading of the eccentricity correction value from the RAM correction table 194 by the RAM access unit 195 in FIG. 20 is performed by reading a sector that is several sectors ahead of the current sector. This takes into account the delay in the correction operation. 6. Variable control of sector size In a disk drive that employs the sector servo method,
Servo frames are fixedly formatted at fixed intervals on the cylinder, and basically the sector size is fixedly determined by the servo frame intervals. That is, a sector pulse is generated in synchronization with the detection of the end of the sector mark.

However, in the case of a fixed sector size, various problems such as a fixed size of a data block to be read / written occur. Therefore, it is necessary to change the sector size, and thus it depends on a physical servo frame. Therefore, it is necessary to generate a sector pulse for determining the sector size at an arbitrary timing as needed.
The disk drive of the present invention has a function of generating a sector pulse that enables the sector size to be varied by simple firmware.

FIG. 24 shows an embodiment of the disk device of the present invention for realizing a variable sector size. In FIG. 24, the MPU 24 has three control registers 216, 21
8, 220 are provided. Control registers 216, 2
18 and 220, time data for determining a position where a next sector pulse is generated starting from, for example, the end of a certain servo frame is stored. Control registers 216, 218, 2
Any one of the outputs 20 is selected by the select circuit 222 and applied to the match detection circuit 224.

On the other hand, the count result of the counter 214 is input to the coincidence detection circuit 224. Counter 21
4 is reset by the MPU 24 based on the detection of the end of the servo frame, and from that point on, the reference clock CLK
Start counting. The coincidence detection circuit 224 controls the control registers 216, 218, and 22 selected by the selection circuit 222.
0 time data, specifically, the reference clock C
The time data defined by the number of LKs and the count value of the counter 214 are compared.

When the counter count value matches the register set time, the match detection circuit 224 outputs a match output to the pulse generation circuit 226 to generate a sector pulse.
The pulse width of the sector pulse may be fixed, or M
The management may be performed under the control of the PU 24. FIG. 25 shows the generation of a sector pulse for achieving a variable sector size according to the embodiment of FIG. In the reading process of the servo frame 246 shown in FIG. 25A, when it is desired to generate the sector pulses 250 and 252 following the servo frame 246 as shown in FIG. Calculate time T1, T2 to the position of each sector pulse 250, 252,
Time data T1, T are stored in control registers 216 and 218.
Set 2

When the time data T1 and T2 have been set, the MPU 24 operates the register 2 by the select circuit 222.
16 to select the time data T1 and the match detection circuit 22.
Set to 4. The counter 214 is reset when the reading of the servo frame 246 is completed, for example, and the reference clock CL is reset.
When the counting of K is started and the count value of the counter 214 matches the time data T1, the pulse generation circuit 2
26 generates a sector pulse 250.

When the generation of the sector pulse 250 is completed, MP
U24 is supplied to the next register 218 by the selection circuit 222.
And sets the time data T2 in the coincidence detection circuit 224. For this reason, the coincidence detection circuit 224
When the value of 4 coincides with the time data T2, a coincidence output is generated, and the pulse generation circuit 226 outputs a sector pulse 252.

FIG. 26 shows the control of the generation of sector pulses when a data split occurs in which a data block is divided into two areas by a servo frame, using the control of the variable sector size of the present invention. FIG. 26A shows a cylinder recording state. If the write block data exceeds the fixed sector size determined by the servo frame interval, the data is divided into data 232 and 236 with the fixed sector size, and the data 232 is recorded following the servo frame 228 and the ID 230 and the next servo The remaining split data 236 is recorded after the frame 234. After the split data 236 is the next sector, and the ID 238 and the data 240 are stored.

In such a case, as shown in FIG. 26B, the sector pulse 24 immediately follows the servo frame 228.
2 and the next sector pulse is the servo frame 234
Not immediately after the end of the split data 236, the sector pulse 244 must be generated. In order to generate such a sector pulse, the time data T1 for the first register 216 shown in FIGS. 26A and 26B is T1 = 0, and the time data T1 for generating the next sector pulse is used. T2 is time data obtained by adding the gap interval to the data 236, and this time data T2 is stored in the control register 2 for the servo frame 234.
Set to 16.

The control register 216 for the time data T1
At the end of reading of the servo frame 228, the counter 214 is reset and the reference clock CLK
When the coincidence detection circuit 224 generates a coincidence output by selecting the time data T1 by the selection circuit 222, the pulse generation circuit 226 outputs the first sector pulse 242.

Subsequently, the control register 21 for the time data T2
6, the count 214 is reset at the end of reading the servo frame 234, and the reference clock CL
When the counting operation of K is started, when the coincidence detection circuit 224 generates a coincidence output by the selection of the time data T2 by the selection circuit 222, the sector pulse 244 is output from the pulse generation circuit 226.

FIG. 26C shows a read gate, in which the gate is inhibited during the periods of the servo frames 228 and 234, and the ID and data can be read during the other gate valid periods. FIG.
Reference numeral 7 denotes a process of generating a sector pulse for a sector slip process for a bad sector. When a defective sector due to a medium defect is detected on the cylinder, a continuous read operation or a write operation can be performed without considering the defective sector by not generating a sector pulse for the defective sector.

Therefore, in the MPU 24 shown in FIG. 24, when the on-track control is performed upon completion of the seek of the designated cylinder address, the MPU 24 refers to the management table of the defective sector prepared in advance, and determines the defective sector. At the timing of the indicated sector number, for example, as shown in the control register 220, time data for preventing a sector pulse from being generated in a defective sector is set.

In the embodiment shown in FIG.
Is set to the register maximum value "FFFF". The set time “FFFF” is time data exceeding the sector size determined by the servo frame. Therefore, the time data “FFF” of the register 220 is
Even if “F” is selected and set in the coincidence detection circuit 224, the counter 214 reset at the end of the reading of the servo frame.
Does not coincide with the time data “FFFF” during the defective sector, and the generation of the sector pulse is prohibited because no coincidence detection output is obtained for the defective sector.

FIG. 27A shows the reading of a servo frame, in which a defective sector 254 exists at a specific position.
For such a defective sector 254, time data “FFFF” for inhibiting generation of a sector pulse is set in accordance with the sector number. As a result, generation of a sector pulse in the defective sector 254 can be prohibited as shown in FIG.

If a sector pulse does not occur in the defective sector 254, the read gate is reset by the first sector mark of the servo frame as shown in FIG. 27C, and becomes a gate signal set by the generation of the sector pulse. The read operation can be performed without being aware of the bad sector 254. The same applies to the write operation. As a result, bad sector 2
When 54 exists, it is unnecessary to perform a replacement process for reading and writing data by moving to a replacement area which has been conventionally performed,
Access performance can be greatly improved. FIG. 27C shows a read gate, but the same applies to a write gate.

FIG. 28 shows a process of generating a sector pulse in a digital error test. In a digital error test of a disk medium, a sector pulse must be generated once immediately after a servo frame.
Therefore, in the embodiment of FIG. 24, when the MPU 24 receives the control command of the digital error test, the MPU 24 causes the control register 216 to generate a sector pulse immediately after the completion of the reading of the servo frame.
Set 0.

The select circuit 222 fixedly selects the value of the register 216 and outputs it to the coincidence detecting circuit 224. In such a set state, when the MPU 24 resets the counter 214 every time the reading of the servo frame is completed and repeats the counting operation, the coincidence detecting circuit 224 generates a coincidence output at the first reset timing, and at the end of the reading of the servo frame. Synchronously, the pulse generation circuit 226 generates a sector pulse each time.

Therefore, when a digital error test is performed on the servo frame shown in FIG.
Sector pulses are generated in a one-to-one correspondence as shown in FIG.
A digital error / write test signal over the entire sector section between servo frames shown in FIG.
The test gate can be set based on the digital error read test signal (D). By such a digital error test, an error test can be performed on all areas except for the servo frame, and it is possible to appropriately cope with the variable setting of the sector size in normal read / write after completion.

FIG. 29 is a flow chart showing a data split process, a slip process of a defective sector, and a process of generating a sector pulse including a digital error test. In FIG. 29, first, in step S1, a sector number is read by reading a servo frame, and in step S2
Then, it is checked whether generation of a sector pulse is necessary. If it is necessary to generate a sector pulse, the process proceeds to step S3,
Check whether or not the digital error test mode is set.

At the time of initial diagnosis upon power-on of the disk device, the digital error test mode has been set, so the flow advances to step S4 to store the time in the digital error test mode in the sector pulse generation register. Data is set, and a sector pulse as shown in FIG. 28 is generated for each servo frame. In the normal state after the start-up upon power-on, since the digital error test mode has been released, the process proceeds from step S3 to S5. Here, if the data block requested to be read or written from the host device exceeds the sector size determined by the servo frame, position data (time data) indicating the sector size occurrence position is set to obtain a variable sector size. One or more are set in the register.

Subsequently, in step S6, it is checked whether or not there is a sector slip with respect to the defective sector. If there is no sector slip, a sector pulse is generated based on the data set in step S5. Step S
If there is a defective sector that requires a sector slip in step 6, the process proceeds to step S7, where position data that does not generate a sector pulse during reading processing of a servo frame in which the sector number to be slipped is obtained, for example, a register The time data having the maximum value is set in a register for generating a sector pulse, and generation of a sector pulse in a defective sector is inhibited to perform a sector slip.

By variably controlling the generation of such a sector pulse, a sector pulse can be generated at an arbitrary position, which is particularly effective in a disk device employing a constant density recording system (CDR system). In addition, by performing a sector slip process that inhibits generation of a sector pulse for a bad sector, a write operation or a read operation can be performed without being aware of the bad sector. Access performance can be improved.

Further, in the digital error test at the time of initialization and startup, by generating a fixed sector pulse immediately after the end of the servo frame, it is possible to eliminate the gap between the servo frames as a non-test portion without causing a gap. Digital write error test and digital read error test of the entire area can be realized, and it is possible to appropriately cope with the variable setting of the sector size performed in the normal read / write operation.

In the embodiment shown in FIG. 24, the generation time of the sector pulse is determined based on the detection of the end of the servo frame. However, the generation of the sector pulse is performed based on an arbitrary position in the servo frame such as the detection time of the sector mark. You may decide the time. In the above embodiment, a disk device using one disk medium is taken as an example. However, the number of disk media can be increased as needed.

Further, the present invention provides both a constant density recording method (CDR method) in which the clock frequency is varied for each zone divided in the radial direction and a constant angular velocity recording method (CVR) in which the clock frequency is constant for all cylinders. , Can be applied as is. Furthermore, the present invention is not limited by numerical values according to the embodiments.

[0145]

As described above, according to the present invention, a short recording length can be obtained by combining both the peak detection and the polarity detection of the read signal with the detection of the sector mark and the gray code recorded in the servo frame. Thus, the sector mark and the gray code can be reliably detected. For this reason, the recording length in the servo frame can be reduced without lowering the detection rate, and the format efficiency in the sector servo method can be increased to increase the storage capacity of the disk medium.

Further, by performing the eccentricity correction using the sector servo in the on-track control in real time, the accuracy of the tracking control can be greatly improved even if there is a temperature fluctuation, and an on-track error occurs even if the track recording density is increased. The read or write operation can be ensured without any problem. Furthermore, a sector pulse can be generated so as to have an arbitrary sector length without being restricted by generation of a fixed sector pulse determined by a servo frame, split recording for dividing and reading / writing block data, and slip processing for skipping a bad sector. For example, a variable generation of a sector pulse can be easily performed at an arbitrary timing as needed, such as generation of a fixed sector pulse synchronized with a servo frame at the time of a digital error test at the time of initialization.

As described above, according to the present invention, useless processing is reduced as much as possible, and processing necessary for improving accuracy is focused on, so that substantial processing efficiency can be improved and a small disk drive can be used. Enable application.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing the overall configuration of the present invention.

FIG. 3 is an explanatory diagram of a format of a servo frame according to the present invention.

FIG. 4 is an explanatory diagram of a read signal of the servo frame of FIG. 3;

FIG. 5 is an explanatory diagram showing a recording state of a servo area in FIG. 3 and detection of a head position signal.

FIG. 6 is a block diagram showing an embodiment of the servo demodulation circuit of FIG. 2;

FIG. 7 is a block diagram showing an embodiment of the sector mark detection circuit of FIG. 6;

FIG. 8 is a block diagram showing an embodiment of a peak pattern comparison unit in FIG. 7;

FIG. 9 is an explanatory diagram showing a pattern of a reference sequence set in a peak pattern comparing unit in FIG. 6;

FIG. 10 is an explanatory diagram showing a pattern of a reference sequence set in a polarity pattern comparing unit in FIG. 6;

11 is a timing chart showing a peak detection pulse and a polarity signal detected from the sector mark read signal in FIG.

12 is a timing chart showing synchronization of a peak detection pulse and a polarity signal with respect to a sector mark read signal in FIG.

FIG. 13 is a block diagram showing an embodiment of the gray code detection circuit of FIG. 6;

14 is a timing chart of a peak detection pulse and a polarity signal detected from a gray code read signal in the embodiment of FIG.

FIG. 15 is a timing chart showing gray code detection during normal reading.

FIG. 16 is a timing chart showing gray code detection when a read signal is missing in state 0;

FIG. 17 is a timing chart showing gray code detection when a read signal is missing in state 3;

FIG. 18 is a timing chart showing gray code detection when a phase shift occurs in a read signal;

FIG. 19 is a timing chart showing gray code detection when a delayed phase shift occurs in a read signal.

FIG. 20 is a block diagram showing an embodiment of the present invention for measuring and correcting eccentricity in real time during on-track.

FIG. 21 is an explanatory diagram of a RAM correction table storing eccentricity correction values.

FIG. 22 is an explanatory diagram showing a state of real-time eccentricity measurement and correction for a head locus and a track center.

FIG. 23 is a flowchart showing the eccentricity measurement and correction processing of FIG. 20;

FIG. 24 is a block diagram showing an embodiment of the present invention for generating a sector pulse so as to have a variable sector size.

FIG. 25 is an explanatory diagram of generation control of a sector pulse according to FIG. 24;

FIG. 26 is a timing chart showing generation of a sector pulse for data splitting;

FIG. 27 is a timing chart showing generation of a sector pulse used for a slip process of a bad sector.

FIG. 28 is a timing chart showing generation of a sector pulse during a digital error test.

FIG. 29 is a flowchart showing a process of generating a sector pulse shown in FIG. 24;

[Explanation of symbols]

10: Disk enclosure 12: Drive controller 14: Head unit 15: Read head 16: Write head 18: Head IC circuit 20: Voice coil motor (VCM) 22: Spindle motor 24: MPU 26: EPROM 28: DRRM 30: Interface circuit 31: Cache Controller 32: Buffer Memory 33: Cache Memory 34: PWM Circuit 36, 40: Driver 38: DA Converter 42: AGC Amplifier 44: Equalizer Circuit 46: Maximum Likelihood Circuit 48: VFO Circuit 50: Encoder / Decoder 52: Hard Disk Controller 54: Peak hold circuit 55: AD converter 56: Servo frame demodulation circuit 58: MPU bus 60-0 to 60-59: Servo frame 62-0 to 62-59: Data Data frame 64: R / W recovery area 66: sector mark area 68: gray code area 70: index area 72: AGC area 74: servo area 76: first field (A) 78: second field (B) 80: second 3 field (C) 82: Fourth field (D) 84: Gap area (pad area) 86, 88: Dummy area 90: Peak detection circuit 92: Polarity detection circuit 94: Synchronization circuit 96: Sector mark detection circuit 98: Gray code detection circuit 100: sector pulse generation circuit 102, 112: sequence latch circuit 104, 106, 108, 110: peak pattern comparison section 114, 116, 118, 120: polarity pattern comparison section 122, 124, 126, 128, 144 , 146,1
52, 154, 158, 162: AND circuit 130: Control register 138: Status counter 140, 142: Preset register 148, 168: Inverting circuit 150, 156, 166: OR circuit 160: 164: Latch circuit 170: Shift register 184: Head positioning control unit 185: Head position detection unit 186: Target position setting unit 188, 190: Addition point 192: Current instruction unit 194: RAM correction table 196: Register 198: Correction value update unit 214: Counter 216, 218, 220: Control register 222: select circuit 224: match detection circuit 226: pulse generation circuit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Eisaku Takahashi 5400-2 Omori, Higashinemoto, Higashine, Higashine-shi, Yamagata (No address) Inside Yamagata Fujitsu Co., Ltd. (72) Inventor Takashi Tokaibayashi, Higashinemoto, Higashine-shi, Yamagata 5400-2 Higashi Omori (without address) Inside Yamagata Fujitsu Co., Ltd. (72) Inventor Isao Suda 5400-2 Higashi Omoto, Higashi-nemoto, Higashine, Higashi-shi, Yamagata (No address) Inside Yamagata Fujitsu Co., Ltd. (72) Inventor Okamura Eiji 1015 Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Tatsuya Gofuku 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Tomohiro Ono Higashi Nemoto, Higashine-shi, Yamagata Prefecture 5400-2 Higashi-ji Omori (No address) Inside Yamagata Fujitsu Co., Ltd. (58) Field surveyed (Int.Cl. ⁷ , DB name) ) G11B 5/09

Claims (9)

(57) [Claims] A sector area having a servo area and a data area is provided on the same cylinder, and a sector mark indicating a servo area is provided in the servo area.
6) Gray code code indicating cylinder address
A disk medium on which a code (68) and a predetermined servo pattern (74) for detecting a head position are magnetically recorded; and the servo pattern (74) by head means (14).
A disk control means (24) for detecting the head position based on the read signal of the head, positioning the head means (14) at an arbitrary cylinder, and reading / writing the data; and the sector mark (14) read by the head means (14). 66) means for detecting a peak of the read signal of (66) to detect a time interval of the peak; and a polarity signal for detecting the polarity of the read signal of the sector mark (66) read by the head means (14). The sector mark (66) is detected based on a polarity detection means (92) for outputting the sector mark (66) based on a peak detection pulse of the peak detection means (90) and a polarity signal of the polarity detection means (92). And a sector mark detection means (96) for notifying the control means (24). 2. The disk apparatus according to claim 1, wherein said sector mark detecting means includes a peak sequence which is a time series of said peak detection pulses over a reading period of said sector mark, and said sector mark. Comparing the peak reference sequence based on the magnetic recording of
A peak comparison means (104) for outputting a peak coincidence signal when both coincide with each other; and a polarity sequence based on a magnetic recording pattern of the sector mark, which is a time sequence of the polarity signal over a reading period of the sector mark. A polarity comparing means (114) for comparing with a reference sequence and outputting a polarity matching signal when they match, a peak comparing means (104) and a polarity comparing means (11)
4) A disk device comprising: gate means (122) for outputting the sector mark detection signal when both of the coincidence signals are obtained. 3. The disk drive according to claim 2, wherein said sector mark detecting means (96) is one of a read sequence signal corresponding to magnetic recording of a sector mark and a read signal of magnetic recording of said sector mark. For each of the read sequence signals for which one of them is missing, the peak comparing means (10
4, 106, 108, 110) and the polarity comparing means (11
4, 116, 118, 120) and gate means (12
2, 124, 126, 128), and outputs a detection signal of a sector mark based on a coincidence signal of any one of the gate means (122, 124, 126, 128). 4. The disk drive according to claim 3, wherein said gate means (122, 124, 126, 12)
8) A disk device provided with control register means (130) for selectively enabling the above (8) by said disk control means (24). 5. A disk drive according to claim 4, wherein said disk control means (24) detects the first sector mark after positioning in a specific cylinder coincides with the magnetic recording of said sector mark. The control register means (130) is set to enable the gate means (104) for outputting a coincidence signal based on the read sequence signal, and
Regarding the detection of the sector mark after the first time, the control register means (130) makes the other gate means (124, 126, 128) for outputting a coincidence signal effective even if the read sequence signal is missing. A disk device characterized by setting: 6. A disk drive according to claim 1, further comprising a peak detection pulse of said code code by said peak detection means (90) and a polarity signal of said code code by said polarity detection means (92). A disk address detecting means (98) for detecting the code code, discriminating the cylinder address and notifying the disc control means (24) based on the code code. 7. A disk drive according to claim 6, wherein said cylinder address detection means (98) repeatedly counts a state state based on a recording bit length (N) of said code code at a reference period (T). Status counter means (138); and when the status counter means (1) detects both the peak detection pulse of the read signal of the positive polarity and the polarity signal thereof,
A first preset means (140) for presetting the status counter means (38) to a first state state; and detecting the status counter means (1) when detecting both a peak detection pulse of a negative polarity read signal and a polarity signal thereof.
(38) a second preset state (142), a detection output when both the peak detection pulse of the positive polarity read signal and its polarity signal are obtained, or the status counter means (138). ), A first latch means (160) for latching the output of the first state state, a detection output when both the peak detection pulse of the negative polarity read signal and its polarity signal are obtained, or the status counter means ( 138) second latch means (164) for latching the output of the second state state, and the first and second latch means (160, 164) at the output timing of the final state state of the state counter means (138). And a gate means (166) for restoring the address bit by taking the logical sum of 8. The status counter according to claim 7, wherein a gray code of (X00X00...) Is magnetically recorded in the servo frame of the disk medium as the code code at a cycle of nT. The means (138) repeatedly counts the counts 0 to n indicating the n state states in the reference cycle (T), and the first preset means (140) calculates the peak detection pulse of the read signal of the positive polarity and the polarity thereof. When both of the signals are detected, the status counter means (138) is preset to a state of state count 0, and the second preset means (142) sets both the peak detection pulse of the negative polarity read signal and the polarity signal thereof. when it is detected, that preset the status counter means (138) to the state of the state count (n / 2) Disk apparatus according to claim. 9. A disk drive according to claim 8, wherein said magnetic recording of the gray code on said disk medium is performed by means of said status counter means (1) every predetermined code length.
38) A disk device wherein a dummy code for forcibly performing the preset of 38) is inserted.