JP3320353B2 - Variable speed phase locked loop system and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to semiconductor devices, and more particularly to a phase locked loop.

[0002]

BACKGROUND OF THE INVENTION Phase locked loops (PLLs) are used for a wide variety of applications in semiconductor devices. For example, PLL
Are used for clock oscillators, frequency multipliers, frequency synthesizers and servo systems for disk drives. Of course, in these and all other applications the PLL
Accuracy and reliability are very important.

Referring to FIG. FIG. 1 is a schematic diagram of a prior art phase locked loop 100. PLL1
00 is a phase detector 102, a charge pump 104,
It includes a filter 106, a voltage controlled oscillator (VCO) 110 and a feedback divider 114.

Since the general operation of a PLL is well known,
Just a brief explanation. Phase detector 102 compares the input signal with the feedback signal from feedback divider 114. The phase detector operates according to the phase difference between the input signal and the feedback signal.
4 is driven. The output of charge pump 104 is filtered by filter 106 and used to drive VCO 110. The VCO 110 has a voltage / current (Vt
oI) including a converter and a current controlled oscillator (ICO). This causes VCO 110 to receive the voltage at its input and output a signal at a frequency proportional to this signal. As those skilled in the art will appreciate, this description of VCO 110 is for purposes of illustration, and VCO 110 may be a separate voltage-to-current converter and current-controlled oscillator rather than a single element.

The output of the VCO 110 is fed back to the phase detector 102 via a feedback divider 114. Feedback divider 114 divides the frequency of the output signal to match the frequency of the input signal and allows the phases of both signals to be compared. Thus, the signal path through the feedback divider to the phase detector 102 creates feedback that facilitates operation of the phase locked loop.

[0006] Some applications of PLLs require that the output frequency of the PLL be able to be switched during operation. The frequency at which phase locked loop 100 operates depends on the frequency of VCO 110 and the value of the division by feedback divider 114. To change the output frequency, one or both of these two factors may be adjusted. However, adjusting these factors while the PLL is operating will leave the phase unlocked until the PLL is locked again. In applications where phase lock must be maintained during switching, this locking delay is unacceptable.

[0007] Therefore, there is a need to provide an improved PLL that can switch from one output frequency to another without interrupting phase lock.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a phase locked loop system which overcomes the limitations of the prior art by providing the ability to switch output frequencies without interrupting phase locking of the output signal. To provide.

[0009]

The system includes a first phase locked loop coupled to a second phase locked loop such that the output signals of each other are in phase, and the output of the first phase locked loop. A switching mechanism is used to switch between the signal and the second phase locked loop output signal.
This system can switch the output frequency without breaking the signal phase lock.

[0010] The other features and advantages of the present invention include:
The following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings, will be apparent from the following description.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred exemplary embodiments of the present invention will be described below with reference to the accompanying drawings. The same elements are denoted by the same symbols.

Many conventional semiconductor devices, such as microprocessors, are designed to operate under a wide range of operating conditions. For example, the CPU of a personal computer
Common microprocessors used as
It is designed to operate at temperatures below freezing to well above about 40 ° C (100 ° F). To ensure proper operation under these extreme conditions, semiconductor devices are typically configured to operate at speeds well below the maximum speed under normal conditions. This allows the device to continue operating within an acceptable range even if the temperature rises or falls to the extreme of the operating range.

Although such an arrangement works, it is less than ideal. The reality is that many devices operate only in the mid-range of the specified operating temperature range (ie, temperature controlled offices). Thus, these devices should be able to operate effectively most of the time, much faster than configured goals. However, this may render the device inoperable if conditions change significantly.

[0014] One solution to this problem is to dynamically adjust the speed of the semiconductor device to changing conditions. For example, it is possible to design a microprocessor such that it operates at a speed close to the maximum speed under room temperature conditions, and automatically switches to a low operating speed when the temperature changes. Is the device approaching its maximum operating speed?
An apparatus and method for determining whether there is enough room to increase speed is described in "Self-Timed Circuit Having Critical," filed August 8, 1996 and assigned to International Business Machines Corporation.
Ferraiolo et al., Co-pending U.S. Patent Application Ser. No. 08/6, entitled "Path Timing Detection."
No. 94120. This solution operates at high speed under ideal conditions and does not sacrifice reliability under extreme conditions.

One problem in switching operating speeds is that
Conventionally, on-the-fly switching cannot be performed without interrupting the operation of the device. For example, a semiconductor device that uses a phase locked loop as a clock oscillator cannot switch speeds without losing the phase lock of the clock system. Therefore, every time the operating speed is changed, it is absolutely necessary to shut down and restart the device.

A variable speed phase locked loop system (PLL) in accordance with the present invention maintains phase lock while maintaining phase lock.
Overcoming the limitations of the prior art by providing a method for instantaneously changing the output frequency of a PLL system. FIG. 2 shows a variable speed PLL according to the first preferred embodiment.
1 is a schematic diagram of a system 200. PLL system 200
Can be used in processing systems without disruption,
The processor can be switched from a first clock speed to a second clock speed. PLL system 200
Includes two PLLs interleaved. First PLL
Includes a first phase detector 202, a first charge pump / filter / voltage controlled oscillator (VCO) 206, a programmable frequency divider 208, and a programmable frequency divider 210. The first PLL operates as a first variable speed clock oscillator and provides a frequency selectable clock signal. The second PLL includes a second phase detector 212, a second charge pump / filter /
Includes VCO 216, programmable frequency divider 218, and programmable frequency divider 220. The second PLL operates as a second variable speed clock oscillator to provide a frequency selectable second clock signal. PLL system 200 further includes multiplexer 2
04, 214, 222, and 224. These multiplexers serve as a switching mechanism to switch the output of PLL system 200 from a first clock signal to a second clock signal and vice versa. Therefore, when used in a processing system, the clock speed of the processing system can be switched.

The phase detectors 202 and 212 include a reference gate (REF GATE) signal and a feedback signal.
When both the gate (FB GATE) signals are at the high level, the edge alignment of the reference signal (REF IN) and the feedback signal (FB IN) is compared. The phase detectors 202 and 212 then output pulses from either the incremental output (INC) or the decrement output (DEC), depending on the direction of the detected phase difference.

Multiplexers 204, 214, 222,
Each 224 receives a plurality of inputs and passes one of these inputs to an output depending on the state of the select signal. That is, when the selection signal is at a low level, the "0" input is passed to the output, and when the selection signal is at a high level, the "1" input is passed to the output. Of course, the multiplexer can be replaced with any other suitable logic or other switching mechanism.

Charge pump / filter / VCO 20
6 and 216 (hereinafter VCO 206 and VC
O216) are shown together for clarity, but are preferably standard PLL components. These receive outputs from the phase detectors 202 and 212 via multiplexers 204 and 214, and output oscillating signals of a frequency corresponding to the inputs.

The programmable frequency dividers 208, 21
0, 218 and 220 each receive an input signal,
A signal having a frequency divided by the selected value is output. Specifically, programmable frequency divider 208 divides the frequency by a selectable integer M, programmable frequency divider 218 divides the frequency by a selectable integer N, and programmable frequency dividers 210 and 220 Divide the frequency by a selectable integer P. In a preferred embodiment, the programmable frequency dividers 208 and 21
8 includes a divider that goes high every N cycles for a period equal to one fast clock cycle. In contrast, programmable frequency dividers 210 and 2
20 is preferably a divider that provides a 50% duty cycle of the output signal.

[0021] PLL system 200 receives an input REF and has two outputs labeled BUS CLK and SYS CLK. As will become clear later,
During operation of the PLL system 200, the BUS CLK signal is always in phase with the REF signal and has a frequency equal to the REF signal. When the multiplexer selection signal is at a low level, the frequency of the SYS CLK signal is M
Is multiplied by and divided by P. Similarly, when the multiplexer select signal is high, the frequency of the SYS CLK signal is equal to REF multiplied by N and divided by P. Therefore, by appropriately selecting the values of M, N, and P, the frequency of the SYS CLK signal can be determined to be selectable.

The operation of the PLL system 200 will be described below. Multiplexers 204, 214, 222, 224
Are selected to pass a “0” input, respectively, and the PLL
Assume that system 200 has been operating for a sufficient time to achieve a lock. When the multiplexers are selected to pass a "0" input, respectively, phase detector 202 outputs to VCO 206 via multiplexer 204, and similarly, phase detector 212 outputs to VCO 216 via multiplexer 214. The phase detector 202 outputs the RE
Receive REF signal at F IN, BUS at FB IN
Receive the CLK signal. REF GATE and FB
Since GATE is both tied to a high level (ie, Vdd), phase detector 202
During the cycle, the phase of the REF signal is compared with the phase of the BUS CLK signal, and the corresponding INC signal or DEC signal is output according to the property of the detected phase difference. The INC and DEC signals are passed to the VCO 206, which drives the VCO 206 to provide an output signal having a frequency that drives the PLL to phase lock.

The output signal of VCO 206 is frequency divided by a programmable divider 208 by an integer M. The output of programmable divider 208 is passed through multiplexer 224 to the BUS CLK output, from which it is fed back to the FBIN input of phase detector 202. The signal path from the BUS CLK output to the phase detector 202 produces feedback that facilitates well-known PLL operation. Specifically, the phase detector 202 drives the charge pump / filter / VCO 206,
A signal having the same phase as the EF signal and having a frequency equal to an integer M times the frequency of the REF signal is output. The signal is
It is frequency divided by an integer M by the programmable divider 208 and passed to the BUS CLK output. Therefore,
The BUSCLK output signal is in phase synchronization with the REF signal,
It has the same frequency as the EF signal.

The output of VCO 206 is also passed to a programmable divider 210, where the frequency is divided by an integer P. The output of the programmable divider 210 is coupled via a multiplexer 222 to the SYS CLK output. Therefore, the SYS CLK output signal is VCO2
It has a frequency equal to the frequency of the output of 06 divided by the integer P. Therefore, the frequency of the SYS CLK signal is equal to the frequency of the REF signal multiplied by the integer M and divided by the integer P. Further, the SYS CLK signal is
(Therefore, the phase matches BUS CLK).
When the values of M and P are different, the frequencies of SYS CLK and REF are different, so the meaning of “phase matching” is that they simply periodically match in phase.

If multiplexers 222 and 224 are selected to pass a "0" input, the first P
The LL provides the output of PLL system 200. Thus, PLL system 200 includes a BUS CLK signal whose frequency and phase match the REF signal, and a SYS CLK signal whose phase matches the REF signal and whose frequency is equal to the frequency of the REF signal multiplied by M times P. Is output. Therefore, by properly selecting the values of M and P, the output frequency of the SYS CLK signal can be determined.

At the same time, a second PLL, specifically phase detector 212, receives the output of VCO 216 at FB IN and the output of VCO 206 at REF IN. Phase detector 212 further includes programmable divider 218
At the FB GATE and the output of the programmable divider 208 at the REF GATE.

When the REF GATE and FB GATE inputs are high, the rising edge of the VCO in that cycle is in phase and the phase detector 212
The phase of the output of VCO 216 is compared with the phase of the output of VCO 206. This is done every M cycles of VCO 206 output and every N cycles of VCO 216 output.

The phase detector 212 outputs a corresponding INC signal or DEC signal according to the nature of the detected phase difference. The INC and DEC signals are passed to VCO 216. The output of VCO 216 is the F
Feedback connected to the B IN input. VCO20
6 is also connected to the REF IN input, so that the phase locked loop operation drives VCO 216 to output VCO 216 every V output cycles of VCO 206 and every N output cycles of VCO 216.
An output signal is provided which is in phase with the output of 206. This causes the output of programmable divider 218 to match the output of programmable divider 208 in both frequency and phase. Therefore, the programmable divider 21
The output of 8 is both frequency and phase matched with the REF input signal and the BUS CLK output signal.

When the output of VCO 216 is driven, RE
Since the output of the programmable divider 218 is provided in frequency and phase with the F signal, the output of the VCO 216 has a frequency equal to the frequency of the REF signal multiplied by the integer N, and the output of the VCO 216 is in phase with the REF signal. Match.

Similarly, the output signal of VCO 216 is frequency divided by integer P by programmable divider 220. Thus, the output of the programmable divider 208 has a frequency equal to the frequency of the REF signal divided by the integer M times the integer P, and the phase matches the REF signal.

Thus, selecting multiplexers 204, 214, 222, 224 to pass a "0" input, respectively, results in phase detector 202, VCO 206, programmable divider 208 and programmable divider 21.
0 constitutes an active PLL whose output is coupled to the BUS CLK output and the SYS CLK output. BUS
The CLK output matches in frequency and phase with the REF signal. Similarly, the SYSCLK signal has a frequency of REF.
It is equal to the frequency of the signal multiplied by the integer M and divided by the integer P, and the phase matches the REF signal. Here, the phase detector 212, the VCO 216, the programmable divider 21
8 and programmable divider 220 provide a standby PL
L. At this time, the programmable divider 218
Are driven in frequency and phase with the outputs of the corresponding active PLL (the output of the programmable divider 208), but these outputs are BUS CLK
Output and SYS CLK output.

If it is desired to switch the SYS CLK frequency, all multiplexers 204, 214, 222,
224 are simultaneously switched to pass a "1" input. As will become clear later, this switch causes SYS
The frequency of the CLK output is determined by multiplying REF by M and dividing by P without affecting the BUS CLK output,
Switch to the value obtained by multiplying REF by N and dividing by P.

Every N cycles of VCO 216, VCO 2
REF signal, programmable divider 210 and programmable divider 22 performed every 06 M cycles
This switching is preferably performed when the output of 0 is phased. If the switch is performed when the phasing of these signals is performed in one clock cycle,
The SYS CLK frequency switches without losing phase lock and without interrupting SYS CLK phasing.

Specifically, switching the multiplexer 224 causes the output of the programmable divider 218 to become the BUS CLK instead of the output of the programmable divider 208.
Sent to the output. Before switching, the programmable divider 2
18 was in frequency and phase with the output of the programmable divider 208, so of course the BUS CLK signal does not change.

Switching multiplexer 222 causes the output of programmable divider 220 to be sent to the SYS CLK output instead of the output of programmable divider 210. As a result, the frequency of the SYS CLK becomes M
Is multiplied by P and then switched to REF multiplied by N and divided by P. The switching was performed in one clock cycle and the output of programmable divider 210 was in phase with the output of programmable divider 220 so that the frequency of SYS CLK could be maintained without breaking the phase lock of the SYS CLK signal. Can be switched. SYS
Using CLK as the processor's system clock allows the processor to switch clock speeds and continue operation at the new speed without interruption.

When the multiplexers 204 and 214 are switched, the INC output of the phase detector 202 and the DEC
The outputs are the INC input of the VCO 216 and the DE, respectively.
Input to C input. Similarly, the IN of the phase detector 212
C output and DEC output are DCO of VCO 216, respectively.
Input to EC input and INC input. The INC and DEC inputs are connected to the phase detector 2 to compensate for the FB IN and REF IN inputs of the phase detector 212.
12 / VCO 216.

Multiplexers 204, 214, 222,
224 is switched, the phase detector 202
Drive 216 to output a signal that matches the frequency and phase of the output of programmable divider 218, which is now the output of BUS CLK, with the REF signal. At this time, the frequency / phase combination is naturally the same as when VCO 216 was driven by phase detector 212, and thus the output of programmable divider 218 and the output of BUS CLK do not change. Also, with the same feedback operation, the frequency of the output of the programmable divider 220 is maintained at N times REF divided by P.

Similarly, the phase detector 212 is connected to the VCO 206
To output a signal that matches the frequency and phase of the output of programmable divider 208 with the output of programmable divider 218. At this time, the frequency / phase combination is naturally the same as when the VCO 206 was driven by the phase detector 202, and thus the output of the programmable divider 208 does not change.

Thus, when the multiplexer is switched, the phase detector 202, VCO 216, programmable divider 218 and programmable divider 220 constitute an active PLL, the output of each being BUS CL
It is coupled to the K output and the SYS CLK output. At this time, the phase detector 212, the VCO 206, the programmable divider 208, and the programmable divider 218 constitute a standby PLL. At this time, the output of programmable divider 208 is in frequency and phase with the output of the corresponding active PLL (the output of programmable divider 218), but these outputs are BUS CLK
Output and SYS CLK output.

The output of programmable divider 208 is BU
From the S CLK output, when the output of the programmable divider 210 is disconnected from the SYS CLK output, respectively,
This allows the programmable divider 208 to be reprogrammed. In particular, the BUS CLK output and the SYS CLK output are now driven by programmable dividers 218 and 220, respectively, so that the programmable divider 21 can be output without interrupting the BUS CLK output signal and the SYS CLK output signal.
The integer M of 8 is changed.

After reprogramming the programmable divider 208, the multiplexers 204, 214, 22
2, 224 can each be switched again to pass a "0" input, thereby again maintaining phase lock and maintaining the frequency and phase of the BUS CLK signal while changing the SYS CLK frequency to a new frequency (REF).
Multiplied by the new M and divided by P). Thus, when the multiplexer is switched back to "0", the phase detector 202, VCO 206, programmable divider 208 and programmable divider 218 also form an active PLL. At this time,
Programmable divider 208 is connected to BUSCLK, and programmable divider 210 is connected to SYS CLK. Similarly, the phase detector 212, the VCO 216,
Programmable divider 218 and programmable divider 220 again constitute a standby PLL.

The programmable divider 218 can then be reprogrammed (ie, change the integer N) and the switch is performed again. Thus, by switching the multiplexer, reprogramming the standby programmable divider, and switching the multiplexer again, the SYS CL
The frequency of K can be changed from one frequency to another. All this does not interrupt the phase of the SYS CLK signal, but does
This is performed while continuously supplying the LK signal. Thus, the system enables the operating frequency of a system, such as a computer system, to be switched from one operating frequency to another without interrupting the system processor. Further, the system provides a fixed frequency second clock signal in phase with the frequency switchable clock signal.

Next, FIG. 3 shows a schematic diagram of the phase detector 300. Phase detector 300 is a preferred phase detector for use as phase detector 202 and phase detector 212 in the preferred embodiment. The phase detector 300 is a phase / frequency detector, that is, a detector that detects both a phase difference and a frequency difference and outputs a signal corresponding to the detected difference. These signals are used to drive the VCO to eliminate phase and frequency differences.

Thus, there is provided a PLL system capable of dynamically switching frequencies from one frequency to another without interrupting signal phase lock. The PLL system can be used wherever frequency switching is required while maintaining phase lock. Specifically, a PLL system can be used to provide a system clock and a bus clock for the microprocessor. The PLL system can be used, for example, to raise or lower the frequency of the system clock in response to changes in environmental conditions.

In the drawings, various conductors are shown by one line.
It will also be appreciated that this is not the case in a limiting sense and may include multiple conductors as understood in the art.

In summary, the following items are disclosed regarding the configuration of the present invention.

(1) In a phase locked loop system which provides a system output signal having a certain frequency and can switch the frequency without interrupting the phase lock of the system output signal, receiving a reference signal; A first phase-locked loop that outputs a first phase-locked loop output signal having a frequency of 1; and a second phase-locked loop that receives the first phase-locked loop output signal and has a second frequency. A second phase locked loop for outputting a loop signal; and the first phase locked loop.
A switching mechanism for selecting the system output signal from a loop output signal and the second phase locked loop output signal, wherein the frequency of the system output signal is reduced without the interruption of the phase lock of the system output signal. A phase locked loop system, wherein the frequency is switched from a first frequency to a second frequency. (2) the first phase locked loop includes a first oscillator and a first phase detector for comparing a phase of the reference signal with a second system output; Outputs a first phase difference signal proportional to a first detected phase difference, wherein the second phase locked loop changes the phase of the output of the second oscillator and the first oscillator to the second phase. A second phase detector for comparing the output phase of the oscillator with the second phase detector, wherein the second phase detector outputs a second phase difference signal proportional to a second detected phase difference. The phase locked loop system according to the above (1). (3) a first selection mechanism, wherein the switching mechanism receives the first phase difference signal and the second phase difference signal and passes a first selected phase difference signal to the first oscillator; And a second selection mechanism that receives the second phase difference signal and the second phase difference signal, and passes a second selected phase difference signal to the second oscillator. Phase locked loop system. (4) a first frequency divider that receives the first signal and outputs a divided first signal; and a second frequency divider that receives the second signal and outputs a divided second signal. A frequency divider, wherein the divided first signal comprises the first phase locked loop output signal, and wherein the divided second signal comprises the second phase locked loop output signal. Wherein the switching mechanism includes a third selection mechanism for receiving the split first signal and the split second signal and outputting a selected split signal; A phase locked loop system according to (3), wherein the signal obtained is coupled to the system output. (5) a third frequency divider for receiving the first signal and outputting a second divided first signal; and a second divided second signal for receiving the second signal. Receiving the second divided first signal and the second divided second signal, and outputting a second selected divided signal. A fourth selection mechanism, wherein the second selected divided signal is coupled to a second system output and further fed back to the first phase detector. The phase-locked loop system according to the above (4). (6) The phase locked loop system according to (5), wherein the first, second, third, and fourth selection mechanisms include a multiplexer. (7) the first and second frequency dividers include a programmable divider that divides each input signal by a programmable integer P, and the third frequency divider includes a programmable integer M The method of claim 5, further comprising a programmable divider for dividing the input signal, wherein the fourth frequency divider includes a programmable divider for dividing the input signal by a programmable integer N. Phase locked loop system. (8) a first charge pump having an increment input and a decrement input and having an output coupled to the first oscillator; and a first charge pump having an increment input and a decrement input coupled to the second oscillator. A second charge pump having an output, the first phase detector including an incremental output signal and a decremented output signal, wherein the second phase detector includes an incremental output signal and a decremented output signal. Wherein the incremental signal of the first phase detector is coupled to an incremental input of the first charge pump via the first selection mechanism and the second signal is provided via the second selection mechanism. And a decrement signal of the first phase detector is coupled to the decrement input of the first charge pump via the first selection mechanism; and The second channel through the second selection mechanism; Coupled to the decrement input of the
An incremental signal of the second phase detector is coupled to an incremental input of the second charge pump via the second selector and to the first charge via the first selector. A decrement input of the second phase detector coupled to a decrement input of a second pump; and a decrement signal of the second phase detector coupled to a decrement input of the second charge pump; (3) characterized in that it is coupled to an incremental input of said first charge pump via a selection mechanism.
A phase locked loop system according to claim 1. (9) A method for switching a phase locked clock signal from a first frequency to a second frequency without interrupting phase locking of the clock signal, comprising: a) a phase locked loop that outputs a system output signal.
Providing a system, wherein the phase locked loop system compares the phases of a first input and a second input and outputs a first phase difference signal proportional to the detected phase difference. And a first phase detector for outputting a first signal.
And the phases of the first input and the second input are compared.
A second phase detector that outputs a second phase difference signal proportional to the detected phase difference, a second oscillator that outputs a second signal, the first phase difference signal and the second phase Receiving a phase difference signal and converting the first selected phase difference signal to the first
A first selection mechanism for passing the first phase difference signal and the second phase difference signal to the second oscillator and passing a second selected phase difference signal to the second oscillator. A first frequency divider that receives the first signal and outputs a divided first signal; and a second frequency divider that receives the second signal and outputs a divided second signal. Including a frequency divider and a third selection mechanism for receiving the divided first signal and the divided second signal and outputting a selected divided signal coupled to the system output; B) switching the first selection mechanism such that the first selection mechanism passes the second selected phase difference signal to the first oscillator; c) the second selection mechanism Converts the first selected phase difference signal to the second oscillator As pass, the method comprising switching the second selection mechanism, d) a method comprising the steps of switching the third selection mechanism. (10) The step of switching the first selection mechanism, the step of switching the second selection mechanism, and the step of switching the third selection mechanism include the step of switching the first divided signal and the second division. Method according to (9), characterized in that the performed signals are executed substantially simultaneously when they are in phase. (11) a third frequency divider for receiving the first signal and outputting a second divided first signal, the phase locked loop system receiving the second signal, A fourth frequency divider that outputs two divided second signals; and a second frequency divider that receives the second divided first signal and the second divided second signal and performs a second selection. A fourth selection mechanism for outputting a divided signal, wherein the second selected divided signal is coupled to a second system output and further fed back to the first phase detector. The method according to (9), further comprising a fourth selection mechanism, further comprising switching the fourth selection mechanism. (12) A phase-locked device that provides a system output signal having a certain frequency and can switch the frequency without interrupting the phase lock of the system output signal.
A) a loop system comprising: a) a first phase detector that compares the phases of a first input and a second input and outputs a first phase difference signal proportional to the detected phase difference; and b) a first phase detector. And c) comparing the phases of the first input and the second input, and outputting a second phase difference signal proportional to the detected phase difference. D) a second oscillator for outputting a second signal; e) receiving the first phase difference signal and the second phase difference signal and converting a first selected phase difference signal to the first signal. A first selector for passing the first phase difference signal and the second phase difference signal to the second oscillator, and passing a second selected phase difference signal to the second oscillator. G) receiving the first signal and receiving a first divided first signal;
A) a first frequency divider that outputs a second divided signal; h) receiving the second signal;
A) a second frequency divider that outputs the first divided signal and the first divided second signal and outputs a selected divided signal. A third selection mechanism, wherein the selected divided signal is coupled to the system output and fed back to the first phase detector; and j) converting the first signal. Receiving the second divided first
A third frequency divider that outputs a second divided signal; k) receiving the second signal and receiving a second divided second signal;
A) a second frequency-divided signal that receives the second divided first signal and the second divided second signal and outputs a second selected divided signal; And a fourth selection mechanism for outputting a phase-locked loop. (13) a first charge pump having an increment input and a decrement input and having an output coupled to the first oscillator; and a first charge pump having an increment and decrement input and coupled to the second oscillator. A second charge pump having an output, wherein the first phase detector includes an incremental output signal and a decrement output signal, and wherein the second phase detector includes an incremental output signal and a decrement output signal. Wherein the incremental signal of the first phase detector is transmitted to the first phase detector via the first selection mechanism.
And coupled to the incremental input of the second charge pump via the second selection mechanism, wherein the decrement signal of the first phase detector is coupled to the incremental input of the second phase pump. And the first charge mechanism via the first selection mechanism.
Coupled to a decrement input of a pump and to a decrement input of the second charge pump via the second selection mechanism, wherein an incremental signal of the second phase detector is coupled to the second phase detector. Coupled to an increment input of the second charge pump via a selection mechanism and to a decrement input of the first charge pump via the first selection mechanism;
The phase detector's decrement signal is coupled to the decrement input of the second charge pump via the second selection mechanism;
And the first charge mechanism via the first selection mechanism.
The system of claim 12, wherein the system is coupled to an incremental input of a pump. (14) a) a processor operating at the first clock speed in response to the first variable speed clock oscillator supplying the first clock signal to the processor at the first clock speed; b) preselecting A second variable-speed clock oscillator that oscillates a second clock signal at the determined second clock speed; and c) a first variable-speed clock oscillator that causes the processor to continue operating without interruption at the second clock speed. Means for switching the processor from a first clock signal at a first clock rate to a second clock signal at a second clock rate at a moment when an edge of the clock signal coincides with an edge of the second clock signal. A processing system characterized by the following. (15) The first variable speed clock oscillator includes a first phase locked loop, and the second variable speed clock oscillator includes a second phase locked loop.
The processing system according to the above (14). (16) The switching means comprises a first clock signal and a second clock signal.
The processing system according to (14), further including a first selection mechanism that receives the clock signal of (1). (17) A first variable speed clock oscillator includes a first oscillator and a first phase detector that outputs a first phase difference signal, and the second variable speed clock oscillator includes a second oscillator. And a second phase detector for outputting a second phase difference signal, wherein the switching means further receives the first phase difference signal and the second phase difference signal and outputs a first selected signal. A second selection mechanism for passing a phase difference signal to the first oscillator, receiving the first phase difference signal and the second phase difference signal, and passing a second selected phase difference signal to the second oscillator; The processing system according to the above (16), further comprising: a third selection mechanism for passing to the oscillator. (18) The processing system according to (17), wherein the first, second, and third selection mechanisms include a multiplexer.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a prior art phase locked loop device.

FIG. 2 is a schematic diagram of a variable speed phase locked loop device according to a preferred embodiment.

FIG. 3 is a schematic diagram of the phase detector of FIG. 2 according to a preferred embodiment;

[Explanation of symbols]

REFERENCE SIGNS LIST 100 phase locked loop (PLL) 102 phase detector 104 charge pump 106 filter 110 voltage controlled oscillator (VCO) 114 feedback divider 200 variable speed PLL system 202 first phase detector 204 multiplexer 206 first charge pump / Filter / voltage-controlled oscillator 208 programmable frequency divider 210 programmable frequency divider 212 second phase detector 214 multiplexer 216 second charge pump / filter / voltage-controlled oscillator 218 programmable frequency divider 220 programmable frequency Divider 222 multiplexer 224 multiplexer

Continued on the front page (72) Inventor John Edwin Garsbach United States 05401 Burlington, Vert.South Willard Street 500 (72) Inventor Charles Joseph Massenas United States 05452 Essex Junction Corduroy Road 25, Vermont 25 (56) References JP-A-7-123001 (JP, A) JP-A-6-45930 (JP, A) JP-A-6-188731 (JP, A) JP-A-9-261019 (JP, A) ( 58) Field surveyed (Int. Cl. ⁷ , DB name) H03L ⁷ /06-7/23

Claims (13)

(57) [Claims] 1. A phase locked loop system for providing a system output signal having a frequency and capable of switching said frequency without interrupting phase lock of said system output signal, comprising: receiving a reference signal; A first phase-locked loop that outputs a first phase-locked loop output signal of a first frequency; a first phase-locked loop output signal of the first frequency; and a divided first signal. A first frequency divider for outputting the first phase locked loop output signal and a second phase locked loop for outputting a second phase locked loop output signal having a second frequency; A second frequency divider that receives a second phase locked loop output signal at the second frequency and outputs a divided second signal; And a first switching mechanism that receives one of the first signal and the divided second signal and outputs one of the divided first signal and the divided second signal as the system output signal. Without said interruption of the phase lock of the system output signal;
The frequency of the system output signal is
Phase locked loop system switched between the frequency of the second signal and the frequency of the divided second signal. 2. The first phase locked loop includes a first phase detector for receiving the reference signal, a second switching mechanism for receiving an output of the first phase detector, and a second switching mechanism for receiving the output of the first phase detector. A first oscillator receiving the output of the switching mechanism and outputting the first phase locked loop output signal; and receiving a first phase locked loop output signal of the first frequency from the first oscillator. A third frequency divider that outputs a divided third signal equal to the frequency of the reference signal, and a third frequency divider that receives the divided third signal and applies the signal to the input of the first phase detector. A switching mechanism, the second phase locked loop receiving a first phase locked loop output signal of the first frequency from the first oscillator, a second phase detector; The output of phase detector 2 A fourth switching mechanism for receiving, a second oscillator for receiving an output of the fourth switching mechanism, and outputting a second phase-locked loop output signal at the second frequency; and A fourth frequency divider that receives a second phase locked loop output signal of the second frequency and outputs a divided fourth signal equal to the frequency of the reference signal to an input of the third switching mechanism; The phase-locked loop system according to claim 1, comprising: 3. The phase detector according to claim 1, wherein the first phase detector detects a phase of the reference signal and a phase of the divided third signal applied by the third switching mechanism or the phase of the divided fourth signal.
And outputs a first phase difference signal proportional to the phase difference to the second switching mechanism and the fourth switching mechanism, wherein the second phase detector outputs the first phase difference signal. Comparing the phase of the phase-locked loop output signal with the phase of the second phase-locked loop output signal, and providing a second phase difference signal proportional to the phase difference to the second switching mechanism and the fourth Output to a switching mechanism, wherein the second switching mechanism receives the first phase difference signal or the second phase difference signal and outputs a first selected phase difference signal to the first transmitter The fourth switching mechanism receives the first phase difference signal or the second phase difference signal and outputs a second selected phase difference signal to the second transmitter. The phase transformer according to claim 2, Lock loop system. 4. The phase lock according to claim 3, wherein said first switching mechanism, said second switching mechanism, said third switching mechanism and said fourth switching mechanism are multiplexers. ·loop·
system. 5. The frequency divider of claim 1, wherein the first frequency divider is a programmable frequency divider, and divides a frequency of a first phase locked loop output signal of the first frequency by a positive number P; Is a programmable frequency divider that divides the frequency of the second phase locked loop output signal at the second frequency by a positive number P; and wherein the third frequency divider is programmable. A frequency divider that divides the frequency of the first phase locked loop output signal at the first frequency by a positive number M; wherein the fourth frequency divider is a programmable frequency divider; 3. The phase locked loop system according to claim 2, wherein the frequency of the second phase locked loop output signal at a frequency of 2 is divided by a positive number N. 6. The first phase detector outputs an increment signal and a decrement signal, the second phase detector outputs an increment signal and a decrement signal, and an increment of the first phase detector. A signal coupled to the incremental input of the first oscillator via the second switching mechanism, coupled to an incremental input of the second oscillator via the fourth switching mechanism; The decrement signal of the phase detector is coupled to the decrement input of the first oscillator via the second switching mechanism, and the decrement signal of the second oscillator is coupled via the fourth switching mechanism. Coupled to an incremental input of the second phase detector, the incremental signal of the second phase detector is coupled to an incremental input of the second oscillator via the fourth switching mechanism, and A second oscillator coupled to a decrement input of the first transmitter; A decrement signal of the detector is coupled to the decrement input of the second oscillator via the fourth switching mechanism and to an increment input of the first oscillator via the second switching mechanism. The phase locked loop system according to claim 3, wherein the phase locked loop system is coupled. 7. A method for switching a phase locked clock signal from a first frequency to a second frequency without interrupting phase locking of the clock signal, comprising: a) a phase locked loop that outputs a system output signal.
Providing a system, wherein the phase locked loop system compares the phases of a first input and a second input and outputs a first phase difference signal proportional to the detected phase difference. A first phase detector, a first oscillator for outputting a first signal, and comparing the phases of a first input and a second input, and outputting a second phase difference signal proportional to the detected phase difference A second phase detector, a second oscillator that outputs a second signal, receives the first phase difference signal and the second phase difference signal, and generates a first selected phase difference signal. A first selection mechanism for passing to the first oscillator, a first selection mechanism for receiving the first phase difference signal and the second phase difference signal, and passing a second selected phase difference signal to the second oscillator; Receiving the first signal and outputting a divided first signal A first frequency divider that receives the second signal and outputs a divided second signal; a divided first signal and the divided second signal And b) a third selection mechanism for receiving a signal of said second phase difference signal and outputting a selected divided signal coupled to said system output; and b) said first selection mechanism outputs said second selected phase difference signal. Switching the first selection mechanism to pass the signal to the first oscillator; c) causing the second selection mechanism to pass the first selected phase difference signal to the second oscillator. Switching the second selection mechanism; and d) switching the third selection mechanism. 8. Switching the first selection mechanism;
Switching the second selection mechanism and switching the third selection mechanism are performed substantially when the divided first signal and the divided second signal are in phase. 8. The method according to claim 7, wherein the steps are executed simultaneously.
The method described in. 9. A phase locked loop system for receiving the first signal and for outputting a second divided first signal; and a third frequency divider for receiving the second signal. A fourth frequency divider that outputs a second divided second signal; and a second frequency divider that receives the second divided first signal and the second divided second signal; A fourth selection mechanism for outputting the selected divided signal of the second phase, wherein the second selected divided signal is coupled to a second system output and further fed back to the first phase detector. 8. The method of claim 7, further comprising: a fourth selection mechanism that is configured to switch, further comprising switching the fourth selection mechanism. 10. A phase locked loop system for providing a system output signal having a frequency and capable of switching said frequency without interrupting phase lock of said system output signal, comprising: a) a first input; A first phase detector that compares the phase of the second input and outputs a first phase difference signal proportional to the detected phase difference; b) a first oscillator that outputs the first signal; c. A) a second phase detector that compares the phases of the first input and the second input and outputs a second phase difference signal proportional to the detected phase difference; and d) a second phase detector that outputs the second signal. E) a first selection mechanism that receives the first phase difference signal and the second phase difference signal and passes a first selected phase difference signal to the first oscillator; f) A) the first phase difference signal and the second phase difference signal; Receive a second selection mechanism to pass the second selected phase difference signal to said second oscillator, g) receiving the first signal, the first, which is first split
A) a first frequency divider that outputs a second divided signal; h) receiving the second signal;
A) a second frequency divider that outputs the first divided signal and the first divided second signal and outputs a selected divided signal. A third selection mechanism, wherein the selected divided signal is coupled to the system output signal; j) receiving the first signal, and receiving a second divided first signal;
A third frequency divider that outputs a second divided signal; k) receiving the second signal and receiving a second divided second signal;
A) a second frequency-divided signal that receives the second divided first signal and the second divided second signal and outputs a second selected divided signal; And a fourth selection mechanism for outputting a feedback signal to the first phase detector. 11. A first charge pump having an increment input and a decrement input and having an output coupled to the first oscillator; and a first charge pump having an increment input and a decrement input, wherein the second oscillator has A second charge pump having a combined output; wherein the first phase detector includes an increment signal and a decrement signal; and wherein the second phase detector includes an increment signal and a decrement signal. An incremental signal of the first phase detector is coupled to an incremental input of the first charge pump via the first selection mechanism, and the second signal via the second selection mechanism. A decrement signal of the first phase detector coupled to an increment input of a charge pump, coupled to a decrement input of the first charge pump via the first selection mechanism; The second charge via the selection mechanism of (2) Coupled to a decrement input of a pump, the incremental signal of the second phase detector coupled to an incremental input of the second charge pump via the second selection mechanism, and to the first select The decrement signal of the second phase detector is coupled to a decrement input of the first charge pump via a mechanism, and the decrement signal of the second charge pump is reduced via the second selection mechanism. The system of claim 10, coupled to a minute input and coupled to the first charge pump incremental input via the first selection mechanism. 12. A processor, a first phase detector for outputting a first phase difference signal, and a first phase detector.
A first phase locked loop having a first oscillator for generating a first clock signal and a first frequency divider receiving the first signal and outputting a first clock signal at a first clock rate. A first variable speed clock oscillator, a second phase detector for outputting a second phase difference signal, and a second phase detector
A second phase locked loop having a second oscillator for generating a second clock signal and a second frequency divider receiving the second signal and outputting a second clock signal at a second clock rate. A second variable speed clock generator; and for operating the processor operating at the first clock speed in response to the first clock signal at the second clock speed without interruption. The first
At the moment when the edge of the second clock signal coincides with the edge of the second clock signal,
Means for switching the processor from the second clock signal to a second clock signal at the second clock rate.
The switching means includes: a first selection mechanism that receives the first clock signal and the second clock signal; a first selection mechanism that receives the first phase difference signal and the second phase difference signal; A second selection mechanism for passing a phase difference signal to the first oscillator, receiving the first phase difference signal and the second phase difference signal, and passing a second selected phase difference signal to the second A third selection mechanism for passing the data to the transmitter. 13. The processing system according to claim 12, wherein said first selection mechanism, said second selection mechanism, and said third selection mechanism are multiplexers.