JP3395319B2 - Transmitter / receiver using the time-division transmitting / receiving method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission / reception apparatus of a time division transmission / reception system suitable for application to, for example, a portable radiotelephone for digital communication.

[0002]

2. Description of the Related Art In a digital cordless telephone such as a telepoint system or a personal handyphone, the same frequency is used for transmission and reception, and TDD method (time division duplex method) in which burst data is transmitted in a time division manner, that is, ping-pong transmission. ) Or a TDMA / TDD system (time division multiple access / time division duplex system) is adopted.

That is, in the case of the TDD system, for example, A in FIG.
, One channel (frequency) is temporally divided into a transmission slot T and a reception slot R, these slots T and R are alternately repeated, and a guard is provided between these slots T and R. A time (not shown) is provided. In this case, for example, each slot T and R is set to 1 msec and the guard time is set to several tens of microseconds. And
In the mobile phone (handset) performs transmission to the base station (parent device) Te in the transmission slot T, and receives from the base station Te to the reception slot R.

In the case of the TDMA / TDD system,
As shown in FIG. 3B, a transmission slot T and a reception slot R in one channel are used for communication between one slave unit and the master unit.
, Are used only once every several cycles, and other transmission slots T and reception slots R in the same channel are used for communication between another slave unit and the master unit, and a plurality of units are used for one channel. It is multiplexed so that communication between communication devices can be performed.
By being multiplexed in this way, the frequency band prepared for the cordless telephone can be used efficiently.

FIG. 4 shows an example of the configuration of a slave unit of a digital cordless telephone which performs communication by such a communication system. As a configuration of the receiving system, the signal received by the antenna 1 (π / 4 shift QPSK modulation) is used. Signal) is supplied to the reception system of the transmission / reception processing circuit 10 via an antenna changeover switch (not shown), and the bandpass filter 11,
It is supplied to the mixer 13 via the low noise amplifier 12.
Then, the mixer 13 mixes the frequency signal f ₀ for receiving channel selection supplied from the PLL circuit (phase locked loop circuit) 14 via the buffer circuit 26 to obtain the first intermediate frequency signal f _i1 . To do. Then, the first intermediate frequency signal f _i1 is supplied to the mixer 16 via the bandpass filter 15, and the predetermined frequency signal supplied from the oscillator 17 is mixed to form a second intermediate frequency signal f _i2 . .

Then, the second intermediate frequency signal f _i2 is supplied to the detection circuit 19 through the bandpass filter 18,
The received signal is detected. Then, the baseband signal obtained by the detection of the detection circuit 19 is processed by the TDMA / TDD processing circuit 30.
And the reception timing is controlled in the TDMA / TDD processing circuit 30. As the control of the reception timing, a process of extracting the burst data received at the specified timing is performed. Then, the extracted received data is supplied to the compression / expansion circuit 40 to be expanded, and the expanded received data is supplied to the PCM codec circuit 50,
Digital voice processing is performed to produce an analog voice signal, and this analog voice signal is supplied to the speaker 2 in the handset and output.

The transmission system is configured so that the sound picked up by the microphone 3 in the handset is PCM codec circuit 5
0 to convert it to digital audio data, supply the digital audio data to the compression / decompression circuit 40 for compression, and supply the compressed audio data to the TDMA / TDD processing circuit 30 for transmission at a burst. Let it be data. Then, the burst data at this transmission timing is supplied to the transmission system of the transmission / reception processing circuit 10, and the binary orthogonal transformation circuit 21 performs orthogonal modulation. In the quadrature modulation at this time, the transmission data is 2-channel data, that is, I-channel and Q-channel data. And this I
The channel and Q channel data are orthogonally modulated in synchronization with the modulation wave supplied from the oscillator 22. Here, the frequency f _L of the modulated wave output from the oscillator 22 is made equal to the first intermediate frequency signal f _i1 . Further, as quadrature modulation in the quadrature modulator 22 in this case, π / 4 shift QPSK modulation is performed.

Then, the quadrature-modulated transmission data is supplied to the mixer 23, and the frequency signal f ₀ for transmission channel selection output from the PLL circuit 14 is mixed to form a signal of a predetermined transmission channel. In this case, the frequency signal f ₀ output by the PLL circuit 14 is supplied to the mixer 23 via the buffer circuit 27. Then, the output of the mixer 23 is supplied to the antenna 1 via the bandpass filter 24, the power amplifier 25, and the antenna changeover switch (not shown) to be wirelessly transmitted.

Note that such a reception and transmission process is
Central control unit (CP
U) 60, and control of transmission timing and reception timing is also performed by the central control unit 60. In addition, the central controller 60 is provided with a key 4 for performing various operations.
And the display panel 5 that displays the communication status such as the dial number is connected.

Here, the format of the data transmitted and received by this cordless telephone will be explained. The structure of one slot of the data transmitted at the time of a telephone call with the base station (master device) is as shown in FIG. 5, for example. In addition, the leading part is a preamble pattern PR, and in the following, a unique word UW, a channel type CI, and a low-speed associated channel S
A, audio data TCH, and error correction code CRC.
This 1-slot data is transmitted in hundreds of microseconds.

By the way, in the case of such a cordless telephone handset, in order to reduce the power consumption, the transmission circuit is operated only during the period for transmitting the data of the slot configuration described above, and the data of the slot configuration is transmitted. The power supply is controlled so that the receiving circuit is operated only during the receiving period. By doing so, it is possible to significantly reduce power consumption and prolong battery life, as compared with a case where power is constantly supplied to the transmitting circuit and the receiving circuit to operate during a call.

[0012]

However, if the power supply is turned on and off repeatedly during the transmission slot period and the reception slot period, the power supply voltage and the transmission line impedance fluctuate, which adversely affects other circuits. Will affect. In particular, a PLL circuit that generates a frequency signal that serves as a reference for determining a reception frequency and a transmission frequency causes a change in the output frequency due to a change in the power supply voltage and a change in the load. This frequency fluctuation causes fluctuations in the transmission frequency and the reception frequency, and increases the bit error of the demodulated data at the time of reception.

In order to solve such a problem, for example, the buffer circuits 26 and 27 inserted between the PLL circuit and the transmission circuit and the reception circuit should be circuits having a configuration in which load fluctuation is sufficiently suppressed. However, in order to make a buffer that copes with sufficient load fluctuations in this way,
It is necessary to connect amplifiers composed of bipolar transistors or the like in multiple stages, which complicates the structure for that and also causes the inconvenience that the power consumption of the amplifiers forming this buffer increases.

In view of the above points, an object of the present invention is to suppress fluctuations in transmission / reception frequency when power supply control is performed according to transmission / reception timing in this type of transmission / reception apparatus.

[0015]

The present invention, for example, as shown in FIG. 1, demodulates a transmission circuit 10b for modulating a transmission signal at a predetermined frequency and transmitting the signal, and a reception signal modulated at a predetermined frequency. a reception circuit 10a, a frequency generator 14 for generating a signal of the predetermined frequency, connected between the frequency generating circuit 14 and the transmitting circuit 10 b, a transmission buffer circuit 27 to reduce the load variation, Above frequency
Connected between the generating circuit 14 and the receiving circuit 10a,
And a receiving buffer circuit 26 for reducing load fluctuation ,
A time-division transmission / reception system transmitting / receiving apparatus that intermittently performs transmission on a transmission slot by a transmission circuit 10b and reception on a reception slot by a reception circuit 10a at different timings.
On the other hand, at least the above transmission buffer circuit and reception buffer circuit
Power supply to the buffer circuit is not duplicated over time
From the start to the end of the transmit slot
During the first period , the first control signal for keeping the transmission circuit in the power supply state ,
Until the end of the transmission slot, the above transmission buffer times
The second control signal that keeps the line powered and the receive slot
From the start point to the end point of the
3rd control signal to keep power supply and start of receiving slot
The end of the receiving slot from the point before the given period before the point in time
Until that time, keep the receiving buffer circuit powered.
A new power supply control circuit for generating the fourth control signal
It is provided .

At this time, the transmission buffer circuit
A frequency signal is supplied to the mixer in the transmitter circuit.
The power supply for controlling is controlled by the second control signal.
Meanwhile, the frequency signal from the receiving buffer circuit is supplied.
The power supply to the mixer in the receiving circuit is
It is obtained by the so that is controlled by the fourth control signal.

[0017]

According to the present invention, the power supply of the buffer circuit is turned on for a predetermined period before the start of transmission or reception, but during this predetermined period, the influence of frequency fluctuation is removed by the buffer circuit, and the actual transmission or When reception starts, the output of the frequency generation circuit is stable, and stable transmission and reception can be performed in time division.

Further, in this case, the mixer for mixing the frequency signal with the transmission signal in the transmission circuit and the mixer for mixing the frequency signal with the reception signal in the reception circuit are operated a predetermined period before the transmission / reception start timing. , More stable transmission and reception processing will be performed.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 and 2, parts corresponding to those in FIGS. 3 to 5 described in the conventional example are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this example, TDMA is performed as in the conventional example.
It is applied to a cordless telephone handset that transmits / receives slot-structured digital data by the / TDD method.
It is configured as shown in FIG. In FIG. 1, reference numeral 61 denotes a power supply control circuit, and this power supply control circuit 61 is a circuit for controlling the power supply to each part in the transmission / reception processing circuit 10 based on the control of the central controller 60. As control of the transmission / reception processing circuit 10 by the power supply control circuit 61, control of five systems is performed simultaneously.

That is, the bandpass filter 11 to the bandpass filter 18 of the receiving circuit system in the transmission / reception processing circuit 10
And the oscillator 17 for generating the second intermediate frequency signal as the receiving unit 10a, and the route from the oscillator 22 of the transmission circuit system to the power amplifier 25 as the transmitting unit 10b, the receiving unit 10a and the transmitting unit 10b The PLL circuit 14, the buffer circuit 26, and the buffer circuit 27 are connected to the power supply control circuit 61.
The power is controlled individually by.

As a concrete power source control by the power source control circuit 61, when it is necessary to periodically perform reception or transmission during a call using the slave unit, the PLL circuit 14 which is a frequency generation circuit is used. A power source is constantly supplied to always operate, and a frequency signal f ₀ corresponding to the transmission frequency and the reception frequency (the transmission frequency and the reception frequency are the same) at this time is continuously output.

Then, during the period of the receiving slot in which it is necessary to receive the data of the slot configuration, the receiving section 10a is supplied with power to perform the receiving process. And this receiving unit 1
Power is supplied to the buffer circuit 26 between the PLL circuit 14 and the receiving unit 10a from a predetermined period before the power is supplied to 0a (about 1 msec before here) to the end of the period of the receiving slot until the buffer circuit 26 is operated.

Further, during the period of the transmission slot in which it is necessary to transmit the data having the slot configuration, the power is supplied to the transmission section 10b to perform the transmission processing. Then, this transmitting unit 10
a predetermined period before the power is supplied to b (here, about 1 ms before)
Until the end of the transmission slot period, the PLL circuit 14
Power is supplied to the buffer circuit 27 between the transmitter 10b and the transmitter 10b to operate it.

The central control unit 60 supplies the power supply control circuit 61 with data relating to the periods of the transmission slot and the reception slot so that the power supply control circuit 61 can determine the periods of the transmission slot and the reception slot.

Here, the control state of the power supply control circuit 61 is shown in the timing chart of FIG. 2. If the period of the transmission slot assigned to communication at this time is t ₁ ,
As shown in the A, in the period t ₁ of transmission slot is operated by turning on the transmission section 10b, the transmission portion 10b and the PL
The buffer circuit 27 between the L circuit 14 and
As shown in, the predetermined period of time than t ₁ of the transmission slot (t _2: about 1m sec) is the transmission slot period t ₁ is operated by on continuously until the end of the previous. Further, when the period of the receiving slot is t ₃ , as shown in C of FIG.
During the receiving slot period t ₃ , the receiving unit 10a is turned on and operated, and the buffer circuit 26 between the receiving unit 10a and the PLL circuit 14 is moved to the receiving slot period t 3 as shown in D of FIG. Predetermined period than ₃ (t ₄ : about 1 msec)
From the front until the reception slot period t ₃ ends, it is continuously turned on and operated.

In the case of this example, the buffer circuits 26 and 27 between the PLL circuit 14 and the receiving section 10a and the transmitting section 10b are each composed of a buffer amplifier of one-stage bipolar transistor. Also, the receiving unit 1
0a, filters 11, 15, 18, 2 in the transmitter 10b
Reference numeral 4 is a circuit that does not require a power supply and does not need to be controlled by the power supply control circuit 61.

Other parts are constructed in the same manner as the conventional cordless telephone shown in FIG.

[0029] When Ru Thus <br/> by the configured cordless phone, stable and good transmission processing and reception processing can be performed with low power consumption. That is, the transmitter 10b and the PLL circuit 14
As shown in FIG. 2B, the buffer circuit 27 located between and is operated by being turned on for a predetermined period t ₂ before the period t _{1 of the} transmission slot, so that the power supply voltage due to the operation of the buffer circuit 27 is increased. 2 and the load impedance, the output frequency fo of the PLL circuit 14 slightly fluctuates as shown in E of FIG.
_When it becomes ₁ , the output frequency fo is already stable at a constant frequency. Therefore, the signal subjected to the transmission processing in the transmission section 10b during the transmission slot becomes a good signal modulated at a stable frequency and can be satisfactorily transmitted to the other party.

Similarly, as shown in D of FIG. 2, the buffer circuit 26 between the receiving section 10a and the PLL circuit 14 is turned on for a predetermined period t ₄ before the period t _{3 of the} receiving slot to operate. By doing so, the output frequency f ₀ of the PLL circuit slightly fluctuates as shown in F of FIG. 2 due to the fluctuation of the power supply voltage and the fluctuation of the load impedance due to the operation of the buffer circuit 26, but the period t _{3 of the} receiving slot. When, the output frequency f ₀ is already stable at a constant frequency. Therefore, the receiving unit 10 can be used during the receiving slot
The signal subjected to the reception processing in a becomes a good signal received at a stable frequency and does not deteriorate the error rate of the reception data.

In addition, the output of the PLL circuit is stabilized during the transmission slot period and the reception slot period in this way, so that the buffer circuits 26 and 27 are constructed as a buffer amplifier having a simple structure using one-stage bipolar transistor. Even then, the processing is performed well. Therefore, the buffer circuits 26 and 27 can be configured in a simpler and smaller circuit than the conventional one, and the power consumption required for the buffer amplifier can be reduced. For example, when the device is driven by a battery, The battery life can be extended.

The mixer 13 in the receiver 10a to which the output of the buffer circuit 26 is supplied and the mixer 23 in the transmitter 10b to which the output of the buffer circuit 27 is supplied are the buffer circuit 26 and the buffer circuit 27. Power supply control may be performed in the same manner as. That is, the mixer 13 of the receiving system
Is activated about 1 ms before the period of the reception slot by the control signal for activating the buffer circuit 26, and the mixer 23 of the transmission system is activated by the control signal for activating the buffer circuit 27 over the period of the transmission slot. The operation may be started from about 1 ms before. By doing this,
The influence of load fluctuations on the PLL circuit 14 side can be further reduced, and more stable transmission processing and reception processing can be performed.

The buffer circuit 2 connected to the receiving system
6 and the buffer circuit 27 connected to the transmission system may be controlled by the power supply control circuit 61 at the same time. That is, the control shown in FIG. 2B and the control shown in FIG.
It is also possible to create a control signal for performing the control shown in (1) at the same time and to operate both buffer circuits 26, 27 at the same time by this control signal. By doing so, the configuration for controlling the buffer circuit becomes simple.

In the above embodiment, the buffer circuit 26,
27 is activated about 1 msec before the timing of activating the receiving unit 10a and the transmitting unit 10b, but it may be activated at least for a period necessary for stabilizing the output frequency of the PLL circuit 14. . In practice, for example, it is preferable to operate from several hundreds of microseconds to several milliseconds.

The operation of other circuits may be controlled by a control signal for controlling the operation timing of the receiver 10a or a control signal for controlling the operation timing of the transmitter 10b. For example, the control signal for controlling the operation timing of the receiving portion 10a, the detection circuit 1 performs demodulation processing
The operation of 9 may be controlled.

Furthermore, in the above-described embodiment, the present invention is applied to a cordless telephone that performs digital communication, but it is needless to say that it can be applied to a communication device of a time division transmission / reception system such as a TDMA system applied to other communication systems.

[0037]

According to the present invention, the power supply of the buffer circuit is turned on for a predetermined period before the start of transmission and the start of reception. When transmission and reception start, the output of the frequency generation circuit is stable, and stable transmission and reception can be performed in a time division manner. Therefore, a buffer circuit can be configured with a small number of stages of amplifiers, the circuit configuration can be simplified, and transmission processing at a stable frequency can be performed by operating only a few buffer circuits configured with a minimum number of circuits. Reception processing can be performed, and power consumption required for transmission and reception can be reduced.

Further, in this case, the mixer for mixing the frequency signal with the transmission signal in the transmission circuit and the mixer for mixing the frequency signal with the reception signal in the reception circuit are operated a predetermined period before the transmission / reception start timing. , More stable transmission and reception processing will be performed.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a timing diagram showing a power control state according to an embodiment.

FIG. 3 is an explanatory diagram showing a communication method.

FIG. 4 is a block diagram showing an example of a conventional transmission / reception device.

FIG. 5 is a configuration diagram showing an example of a slot configuration of transmission data.

[Explanation of symbols]

10 Transmission / reception processing circuit 10a receiver 10b transmitter 14 PLL circuit (phase locked loop circuit) 26,27 buffer circuit 60 Central control unit (CPU) 61 Power supply control circuit

Claims (2)

(57) [Claims] 1. A transmission circuit that modulates and transmits a transmission signal at a predetermined frequency, a reception circuit that demodulates a reception signal that is modulated at a predetermined frequency, and a frequency generation circuit that generates a signal of the predetermined frequency. , connected between the frequency generating circuit and the transmitting circuits, the transmission buffer circuit to reduce the load variation, is connected between the frequency generating circuit and the receiving circuit,
A receiving buffer circuit for reducing load fluctuations, and a transmitter / receiver of a time division transmission / reception system that intermittently performs transmission on the transmission slot by the transmission circuit and reception on the reception slot by the reception circuit at different timings And
At least the above transmission buffer circuit and reception buffer
Power supply to the circuit
From the start to the end of the transmission slot.
The first control signal for putting the communication circuit in the power supply state and the transmission from the time point before the start of the transmission slot by a predetermined period
Until the end of the slot, the transmission buffer circuit above
The second control signal in the power supply state and the above-mentioned reception from the start time to the end time of the receiving slot.
The third control signal for putting the receiving circuit in the power supply state and the reception from the time point before the start of the reception slot by a predetermined period
Until the end of the slot, the receive buffer circuit above
A power supply that generates a fourth control signal that remains in the power supply state
A time-division transmission / reception type transmission / reception device provided with a control circuit . 2. A frequency signal from the transmission buffer circuit.
Power supply to the mixer in the transmission circuit
The supply is controlled by the second control signal, while
The frequency signal from the receiving buffer circuit is supplied,
The power supply to the mixer in the receiving circuit is the fourth
Transceiver for division duplex scheme when claim 1, wherein you so that is controlled by a control signal.