JP3392657B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which stores information by utilizing a change in magnetic resistance.

[0002]

2. Description of the Related Art Today, semiconductor memories are used in main memory of large computers, personal computers, home appliances,
It is also used everywhere, including mobile phones. Volatile DRAM (Dynamic RA) is a type of semiconductor memory.
M), SRAM (StaticRAM), non-volatile MROM
(MaskROM), Flash E2PROM (Electrically E
rasable Programmable ROM) is on the market. Especially, although DRAM is a volatile memory,
Its low cost (cell area is 1 / compared to SRAM
4) It is excellent in terms of high speed (Flash E2PROM) and currently occupies most of the market.

Rewritable and non-volatile Flash E2PR
The OM can be turned off, but the number of rewrites (W
(/ E number of times) is as small as about 10 ⁶ and the writing time also takes about microseconds. Furthermore, due to problems such as the need to apply a high voltage (12V to 22V) at the time of writing, the market is not as open as that of DRAM.

On the other hand, a ferroelectric capacitor (ferroelectric capacitor)
F of non-volatile memory using odielectric capacitor)
A RAM (Ferrodielectric RAM) has been advantageous since it was proposed in 1980, it is non-volatile, has a large number of rewrites of 10 ¹² , has a read / write time of about DRAM, and can operate at 3V to 5V. Because there is
Each storage device manufacturer is developing it. However,
When the number of rewrites is 10 ¹² and the cycle time is 100 ns, (100 ns × 10 ¹² ) / (60 * 60 * 24 seconds)
= 1.15 days. Under the present circumstances, unless the number of rewrites is 10 15 or more, continuous operation cannot be performed for 10 years or more and the memory cannot be used as a main memory such as a DRAM.

On the other hand, in recent years, GMR (Giant Magnet)
toResistive) Magnetoresistance of film etc. (MagnoResistive)
A non-volatile semiconductor memory device utilizing the effect has been developed (JL Brown et al, IEEE Trans. Of Compon
ents Packaging, and Manufacturing Technology-PART
A, Vol. 17, No. 3, Sep., 1994., Y. Irie et a
l., Japanese Journal of Applied Physics Letter, Vo
l.34, pp.L415-417, 1995., DD Tang et al., IEE
E InterMAG'95, AP03, 1995 etc.). A storage device utilizing such a magnetoresistive effect has advantages such as non-destructive reading, high-speed operation, and high radiation resistance, and a rewrite count of 10
More than ¹⁵ and DRAM market, all semiconductor memory, and H
There is a possibility that the ardDisk (HD) or the like will be replaced as it is.

FIG. 17A shows a cell plan view of a conventional GMR memory, and FIG. 17B shows a BB 'sectional view of this plan view. As shown in FIGS. 17 (a) and 17 (b),
The GMR film 1 is connected in series to the bit lines 2 and 3, and the word line 4
Are formed on the upper layer of the GMR film 1 so as to cross the bit lines. The GMR film 1 includes a metal artificial lattice, a nanogranular alloy, and a thin ferromagnetic layer 1 as shown in FIG.
1, an exchange-coupling type GMR film including a laminated film of a non-magnetic conductor layer 12 and a ferromagnetic layer 13 and the like. In addition, tunnel type GMR, GMR using oxide magnetic material and CMR (Colo
ssal MR) etc. are also proposed.

Next, the operation of the GMR memory is shown in FIG.
The exchange coupling type GMR film shown in FIG. The thickness of each layer is 3.0 μm for the ferromagnetic layers 11 and 13 and 2.0 μm for the non-magnetic layer conductor layer 12, which is thinner than the electron mean free path l.
The spins of the ferromagnetic layers 11 and 12 that sandwich the non-magnetic conductor layer 12 from above and below have spins in opposite directions due to exchange interaction in a zero magnetic field. And FIG. 18 (b)
The spin direction is changed by the magnetic field due to the word line current shown in FIG. 18 and the magnetic field due to the bit line current shown in FIG. In FIGS. 18 (b) and 18 (c), a dot and a circle indicate the current direction from the back side to the front side of the paper, and a circle indicates the opposite direction. The arrow indicates the current magnetic field. According to Ampere's right-handed screw law, the magnetic field due to the word line current acts on the two ferromagnetic layers 11 and 13 of the GMR film 1 in parallel with the bit lines. The magnetic field due to the bit line current is parallel to the word line GMR
It acts on the ferromagnetic layers 11, 13 of the film 1. The electric resistance of the GMR film is high when the spin directions of the ferromagnetic layers are changed so that the spin directions of the ferromagnetic layers 11 and 13 are opposite to each other, and when the spin directions are the same, the electric resistance becomes low. This resistance change is determined only by the relative directions of the spins on both sides,
It does not depend on the absolute directions of spins on both sides (isotropic). G
The MR memory reads write information based on such a change in resistance.

The GMR film 1 has a structure shown in FIGS.
(B) and spin valve type G as shown in FIG. 16 (c)
MR films have been proposed. FIG. 16A shows an exchange coupling type G.
An MR film is shown. This film is a ferromagnetic layer 23 (C
One of o, NiFe, CoFe, and NiFeCo is a main constituent element. ), The non-magnetic conductor layer 22 (Co,
One of Ag and Au is a main constituent element. ) And the ferromagnetic layer 21 (Co, NiFe, CoFe, NiF)
One of e and Co is a main constituent element. ) Is a laminated body. In the example of this type of data storage method, spins are provided in opposite directions in a low magnetic field, which is "1" data, and spins in the same direction above a saturation magnetic field are "0" data. As another storage method, the ferromagnetic layers 21 and 22 are provided with spins in the direction opposite to the current direction of the word line, and this is set as "0" data, and a large current is passed through the word line to cause both ferromagnetic layers to flow. Current is directed to the bit line so that a rotating magnetic field is generated in the direction opposite to the spin direction facing in the opposite direction, and the spin of the upper and lower ferromagnetic layers is rotated in the spin direction opposite in absolute direction. Is inverted to obtain "1" data. The spin is not simply reversed by the rotating magnetic field, but is reversed only when the combined magnetic field of the magnetic field of the word line current and the magnetic field of the bit line current exceeds the energy required for the reversal. In reading, first, a current smaller than that in writing is made to flow in the direction opposite to the word line direction, and the directions of both spins are directed to the same bit line direction. Next, as in the case of writing "1" data, a bit line current is caused to flow in the direction in which a rotating magnetic field is generated. At this time, if the data is "1", the spin direction and the rotating magnetic field are in the same direction, so the spins are directed in opposite directions in the word line direction, and as a result, the resistance of the nonmagnetic conductor film becomes high. In the case of “0” data, the spin direction and the rotating magnetic field are different directions, so that the force of both spin directions due to the word line current is directed toward the same bit line direction (the word line current is small, so there is no inversion). ). As a result, the resistance of the bit line is low (JL Brown et al, IEEE Trans. Of Co
mponents Packaging, and Manufacturing Technology-P
ART A, Vol. 17, No.3, Sep., 1994.).

FIG. 16 (b) shows the structure of the non-bonded spin valve film, which is characterized by the soft magnetic layer (Ni) under the conductor layer.
Fe (Co)) operates independently of other layers. The film shown in FIG. 16B is a soft magnetic layer (Ni
Fe (Co)) 26, non-magnetic conductor layer (Cu) 25, and
(Semi) hard magnetic layer (CoPt) 24 is a laminated film,
The magnetic field strength for reversing the spin direction of the (semi) hard magnetic layer 24 is large, and the magnetic field strength for reversing the spin direction of the soft magnetic layer 26 is small (Y. Irie et al., Japanese Journal of Ap.
plied Physics Letter, Vol.34, pp.L415-417, 1995.
etc). Therefore, in FIG. 16B, for example, when a large word line current is passed from the back side of the paper to the front side, the (semi) hard magnetic layer stores “0” data, and a large word line current is passed from the front side to the back side of the paper. Is flowed, the (semi) hard magnetic layer stores "1" data. At the time of reading, for example, in the case of “0” data, when a small word line current is passed from the front side to the back side of the paper, the soft magnetic layer 26 has a spin opposite to that of the hard magnetic layer 24, and the resistance becomes high. In the case of "1" data, the soft magnetic layer 2
6 and the hard magnetic layer 24 have the same spin and have low resistance. This difference in resistance value is read out as recording information.

FIG. 16C shows an example of another non-bonded spin valve film. This film is a soft magnetic layer (NiF
e (Co)) 30, non-magnetic conductor layer (Cu) 29, soft magnetic layer (NiFe (Co)) 28, and antiferromagnetic layer (FeM)
n) a laminated body composed of 27. The soft magnetic layer 28 is strongly connected to the antiferromagnetic layer 27 by exchange coupling and has a fixed spin. On the other hand, in the soft magnetic layer 30, spins are inverted by an external magnetic field, and information is stored by spin inversion and non-inversion (D.
D. Tang et al., IEEE InterMAG'95, AP03, 1995
etc).

Such a GMR memory has not been put to practical use due to the following problems. This is the current G
In the MR film, a large current of 100 mA to several A is applied to the word line, and a large magnetic field causes a change rate of magnetoresistance (1 at room temperature).
This is because the current consumption increases although it is possible to earn (such as 00%). In particular, since there is a distance difference between the word line and the GMR film and between the bit line and the GMR film, the magnetic field due to the word line current becomes weaker than the magnetic field due to the bit line, and a large current is required for the word line. In the current state, if a material having a high sense of resistance and a high resistance change rate (high MR rate), which is indispensable for producing a highly reliable LSI, is used, a large word line current needs to flow in the chip. If a plurality of word lines are selected, a larger current consumption will flow, and there is a big drawback that it is far from practical use. The above problem is caused by the magnetic field [O
e] and the MR change rate (%). Current G
In the MR film, the change rate is high but the required magnetic field is large (shown by the line A), or the change rate is low but the required magnetic field is low (shown by the line B). There is no ideal film with high MR ratio.

Further, in the prior art, when a current is applied to a selected word line to generate a magnetic field, the magnetic field also affects the memory cells of the adjacent non-selected word line. When the data is destroyed and the reverse data of the selected cell is written in the adjacent cell at the time of reading the data, it works to weaken the resistance change of the selected cell. This becomes remarkable as the miniaturization progresses.

[0013]

As described above,
In addition to the advantages of non-destructive read, high-speed operation, high radiation resistance, etc., the conventional GMR memory is capable of rewriting 10 ¹⁵ or more and continuous operation for 10 years. If a material with a high sense of sensitivity and high resistance change rate (high MR rate) is used, it is necessary to pass a large word line current in the chip. Furthermore, if a plurality of word lines are selected, a further large current consumption will occur. There were major drawbacks that made it far from practical use. or,
As miniaturization progresses, there is a drawback that adjacent cell data tends to be destroyed by the leakage magnetic field.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a memory device which stores information by a change in magnetic resistance, which has low power consumption and high sense sensitivity. And

[0015]

[Means for Solving the Problems]

(Summary) In order to solve the above problems, the first aspect of the present invention is to provide a plurality of word lines, each of which is composed of a plurality of bit lines and a plurality of parallel word line layers that intersect with the bit lines and are connected in series. Provided is a semiconductor memory device, comprising: a line; and a plurality of memory cells each having a magnetoresistive film formed in a region where the bit line and the word line cross each other and connected in series to the bit line. To do.

In order to solve the above problems, a second aspect of the present invention is to provide a plurality of bit lines and a plurality of layers of word lines which intersect with the bit lines and are supplied with current from the same current source. A plurality of word lines made of layers, and a plurality of memory cells each having a magnetoresistive film formed in a region where the bit lines intersect the word lines and connected in series to the bit lines. A characteristic semiconductor memory device is provided.

Preferred configurations in the first and second inventions are shown below. a) The current directions of the plurality of word line layers formed in either the upper layer or the lower layer of the magnetoresistive film are the same. b) The current direction of the word line layer formed in the upper layer of the magnetoresistive film and the current direction of the word line layer formed in the lower layer of the magnetoresistive film are opposite to each other. c) The word line layer formed in the upper layer of the magnetoresistive film and the word line layer formed in the lower layer of the magnetoresistive film are connected at one end of a cell array arranged in the word line direction. d) A plurality of word lines composed of an upper word line layer and the lower word line layer are alternately connected to word line drive circuits at both ends of the cell array. e) A first word line layer is formed on an upper layer of the magnetoresistive effect film, a second word line layer is further formed on an upper layer of the first word line layer, and a third word line layer is formed on a lower layer of the magnetoresistive effect film. A word line layer is formed, and a fourth layer is formed below the third word line layer.
Word line layer is formed, the first word line layer and the fourth word line layer are connected at one end of the cell array, and the second word line layer and the fourth word line layer are connected to each other. Connected at the ends. In order to solve the above problems, a third aspect of the present invention is to provide a plurality of bit lines, a plurality of word lines intersecting with the bit lines, a plurality of word line drive circuits for driving the word lines, and A plurality of memory cells each having a magnetoresistive film formed in a region where a bit line and the word line intersect with each other and serially connected to the bit line, and a potential at the other end of the word line at the cell array end in the word line direction. A first power supply line that supplies a lower potential and a second power supply line that is connected to the first power supply line. At one end of another cell array, the word line has a higher potential than the other end. There is provided a semiconductor memory device including a second power supply line for supplying a potential.

In order to solve the above problems, a fourth aspect of the present invention is to provide a plurality of bit lines, a plurality of word lines intersecting with the bit lines, and a plurality of word lines for driving the word lines. A plurality of memory cells each including a drive circuit, a plurality of magnetoresistive films formed in a region where the bit line and the word line intersect, and connected in series to the bit line, and one end of a cell array in the bit line direction. Is a first power supply line that supplies a potential lower than the potential of the other end and a second power supply line that is connected to the first power supply line. One end of the bit line of another cell array and the other end And a second power supply line that supplies a potential higher than the potential of the semiconductor memory device.

In order to solve the above problems, a fifth aspect of the present invention is to provide a plurality of bit lines, a plurality of word lines intersecting with the bit lines, and a plurality of word lines for driving the word lines. A driving circuit and a plurality of memory cells each having a magnetoresistive film formed in a region where the bit line and the word line intersect each other and serially connected to each of the bit lines are provided. There is provided a semiconductor memory device, comprising: the word line through which a current flows and a wiring through which a reverse current smaller than the positive current flows between the word line adjacent to the word line.

In order to solve the above problems, a sixth aspect of the present invention is to provide a plurality of bit lines, a plurality of word lines intersecting with the bit lines, and a plurality of word lines for driving the word lines. The word is provided with a drive circuit and a plurality of memory cells formed in a region where the bit line and the word line intersect and provided with a magnetoresistive film connected in series to the bit line. A semiconductor memory device is provided, in which a reverse current smaller than the positive current flows through the other word line adjacent to the line.

In order to solve the above problems, a seventh aspect of the present invention is to provide a plurality of bit lines, a plurality of word lines intersecting with the bit lines, and a region where the bit lines intersect with the word lines. And a magnetoresistive effect film connected in series with the bit line, the horizontal projection of the word line having a region overlapping with the bit line.

(Operation) According to the first and second aspects of the present invention,
The magnetoresistive film is affected by the combined magnetic field generated by the currents in the plurality of word line layers by the plurality of word lines. Therefore, a large magnetic field that is almost proportional to the number of layers of word lines can be obtained with respect to the memory device using the conventional magnetoresistive film using one layer of word lines. Then, if a plurality of word line layers are connected in series by connecting at cell ends and the like and the currents flowing from the same current source are used, the number of word line layers can be made almost equal to that of the conventional memory device. It is possible to generate a proportionally large synthetic magnetic field. Therefore, a large magnetoresistance change rate can be realized with a small word line current and a small chip consumption current.

According to the third aspect of the present invention, a plurality of magnetoresistive effect films are formed in an array between the plurality of layers of word lines formed in parallel with each other, and the magnetoresistive effect films are located at the center of each other. Currents flow in opposite directions to the opposing word lines. Then, by connecting the power supplies of the plurality of word line drive circuits in different cell arrays in series, the current consumption is not increased even if the word lines of the plurality of cell arrays are simultaneously operated,
The power consumption of the entire plurality of cell arrays can be suppressed.

According to the fourth aspect of the present invention, if the power supplies of the bit line drive circuits of different cell arrays are connected in series, even if the bit lines of a plurality of cell arrays are operated at the same time, the current consumption does not increase, The power consumption of the chip can be suppressed.

According to the fifth aspect of the present invention, the influence of the leakage magnetic field on the adjacent memory cells due to the magnetic field flowing in the selected word line is controlled by the control line arranged between the word lines and the selected word line. The current can be weakened by passing a current in the opposite direction and generating a magnetic field in a direction that weakens the magnitude of the leakage magnetic field.

According to the sixth aspect of the present invention, the influence of the leakage magnetic field on the adjacent memory cell is caused by the magnetic field flowing in the selected word line, and a slight current in the opposite direction to the selected word line is applied to the adjacent word line. The leakage can be weakened by generating a magnetic field in the direction of weakening the magnitude of the leakage magnetic field.

According to the sixth aspect of the present invention, the distance between the word line and the magnetoresistive film can be made shorter than before.
Further, in the above-mentioned present invention, it is optimal to use a material or structure which has a large rate of change in magnetic resistance but consumes a large amount of current and which is desired to reduce the amount of current consumed. For example, there is a GMR film. Among them, the exchange coupling type GMR film is a film in which ferromagnetic layers of Co, Ni, Fe and the like and alloys thereof are formed on the upper and lower layers of a non-ferromagnetic conductor layer of Cu, Au, Ag and Cr. The spin-valve type GMR film is a (semi) hard magnetic layer such as CoPt on one side of a non-ferromagnetic conductor layer such as Cu, Au, Ag and Cr, and an N on the other side.
It is a film in which a soft magnetic layer such as iFe or NiFeCo is formed. As another spin valve type GMR film, Cu,
NiF on one side of the non-ferromagnetic conductor layer of Au, Ag, Cr, etc.
e, a soft magnetic layer such as NiFeCo and an antiferromagnetic layer such as FeMn, and a soft magnetic layer such as NiFe and NiFeCo formed on the other side. Also, a tunnel type GMR in which ferromagnetic layers such as Fe are connected to both sides of a non-ferromagnetic insulating layer such as Al2O2.
Film, CMR (Colos containing Pr, Sr, Mn, O, etc.)
sal Magneto Resistive) membrane.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1A is a sectional view of a memory cell for explaining a semiconductor memory device utilizing a magnetoresistive effect according to a first embodiment of the present invention. Also, FIG. 1 (b)
Is a plan view showing a plurality of memory cells adjacent to each other, and FIG. 1C shows a cross-sectional view of the cell array in the word line direction and a word line drive circuit.

In the present embodiment, FIGS. 1A and 1B are used.
As shown in FIG. 3, the bit line 31, and the upper layer word line 32 and the lower layer word line 33 formed in the upper and lower layers, respectively.
Are three-dimensionally crossed, and a GMR film 34 having both ends connected to the bit line 31 is formed in the crossing region. That is, the upper layer word line 32 is formed immediately above the GMR film 34, and the lower layer word line 33 is provided immediately below. The upper and lower word lines 32 and 33 are GM.
The R film 34 and the interlayer film are formed so as to overlap each other in the vertical direction of the main surface of the substrate. The interlayer film electrically insulates between the upper and lower word lines 32 and 33 and between these and the GMR film 34 and the bit line 31.

Next, the upper word line 32 of this memory cell
In addition, for example, a current is passed from the front side of the paper to the front side (in the circle), and a current is passed to the lower word line 33 from the front side of the paper to the back side (in the circle). Then, the magnetic field generated by the current in the upper layer word line 32 and the lower layer word line 33 is directed to the right direction in the figure according to Ampere's right-handed screw law, and as a result, the magnetic fields produced by the two layers of word lines are aligned with the cell. A synthetic magnetic field is generated and acts on the GMR film 34. This combined magnetic field has a magnetic field strength about twice that of a magnetic field generated by a single-layer word line (prior art) when the current amount is the same.

Here, for example, as shown in FIG.
When the upper and lower word lines 32 and 33 are extended from the left end cell 36a of the cell array to the right end cell 36l and both are connected in series by the contact 37 at the left end of the cell array, the current consumption is the same as the conventional one, but the two layer word lines are used. The composite magnetic field of the current flowing through the line can be generated about twice as much as the conventional one.

The voltage is applied to each layer by applying the upper word line 32.
Is applied with a voltage of V1 from the word line drive circuit 35, and the lower layer word line 33 is connected to the potential of V2 from the word line drive circuit 35. When V1> V2, the upper word line 32
, A current flows leftward on the paper, and a current flows rightward on the lower word line 33. As an example of V1> V2, V1 = Vcc and V2 = 0V may be used, or V2
As an example of> V1, V2 = Vcc and V1 = 0V may be used, and V1 and V2 may be set to arbitrary potentials so as to satisfy the above relationship in order to flow a desired current. The difference between the upper word line and the lower word line when writing / reading data is
When writing, V1-V2 is increased, and when reading, V1-V2
If V2 is set to be small, current consumption can be suppressed.

According to this embodiment, the same required magnetic field can be generated with a smaller word line consumption current. Further, even if a material or structure having a high sense resistance and a large magnetoresistance change rate is used, an LSI with low current consumption can be realized, and low power consumption and improvement in sense sensitivity can both be achieved.

The present embodiment is not limited to that shown in FIG. 1C, but other structures can be used as long as the layers are connected in series.
Morphology is also included. In this embodiment and other embodiments described below, the GMR (Giant MagnetoResisto) described above is used.
An exchange-coupling type GMR film in which ferromagnetic layers of Co, Ni, Fe, etc. and their alloys are connected to both sides of a non-ferromagnetic conductor layer of Cu, Au, Ag, Cr or the like, or Cu, Au,
A spin valve type GMR film in which a (semi) hard magnetic layer such as CoPt is connected to one side of a non-ferromagnetic conductor layer such as Ag or Cr and a soft magnetic layer such as NiFe or NiFeCo is connected to the other side, or C
On one side of the non-ferromagnetic conductor layer of u, Au, Ag, Cr, etc., N
Examples include a soft magnetic layer such as iFe and NiFeCo, an antiferromagnetic layer such as FeMn, and a spin valve type GMR film in which a soft magnetic layer such as NiFe and NiFeCo is connected to the other side. Further, as the tunnel type GMR film, there is a film in which a ferromagnetic layer such as Fe is connected to both sides of a non-ferromagnetic insulating layer such as Al2O2.
In addition to the GMR film, there is a film CMR (Colossal MagnetoResisto) containing Pr, Sr, Mn, O, etc. as a film. It is also possible to use permalloy or the like having an AMR effect that exhibits magnetic anisotropy in one direction.

(Second Embodiment) The second embodiment of the present invention will be described below.
The semiconductor memory device of the embodiment will be described. 2A shows a memory cell sectional view, and FIG. 2B shows a word line direction sectional view of the cell array and a word line drive circuit. In the present embodiment, the first and second word line layers 43a and 43b, the GMR film 45 formed below these layers, and the first and second word line layers 44a and 44b formed below these layers are formed. It is provided. The bit line 42 includes four word line layers 43a and 43.
B, 44a and 44b are crossed, and the GMR film 45 is formed at this crossing portion.

Next, the magnetic field generated in the memory cell 41 will be described. A current in the same direction is applied to the first and second word line layers 43a and 43b of the memory cell 41, and
By passing a current in the direction opposite to that of the first and second word line layers to the fourth and fourth lower word lines 44a and 44b, even if the current amount of one word line is the same as the conventional one, the combined magnetic field As a result, a magnetic field that is approximately four times that of the conventional one can be generated, and the GMR film 45 is affected by this composite magnetic field. The resultant magnetic field increases in proportion to the number of layers.

Next, the connection of each word line layer will be described. In this embodiment mode, the first word line layer 43a and the fourth word line layer 44b, the second word line layer 43b and the fourth word line layer 44a, and the second word line layer 43b and the fourth word line layer 43a. As shown in FIG. 2B, the line layer 44a is connected in series by the contacts 46a, 46b, 46c at both ends of the cell array. Therefore, even if the current consumption is the same as the conventional one, a composite magnetic field that is four times larger can be realized, and an LSI with a current consumption lower than that of the first embodiment can be realized. Also, G
The MR film 45 makes it possible to apply a high magnetoresistance change material.

The method of connecting the layers described above in series is not limited to that shown in FIG. The voltages V1 and V2 applied to the word lines may be the same as in the first embodiment, and detailed description thereof will be omitted here.

(Third Embodiment) Next, a third embodiment of the present invention will be described. When the word lines below and above the magnetoresistive film are formed in multiple layers as in the second embodiment described above, if the word line pitch is defined by the minimum processing dimension,
The following problems are likely to occur. That is, since the contact 46a is formed, the uppermost layer of the lower word line layer (the third word line layer 44 in the example of the second embodiment).
It becomes difficult to connect a) with the word line drive circuit 57. The third embodiment solves this problem.

In the present embodiment, as shown in FIG. 3, the cell arrays are alternately connected to the left and right word line drive circuits 57 (the word line drive circuits connected to one side are omitted in FIG. 3), and the second contacts are formed. Thus, the above problem is solved by drawing out the word line layer, which is difficult to connect to the word line drive circuit, to the side of the second contact 56b.

At this time, the cell arrays, which are connected symmetrically with the word line drive circuit, are arranged so as to be shifted left and right as shown in FIG. A layer such as the second upper layer word line of the cell array A, which is not connected to the driving circuit, is inside the cell array, and if the first and third contacts are made, the first lower layer word of the cell array B formed as a phase object. The lines are shifted by 1 pitch in the cell array A direction.

The arrangement of the word lines in this embodiment can be applied to a cell array in which word lines of three layers or more which require contacts for series connection are formed. (Fourth Embodiment) Next, a fourth embodiment of the present invention will be described.

As described above, the method of storing "1" and "0" data in the exchange-coupling type GMR film by using the word line of one layer is described in JL Brown et al, IEEE Trans.
Components Packaging, and Manufacturing Technolog
y-PART A, Vol. 17, No. 3, Sep., 1994.). In this storage method, the word line current flows in the opposite direction during reading and writing.

On the other hand, in the present invention using a multi-layered word line, the word line currents at the time of reading and writing can be made to flow in the same direction, and the spin directions of both ferromagnetic layers are set to the same bit line direction. It is possible to operate as a storage device even when facing toward. Similar to the case where "1" data is written by the method described above, a rotating magnetic field due to the bit line current is generated in the direction opposite to the spin direction of both ferromagnetic layers. At this time, if the data is “1”, the spin direction and the rotating magnetic field are in the same direction.
The spins are directed in opposite directions in the word line direction regardless of the word line current. As a result, the resistance of the bit line becomes high. In the case of "0" data, the spin directions of both ferromagnetic layers are different from the rotating magnetic field, so that the force of the spin directions of both ferromagnetic layers toward the same bit line direction due to the word line current is increased (word line current). Because it is small, it is not inverted).
As a result, the resistance of the bit line becomes low, and the memory cell operation becomes possible. That is, the word line current can be read / written in one direction. Therefore, as shown in FIG. 4, a plurality of word line drive circuits are arranged at one end of the cell array, and one end of each word line connected to each cell array, for example, the end of a word line layer for applying a V2 potential is shared. Can be converted. For example, the third word line layer is made common before the second contact and is drawn out in the bit line direction,
It is pulled out of the cell array.

When this embodiment is applied to a cell structure in which word lines of a plurality of layers are connected in series in the upper layer and the lower layer as in the second embodiment by contacts, the V2 potential is common to each word line on the ground side. Since it can be performed, the word line drive circuit and the word line can be configured with the minimum design rule.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described with reference to FIGS. 5 (a) and 5 (b). In the present embodiment, as shown in FIG. 5A, the word lines in the upper layer of the GMR cell 71 are two layers (first word line 73a and second word line 73b), and a current in the same direction is applied to each layer to The feature is that the combined magnetic field doubles the magnetic field of the conventional one-layer word line. In this embodiment, the first
Thus, unlike the fourth embodiment, the word line layer is not provided below the GMR film.

As described above, in order to pass currents in the same direction in forming the word line layer formed only on one of the upper side and the lower side of the GMR film, they cannot be connected in series. Therefore, in this embodiment, the word line layer is arranged as shown in FIG. The first word line layer 73a to which the voltage V12 is supplied from the word line drive circuit 75a at the right end of the cell array A formed in parallel with the word line layer is extended to the left end of the cell array. Only the switch Q1 connected to the selected first word line layer is turned on to connect to the first power supply line 76 common to each word line. The first power supply line 76 is arranged in the bit line direction and extends to the right end of the cell array in units of several word lines. Although it intersects with the bit line 72 by being stretched, no problem occurs unless a memory cell is arranged at this intersection. First power line 76
Is stretched in the bit line direction at the right cell array edge,
The second word line 73b of each cell array via the switch
Connected to. By turning on the selected word line switch Q2, as a result, the second word line current can be made to flow in the same direction below the first word line. The left end of the second word line is connected to the drive circuit 75b that applies the V2 potential.

As described above, it can be said that the same required magnetic field can be generated with a smaller word line consumption current by arranging a plurality of layers of word lines connected in series to the cell array. Further, even if a material or structure having a high sense resistance and a large magnetoresistance change rate is used, an LSI with low current consumption can be realized, and low power consumption and improvement in sense sensitivity can both be achieved.

(Sixth Embodiment) Next, the sixth embodiment of the present invention will be described.
Will be described. Similar to the fifth embodiment, this embodiment is another arrangement of the word lines when the cell structure is adopted in which a plurality of word lines are formed on one side of the upper or lower layer of the GMR film. As described in the fourth embodiment,
Since reading and writing can be performed by the word line current flowing in one direction, the drive circuit at one end (the left end in FIG. 6) of the cell array can be omitted and the V2 power supply common to each cell array can be connected. At the other end (right end in FIG. 6), the word line drive circuit 85 that supplies V1 is shared by a plurality of cell arrays. Using the word line drive circuit 85 as a switch,
An arbitrary word line can be selected through a switch such as 3. WS0-1 and WSn-1 indicate word line selection control signals.

(Seventh Embodiment) Next, the seventh embodiment of the present invention will be described.
Will be described. In the above-described first to sixth embodiments, there is a problem that the resistance of the entire wiring increases in proportion to the number of layers by connecting multiple word line layers in series. When the wiring resistance of each word line layer is small, there is no problem, but when the wiring resistance is large, voltage drop and RC delay become problems. The above problem can be solved by performing word line division as in this embodiment.

In this embodiment, as shown in FIG. 7, the cell array is divided into a plurality of sub-arrays 91, and a main row decoder is provided at the cell array end.
92, a sub row decoder 93 is arranged at the end of each sub array 91. The main row decoder 92 and the sub row decoder 93 are connected to the main word line (Main Word-Lin).
e) The multilayer word line of the present invention is applied to the word line which is connected by 94 and is arranged from the sub row decoder 93 to the sub array 91.

By dividing the decoder in this way,
Even if the series-connected multilayer word lines of the present invention are applied, the voltage drop and the increase in RC delay can be suppressed.

(Eighth Embodiment) Next, an eighth embodiment of the present invention will be described. In the conventional MRAM, when a plurality of word lines of a plurality of cell array blocks are simultaneously selected like a DRAM, a current consumption proportional to the number of selected word lines is generated. Even if one word line is selected, it is fatal to a GMR memory in which a large amount of current flows.

In the present embodiment, even if a plurality of word lines in a plurality of cell arrays are selected at the same time, the current consumption can be reduced to the same level as when one word line in one cell array is selected. or,
According to this embodiment, a plurality of word lines can be activated with low power consumption, and a large number of bit line data can be input / output.

Two cell array blocks A shown in FIG.
The eighth embodiment will be described by taking B as an example. The row decoder B is connected to the cell array B, and further connected to the row decoder A and the current used for driving the arbitrary word line 102B of the cell array B is used for driving the arbitrary word line 102A of the cell array A. This connects the ground side power supply of the final stage driver of the word line drive circuit of the row decoder B connected to the cell array B and the power supply side of the final stage driver of the word line drive circuit of the row decoder A to the connection point ( V1 + V2) /
This is achieved by applying 2 [V] (V1 and V2 are voltages supplied from the word line drive circuits 101A and 101B to each cell array). The intermediate power supply of FIG. 8 is (V1 + V2) / 2
It is generated and fixed during standby, and when the memory cell is operating, Q10 is turned off to disconnect from the word line. This prevents inconvenience that a voltage is first applied to the word line of the cell array B and then applied to the word line of the cell array A, and unstable operation due to clock skew is prevented.

As described above, even when a plurality of word lines of a plurality of cell array blocks are selected at the same time according to the present embodiment, the current consumption is about the same as when one word line of one cell array block is selected. Can be suppressed.
Further, as described above, it becomes possible to activate a plurality of word lines, and as a result, it becomes possible to output a large number of word line data to the outside of the chip and input to the inside of the chip.

Although two cell array blocks are used in the above description, the present embodiment can be applied to three or more cell array blocks. (Ninth Embodiment) In a conventional MRAM, when a plurality of bit lines of a plurality of cell array blocks are simultaneously selected like a DRAM, a current consumption proportional to the number of selected bit lines is generated. Even if one bit line is selected, it is fatal to a GMR memory in which a large amount of current flows.

In the present embodiment, even if a plurality of bit lines of a plurality of cell arrays are selected at the same time, the current consumption can be reduced to the same level as when one bit line of one cell array is selected. or,
According to this embodiment, a plurality of bit lines can be activated with low power consumption, and a large number of bit line data can be output outside the chip and input inside the chip.

This embodiment will be described by taking the two cell array blocks shown in FIG. 9 as an example. The current used in the bit line current generating circuit of the cell array B of the two cell array blocks A and B is reused as the current of the bit line current generating circuit of the cell array A. That is, the power supply on the ground side of the final stage driver of the bit line current generation circuit of the cell array B and the power supply side of the final stage driver of the bit line current generation circuit of the cell array A are connected and operated simultaneously.

According to the present embodiment, even when a plurality of bit lines of a plurality of cell array blocks (or a plurality of bit lines of the same cell array) are selected at the same time, the current consumption thereof is
This can be made equivalent to the case of selecting one bit line pair of one cell array block. Further, according to the present embodiment, it is possible to simultaneously activate a plurality of bit lines, and as a result, it is possible to output a large number of bit data outside the chip and input inside the chip.

Next, details of the ninth embodiment will be described with reference to FIG. FIG. 10 shows the memory cell 1 of the cell array A of FIG.
11, word lines WL0 to WL7 connected to the row decoder,
Main bit line BL connected to bit line current generation circuit
0, BL0 ′, BL1, BL1 ′, and then a column decoder for selecting a predetermined bit line are shown.

The rate of change in electric resistance of the GMR film is 5% to 100.
However, if a plurality of cells (for example, n stages) are connected to one bit line, the rate of resistance change becomes 1 / n, which is a problem. So, as shown in FIG.
The cells of four stages (111a, 111b, 111c, 111d) are connected and connected to the main bit line BL1 via the transistor Q12 of the column control line CSLn-2 to be selected. BL1 is performed through transistors Q15 and Q16. Further, since the GMR memory consumes a large amount of current, the temperature rises and the cell resistance changes.

Therefore, the bit lines (BL0, BL0 ') connected to the non-selected cells adjacent to the selected word line are referred to.
The rence bit line is connected to the sense amplifier circuit and the bit line current generation circuit together with the bit line connected to the selected cell.

FIG. 11A shows details of the bit line current generating circuit of FIG. In FIG. 11A, the bit lines (BLi, BLi ′) pass a current from the bit line i to the bit line i ′, or a bit line i ′ to the bit line for reading / writing data from each other. It is necessary to pass a current through i. It is necessary to provide a circuit for supplying a current from the power supply V3 to the power supply V4 to each one bit line pair (BL0 and BL0 ', BL1 and BL1'). So, from BL0 to BL0 ', B
When a current flows from L1 to BL1 ', the transistor Q1
Turn on 7, Q18, Q19, and Q20. The constant current control is performed by controlling the potential difference between V3 and V4 and the resistor R. In this way, by connecting the power supplies V3 'and V4 of the bit line current generating circuit, it is possible to reduce the current consumption of multiple bit line pairs operating simultaneously to the same level as in the case of one. FIG. 11B shows the sense amplifier of FIG.

Next, the voltage drop in each of the above-described embodiments and the prior art will be quantitatively estimated. FIG. 12 is a diagram used for estimating how much magnetic field is generated in the central portion of the GMR film from the word line. This estimate was made as follows. The cross section of the word line formed in a quadrangle is equally divided into a plurality of parts, and the current of one of the divided regions is calculated. The distance and angle from each divided region to the GMR film are calculated, and the horizontal magnetic field Hx and the vertical magnetic field Hy components are calculated according to Biot-Savart's law (Formula 1). This magnetic field component is applied to all the divided currents and all horizontal magnetic fields H
x and the resultant magnetic field of the vertical magnetic field Hy are as follows. In this estimation, the amount of current passed through each word line layer is unified to 30 mAmps.

13 (a), 13 (b), and 13
(C) shows an example of the prior art. If the distance between the word line 4 having a film thickness of 0.4 μm and the GMR film 1 is 0.6 μm, 75
[Oe] is generated (FIG. 13A). Thickness is 0.2μm
When the distance between the word line 4 and the GMR film 1 was set to 0.6 μm, 81 [Oe] was generated (FIG. 13B). The distance between the word line 4 having a thickness of 0.4 μm and the GMR film 1 is 0.3.
114 [Oe] was generated at μm (Fig. 13).
(C)). Here, 1 [Oe] is about 80 (A / m). As shown in FIG. 13B, when the film thickness of the word line 4 is reduced, the magnetic field slightly increases. This is because the magnetic field is inversely proportional to the distance r from the Biot-Savart equation (Equation 1).
As shown in FIG. 13C, when the distance between the word line 4 and the GMR film 1 is reduced, a larger magnetic field is generated. However, as shown in FIG. 13 (a), FIG. 13 (b) and FIG.
In the configuration of (c), the bit line 2 connected to the GMR film 1 is an obstacle, and the distance cannot be reduced.

13 (e), 13 (f), 13
13 (g) and FIG. 13 (h) show the magnetic field generated by the multilayer word line layer of the present invention. As shown in FIG. 13 (e), the magnetic field becomes nearly double that of the conventional one simply by increasing the number of layers above one layer. FIG.
As shown in FIG. 13F, it is more effective to make the word line layer thinner. As shown in FIG.
When the MR film is brought closer, the magnetic field also increases to 218 (Oe). As shown in FIG. 13 (h), when the word line layers are provided above and below the bit line, a magnetic field twice as large as that in FIG. 13 (a) is generated. From this example as well, it can be seen that the magnetic field becomes extremely large even if one constant current is used in multiple layers.

FIG. 11D shows the magnetic field generated at the center of the ferromagnetic film by the bit line current. Since the distance r is short, a magnetic field of 107 (Oe) can be generated with only 5 mA. You can see how the efficiency of the magnetic field generated by the word line is poor.

(Tenth Embodiment) Next, the first embodiment of the present invention
No. 0 embodiment will be described. 13 (a) and 13
(B) and FIG. 13 (c) show the GMR film 1 in the conventional structure.
The bit line 2 connected to the word line 4 and the GMR film 1
The distance between cannot be shortened. As described above, this distance may be shortened to increase the magnetic field strength.

In this embodiment, as shown in FIGS. 14A and 14B, if the bit line wiring layers, the word line wiring layers are embedded, or the word lines are formed below the bit line layers,
You can get closer.

(Eleventh Embodiment) FIG. 12 shows an eleventh embodiment of the present invention. As memory cells become finer,
If the word line pitch is reduced and the thickness of each layer is not reduced so much, leakage to the non-selected word line 4'next to the selected word line 4 occurs as shown by the black arrow in the conventional structure of FIG. A magnetic field is generated, and there is a concern that data in adjacent cells will be destroyed.
Therefore, as shown in FIG. 15A, if a dummy word line 134 is arranged between the word lines and a reverse current smaller than the word line current is passed, a magnetic field like a white arrow is generated and a black arrow shows. You can almost cancel the magnetic field. This word line may be a dummy line as shown in FIG. 15 (a), or an adjacent word line may be used as shown in FIG. 15 (c). In the case of FIG. 15C, an upward component remains in the composite magnetic field, but G
Since the spin direction of the MR element does not change with respect to the upward direction, this magnetic field has no effect. Thus, when the adjacent word lines are used, as shown in FIG. 15B, cells are arranged at every other intersection of the word line and the bit line,
Further, even when cells are provided at all the intersections of the word lines and the bit lines, the effect can be obtained by passing a slight reverse current to the adjacent cells.

[0072]

As described above in detail, according to the present invention, in a non-volatile memory which stores information by a change in magnetic resistance, a small word line current and a small chip are provided.
A large magnetoresistance change rate can be realized with current consumption, and low power consumption and improved sense sensitivity can both be achieved. Further, it becomes possible to prevent the data destruction of the adjacent cells when miniaturized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a magnetoresistive effect memory cell, a plan view of a plurality of adjacent memory cells, and a cell array cross-sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a view for explaining a second embodiment of the present invention,
A sectional view of a magnetoresistive effect memory cell, and a cell array sectional view.

FIG. 3 is a plan view of a cell array for explaining a third embodiment of the present invention.

FIG. 4 is a plan view of a cell array for explaining a fourth embodiment of the present invention.

FIG. 5 illustrates a fifth embodiment of the present invention,
Sectional drawing of a magnetoresistive effect memory cell, and a word line wiring diagram.

FIG. 6 is a word line wiring diagram for explaining a sixth embodiment of the present invention.

FIG. 7 is a wiring diagram of main / sub decoders and word lines for explaining a seventh embodiment of the present invention.

FIG. 8 is a diagram for explaining an eighth embodiment of the present invention, in which word line wirings related to a plurality of cell arrays, row decoders,
And a configuration diagram of a driving power supply.

FIG. 9 is a configuration diagram of a bit line wiring, a sense amplifier circuit, a bit line current generation circuit, and the like relating to a plurality of cell arrays, for explaining a ninth embodiment of the present invention.

FIG. 10 is a wiring diagram of bit lines and word lines related to a cell array for explaining the ninth embodiment.

FIG. 11 is a view for explaining a ninth embodiment.

FIG. 12 is a sectional view for explaining the effect of the present invention.

FIG. 13 is a view for explaining the effect of the present invention as compared with the related art.

FIG. 14 is a cell cross-sectional view for explaining the tenth embodiment of the present invention.

FIG. 15 is a sectional view for explaining an eleventh embodiment of the present invention, a plan view and a cell sectional view of a conventional technique.

FIG. 16 is a cross-sectional view of various GMR films.

FIG. 17 is a cell plan view and a sectional view for explaining a conventional technique of the present invention.

FIG. 18 is a sectional view of a GMR film for explaining the conventional technique of the present invention, and a diagram showing magnetic fields generated by word lines and bit lines.

[Explanation of symbols]

1, 34, 45, 75, 121, 131. ． ． Dot on GMR film circle. ． ． Current direction from the back side of the paper to the front side. Circle the X. ． ． Current direction from the front side of the paper to the back side. 4, 4 ', 32, 33, 43a, 43b, 44a, 44
b, 53a, 54a, 63a, 64a, 73a, 73
b, 95, 96, 102A, 102B, 122, 13
2,132 '. ． ． Word lines 2, 3, 31, 31a, 31l, 42, 42a, 5
2, 72, 123 ... Bit lines Q11, Q12, Q13, Q14 ,. ． ． Transistor WSi. ． ． Word line selection control signal MWL. ． ． Main word line SWL. ． ． Sub word lines WL, WLi. ． ． Word lines BL, BLi, BLi '. ． ． Bit line CSLi. ． ． Column selection line

Claims (4)

(57) [Claims] 1. A plurality of bit lines, a plurality of word lines intersecting with the bit lines, a plurality of word line driving circuits for driving the word lines, and a region where the bit lines intersect with the word lines. are formed on, the word between each of said bit lines and a plurality of memory cells with a magnetoresistive film to be connected in series provided on the word lines adjacent and to the word lines through which positive current selected Arranged parallel to the line,
A semiconductor memory device, comprising: a wiring through which a reverse current smaller than the positive current flows. 2. A plurality of bit lines, a plurality of word lines orthogonal to the bit lines, a plurality of word line drive circuits for driving the word lines, and a region where the bit lines and the word lines intersect at right angles. A plurality of memory cells each having a magnetoresistive film connected in series to the bit line, the word line being adjacent to a first word line in which a selected positive current flows . 2. A semiconductor memory device characterized in that a reverse current smaller than the positive current flows between the second word lines arranged in parallel with each other. 3. A plurality of bit lines, a plurality of word lines intersecting with the bit lines, a plurality of word line driving circuits for driving the word lines, and a region where the bit lines intersect with the word lines. A plurality of memory cells each having a magnetoresistive film connected in series with each of the bit lines, the selected positive current flowing between the word line and the word line adjacent to the word line. rather smaller than the positive current direction is 1
A semiconductor memory device, comprising: a wiring through which currents different by 80 ° flow. 4. A plurality of bit lines, a plurality of word lines orthogonal to the bit lines, a plurality of word line drive circuits for driving the word lines, and a region in which the bit lines and the word lines are orthogonal to each other. A plurality of memory cells each having a magnetoresistive film connected in series to the bit line, the word line being adjacent to a first word line in which a selected positive current flows . between the second word lines being disposed Te, the semiconductor memory device small rather direction than the positive current, characterized in that the flow 180 ° different currents.