JP3389174B2 - Input protection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input protection circuit against electrostatic discharge.

[0002]

2. Description of the Related Art Conventionally, semiconductor integrated circuits, especially complementary MO
As shown in FIG. 6, the input protection circuit in the S integrated circuit connects the voltage input terminal 2 and the internal circuit 1 through a resistor R1, and connects the gate electrode, the source electrode, and the back gate electrode of the N-channel MOS field effect transistor Q1. Is connected to the low potential power supply Vss, the drain electrode is connected to the voltage input terminal 2, the gate electrode, the source electrode and the back gate electrode of the P-channel MOS field effect transistor Q22 are connected to the high potential power supply Vdd, and the drain electrode is connected to the voltage. It is configured to be connected to the input terminal 2.

A high-potential power supply Vd is applied to the voltage input terminal 2 from the outside.
When the positive static electricity exceeding d is applied, the drain electrode of the P-channel MOS field effect transistor Q22 serves as the emitter electrode, the source electrode serves as the collector electrode, and the back gate electrode serves as the base electrode. The path is conducting and P
Since the source / drain path of the channel MOS field effect transistor Q22 becomes conductive, static electricity is generated by the high potential power supply V
When it is discharged to dd and a negative static electricity exceeding the low potential power supply Vss is applied to the voltage input terminal 2 from the outside,
A drain electrode of the N-channel MOS field effect transistor Q1 serves as an emitter electrode, a source electrode serves as a collector electrode, and a back gate electrode serves as a base electrode.
Further, since the source / drain path of the N-channel MOS field effect transistor Q1 is made conductive, static electricity is discharged to the low potential power supply Vss, and further, the current flowing into the internal circuit 1 is suppressed by the resistor R1, and the internal circuit is protected. To be done.

[0004]

However, for example, the internal circuit 1 is a PROM (programmable read only memory) circuit, and the voltage input terminal 2 is a high potential power source V.
In the case of the voltage input terminal to which the writing power supply Vpp further boosted by dd is connected, the P-channel MOS field effect transistor Q22 becomes conductive and the writing power supply Vp
Since p and the high-potential power supply Vdd are short-circuited, the input protection circuit, as shown in FIG.
The protection transistor on the side had to be removed.

Therefore, the conventional input protection circuit for the voltage input terminal to which the write power supply Vpp is connected has a lower positive electrostatic withstand voltage than a general signal terminal.

It is an object of the present invention to secure a withstand voltage of the voltage input terminal and short-circuit the high potential power supply Vdd even when a voltage higher than the high potential power supply Vdd is applied to the voltage input terminal during normal operation. It is to provide an input protection circuit that does not cause this.

[0007]

According to the structure of the input protection circuit of the present invention, a resistor and a source / drain path are externally supplied.
Voltage input terminal for inputting the voltage
A gate electrode and a back gate connected between the power source and
The electrodes are connected to the high potential power source through the resistor.
Switching the voltage of the field effect transistor and the gate electrode
A switch circuit including:
The switch means is compared by comparing the terminal voltage and the reference voltage.
An input protection circuit comprising: a voltage detection circuit for turning on and off, wherein the gate is provided when the switch means is in an on state.
The voltage of the voltage input terminal is applied to the electrodes .

Further, the first diode and the second diode
And one end of the source / drain path is supplied externally
Connected to the voltage input terminal for inputting voltage to the internal circuit.
The other end of the source / drain path is in the reverse bias direction.
The gate is connected to the high potential power supply through the first diode.
And the back gate electrode is in the reverse bias direction.
2 is connected to the high potential power source via the diode.
Switching the voltage of the field effect transistor and the gate electrode
A switch circuit including:
The switch means is compared by comparing the terminal voltage and the reference voltage.
An input protection circuit comprising: a voltage detection circuit for turning on and off, wherein the gate is provided when the switch means is in an on state.
The voltage of the voltage input terminal is applied to the electrodes .

[0009]

[0010]

[0011] The configuration of the voltage detection circuit when the voltage of the voltage input terminal exceeds the reference voltage, characterized in that said switching means is turned on.

Further, the reference voltage is a voltage obtained by adding a threshold of the field effect transistor to the voltage of the high potential power supply.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an input protection circuit according to an embodiment of the present invention will be described with reference to the drawings. 1 is a configuration diagram of an input protection circuit according to a first embodiment of the present invention, and FIG. 2 is a configuration diagram of a voltage detection circuit of an input protection circuit according to a first embodiment of the present invention. FIG. 3 shows the first of the present invention.
FIG. 6 is an explanatory diagram of a cross-sectional structure of a main part of the input protection circuit of the embodiment. 1 and 3, the same components as those of the input protection circuit of the conventional example shown in FIG. 7 are designated by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 1, the input protection circuit according to the first embodiment of the present invention comprises a discharge circuit 3 and a voltage detection circuit 4.
It consists of and.

The discharge circuit 3 is composed of P-channel MOS field effect transistors Q2 and Q3 and a resistor R2.
The source electrode 23 of the P-channel MOS field effect transistor Q2 is connected to the high potential power supply Vdd, and the gate electrode 21
And the back gate electrode 24 are connected to each other, and further connected to the high potential power supply Vdd via the resistor R2.

The drain electrode 32 of the P channel MOS field effect transistor Q3 is connected to the back gate electrode 34, and the source electrode 33 of the P channel MOS field effect transistor Q3 is connected to the gate electrode 21 of the P channel MOS field effect transistor Q2. It is connected.

P-channel MOS field effect transistor Q
2 functions as an electrostatic discharge element, and is a P-channel MOS
The field effect transistor Q3 functions as a switch means for switching the gate voltage of the P channel MOS field effect transistor Q2.

As an example of the voltage detection circuit 4, as shown in FIG. 2, there is a circuit composed of a voltage comparator 7 and a reference voltage 8. The positive input end of the voltage comparator 7 is connected to the input terminal 5, the negative input end of the voltage comparator 7 is connected to the reference voltage 8, and the output end of the voltage comparator 7 is connected to the output terminal 6.

The reference voltage 8 is a voltage for the low-potential power supply Vss, and the voltage comparator 7 compares the voltage input to the input terminal 5 with the reference voltage 8, and when the voltage at the input terminal 5 is equal to or lower than the reference voltage 8. Output terminal 6 outputs the voltage of high potential power supply Vdd
When the voltage of the input terminal 5 is higher than the reference voltage 8, the voltage of the low potential power supply Vss is output to the output terminal 6.

Here, the reference voltage 8 is set to a voltage (Vdd + Vtp) obtained by adding the threshold Vtp of the P-channel MOS field effect transistor Q2 to the voltage of the high potential power supply Vdd.

The drain electrode 22 of the P-channel MOS field effect transistor Q2 of the discharge circuit 3 is connected to the voltage input terminal 2, and the drain electrode 32 of the P-channel MOS field effect transistor Q3 is one end of the resistor R1 on the internal circuit 1 side. The input terminal 5 of the voltage detection circuit 4 is connected to one end of the resistor R1 on the internal circuit 1 side, and the output terminal 6 is connected to the P-channel MOS field effect transistor Q3 of the discharge circuit 3.
Of the gate electrode 31.

Further, as shown in FIG. 3, the discharge circuit 3 is formed on a P substrate 40 which is a semiconductor integrated circuit substrate,
The P substrate 40 is connected to the low potential power supply Vss.

P-channel MOS field effect transistor Q
2 is formed in the N well 25, the N well 25 has the back gate electrode 24 of the same potential, and the P channel MOS field effect transistor Q3 is formed in the N well 35.
The N well 35 has a back gate electrode 34 of the same potential.

Next, the operation of the input protection circuit according to the first embodiment of the present invention will be described with reference to FIGS. 1, 2, 3, and 4. FIG. 4 is an explanatory diagram of the operation of the input protection circuit according to the first embodiment of the present invention, showing the voltage waveform of each part, the voltage V1 shows the voltage of the voltage input terminal 2, and the voltage V
1'represents the voltage at one end of the resistor R1 on the internal circuit 1 side, voltage V2 represents the voltage of the gate electrode 21 of the P channel MOS field effect transistor Q2, and voltage V3 is the P channel M.
The voltage of the gate electrode 31 of the OS field effect transistor Q3 is shown, the current I1 shows the current flowing through the P-channel MOS field effect transistor Q2, the vertical axis shows the potential, and the horizontal axis shows the time.

Although not shown in the figure, the voltage input terminal 2
Vdd from time t1 to Vpp from time t3 to time t4
(> Vdd), PRO that becomes Vdd after time t6
The write pulse voltage of the M write power supply is input.

First, before time t1, the write pulse voltage is not input, the voltage V1 is Vdd,
Since the input resistance of the internal circuit 1 is high, the voltage drop due to the resistor R1 can be ignored, and the voltage V1 ′ is also Vdd.

Therefore, since the voltage of the input terminal 5 of the voltage detecting circuit 4 is lower than the reference voltage 8 (Vdd + Vtp), the output terminal 6 outputs Vdd, and the voltage V3 also becomes Vdd.
The P-channel MOS field effect transistor Q3 is off.

Further, since the gate electrode 21 of the P-channel MOS field effect transistor Q2 is pulled up to the high potential power supply Vdd by the resistor R2, the voltage V2 is also Vdd.
Therefore, the P-channel MOS field effect transistor Q2 remains off. Therefore, the current I1 is 0.

Next, the write pulse voltage rises at time t1, and the voltage V1 (= voltage V1 ') changes to Vdd at time t2.
When the voltage exceeds + Vtp, the voltage of the input terminal 5 of the voltage detection circuit 4 is higher than the reference voltage 8 (Vdd + Vtp), so that the output terminal 6 outputs the voltage of the low potential power supply Vss and the voltage V3.
Becomes Vss, and the P-channel MOS field effect transistor Q3 is turned on.

Therefore, the voltage V1 (= voltage V1 ') is V
After the time points t3 and t4, which are pp, have passed, and it has descended to Vd again.
Until time t5 when d + Vtp is reached, the voltage V2 is always equal to the voltage V1 ′, and the gate voltage and drain voltage of the P-channel MOS field effect transistor Q2 are always equal.
Never goes on. Therefore, the current I1 is 0.

The reference voltage 8 is set to the voltage (Vdd + Vt
The reason for setting p) is that if the P-channel MOS field effect transistor Q3 does not exist, the voltage (Vdd) is set.
+ Vtp) P channel MOS field effect transistor Q
This is because the gate voltage of the P-channel MOS field-effect transistor Q2 is switched by the P-channel MOS field-effect transistor Q3 with this voltage as a boundary, since 2 is turned on.

Further, after the time t5, the voltage of the input terminal 5 of the voltage detection circuit 4 becomes the reference voltage 8 (Vdd + Vt).
p), the output terminal 6 outputs the voltage of the high potential power supply Vdd again, the voltage V3 also becomes Vdd, and P
The channel MOS field effect transistor Q3 is turned off.

Since the voltage V2 also becomes Vdd, the P-channel MOS field effect transistor Q2 remains off. Therefore, the current I1 is 0.

As described above, after all, until time t2 and after time t5, the gate voltage of the P-channel MOS field effect transistor Q2 is Vdd, so that the P-channel MOS field effect transistor Q2 functions as an electrostatic discharge element. To do.

That is, when a positive static electricity exceeding the high potential power supply Vdd is input to the voltage input terminal 2 with respect to the low potential power supply Vss, the P-channel MOS field effect transistor Q is generated.
The drain and collector electrodes of the parasitic PNP bipolar transistor having the drain electrode 22 of 2 as the emitter electrode, the source electrode 23 as the collector electrode, and the back gate electrode 24 as the base electrode are turned on, and the P-channel MOS field effect transistor Q2 is turned on. As a result of the source-drain path becoming conductive, static electricity is discharged to the high-potential power supply Vdd, and the electrostatic breakdown voltage of the voltage input terminal 2 is secured.

Further, even when the high voltage Vpp exceeding the high potential power supply Vdd is input to the voltage input terminal 2 during the write operation from the time t2 to the time t5, the P channel MOS field effect transistor Q2 which is the electrostatic discharge element is It is always in the off state, and a short circuit does not occur with respect to the high potential power supply Vdd.

FIG. 5 is a block diagram of an input protection circuit according to the second embodiment of the present invention. 5, the same components as those of the input protection circuit according to the first embodiment of the present invention shown in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 5, the input protection circuit according to the second embodiment of the present invention comprises a discharge circuit 13 and a voltage detection circuit 4.

In the discharge circuit 13, a component different from the discharge circuit 3 of the input protection circuit according to the first embodiment of the present invention shown in FIG. 1 is that the resistor R2 is replaced by a diode D1 and a P-channel MOS field effect transistor is provided. This is a portion where a diode D2 is added to the source electrode of Q12.

P-channel MOS field effect transistor Q
The gate electrode and the back gate electrode of 12 are both connected to the cathode electrode of the diode D1, and the anode electrode of the diode D1 is connected to the high potential power supply Vdd.

The source electrode of the P-channel MOS field effect transistor Q12 is connected to the cathode electrode of the diode D2, and the anode electrode of the diode D2 is connected to the high potential power supply Vdd.

The P-channel MOS field effect transistor Q13 is the same as the P-channel MOS field effect transistor Q3 of the discharge circuit 3 of the input protection circuit of the first embodiment of the present invention shown in FIG.

Next, the operation of the input protection circuit according to the second embodiment of the present invention will be described with reference to FIG. Regarding the operation of the P-channel MOS field effect transistors Q12 and Q13 when the write pulse voltage is applied to the voltage input terminal 2, parts different from the operation of the input protection circuit according to the first embodiment of the present invention shown in FIG. , Diodes D1 and D2
Is set to Vd and the P-channel MOS field effect transistor Q13 is in the off state,
The pull-up voltage of the gate electrode and the back gate electrode of the OS field effect transistor Q12 becomes Vdd-Vd,
Diode D for compensating the voltage drop of diode D1
2, the P-channel MOS field effect transistor Q1
The voltage of the second source electrode is Vdd-Vd only.

Therefore, the voltage V11 is the voltage of the voltage input terminal 2, the voltage V11 'is the voltage at one end of the resistor R1 on the internal circuit 1 side, the voltage V12 is the gate voltage of the P-channel MOS field effect transistor Q12, and the voltage V13. Is the gate voltage of the P-channel MOS field effect transistor Q13, and the current I11 is the current flowing through the P-channel MOS field effect transistor Q12, the voltage V11 is equal to the voltage V1 shown in FIG. 1, and the voltage V11 'is also equal to the voltage V1'. , Voltage V12 becomes voltage V2-Vd when P-channel MOS field effect transistor Q13 is in the off state, voltage V13 is equal to voltage V3, and current I11 is also equal to current I1.

As described above, even when the high voltage Vpp exceeding the high potential power supply Vdd is input to the voltage input terminal 2, the P channel MOS field effect transistor Q12, which is an electrostatic discharge element, is always kept in the off state, High potential power supply Vd
No short circuit will occur with respect to d.

When a positive static electricity exceeding the high potential power source Vdd is applied to the voltage input terminal 2 with respect to the low potential power source Vss, the drain electrode of the P channel MOS field effect transistor Q12 is used as the emitter electrode and the source electrode. As the collector electrode and the back gate electrode as the base electrode, the emitter / collector path of the parasitic PNP bipolar transistor is made conductive, and the P-channel MOS field effect transistor Q12 is turned on to make the source / drain path conductive.
Further, as the diode D2 breaks down, static electricity is discharged to the high-potential power supply Vdd, and the electrostatic breakdown voltage of the voltage input terminal 2 is secured.

Further, by replacing the resistor R2 with the diode D1, the diode D1 is reverse biased when the voltage V12 rises above Vdd and the bias current does not flow, so that the input resistance of the voltage input terminal can be increased. it can.

[0048]

As described above, the first effect of the input protection circuit of the present invention is that the electrostatic withstand voltage of the voltage input terminal can be secured, and the voltage input is performed during the normal operation such as PROM write operation. High potential power supply Vd
Even if a voltage higher than d is applied, a short circuit between the voltage input terminal and the high potential power supply Vdd does not occur.

Further, the second effect is that the input resistance of the voltage input terminal can be increased during the normal operation such as the PROM write operation.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an input protection circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a voltage detection circuit of the input protection circuit according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a cross-sectional structure of a main part of the input protection circuit according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of an operation of the input protection circuit according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram of an input protection circuit according to a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional input protection circuit.

FIG. 7 is a configuration diagram of another conventional input protection circuit.

[Explanation of symbols]

1 Internal circuit 2, 5, 6 Terminal 3, 13 Discharge circuit 4 Voltage detection circuit 7 Voltage comparator 8 Reference voltage 21, 31 Gate electrode 22, 32 Drain electrode 23, 33 Source electrode 24, 34 Back gate electrode 25, 35 N Well 40 P substrate Q1 N channel MOS field effect transistor Q2, Q3, Q12, Q13, Q22 P channel M
OS field effect transistor D1, D2 diode R1, R2 resistance

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 27/085-27/092 H01L 21/8234-21/8238 H01L 27/04

Claims (4)

(57) [Claims] 1. A resistor and a source / drain path are provided from the outside.
Voltage input terminal for inputting the supplied voltage to the internal circuit
And a high potential power supply connected between the gate electrode and the back
The gate electrode is connected to the high potential power source through the resistor.
And the voltage of the gate electrode
A discharge circuit including switch means for changing over,
The switch comparing the voltage of the voltage input terminal with a reference voltage
An input protection circuit comprising a voltage detection circuit for turning on and off the means,
An input protection circuit , wherein the voltage of the voltage input terminal is applied to a gate electrode . 2. A first diode and a second diode
And the voltage supplied to one end of the source-drain path from the outside
Is connected to the voltage input terminal for input to the internal circuit
The other end of the source / drain path is the reverse bias direction.
It is connected to the high potential power supply through the diode of
The pole and the back gate electrode have the second bias in the reverse bias direction.
Electric field effect connected to the high potential power supply through a diode
The transistor that switches the voltage of the gate electrode
Switch circuit, and the voltage input terminal
Of the switch means is turned on by comparing the voltage of
An input protection circuit comprising: a voltage detection circuit for turning off; the gate electrode when the switch means is in an on state.
An input protection circuit , wherein the voltage of the voltage input terminal is applied to the input protection circuit. Wherein said voltage detecting circuit, when the voltage of the voltage input terminal exceeds the reference voltage, the input protection according to claim 1 or claim 2, wherein that said switching means in the ON state circuit. 4. The input protection circuit according to claim 1, wherein the reference voltage is a voltage obtained by adding a threshold of the field effect transistor to a voltage of the high potential power supply.