JP3383617B2 - Liquid crystal display or EL display - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The invention disclosed in this specification includes:
The present invention relates to a configuration applicable to a flat panel display represented by an active matrix type liquid crystal display device and an EL type display device. Further, the present invention relates to a structure of an interlayer insulating film of a semiconductor device represented by a thin film transistor.

[0002]

2. Description of the Related Art Conventionally, an active matrix type liquid crystal display device has been known as a flat panel display. This has a structure in which a thin film transistor for switching is arranged in each of a large number of pixels arranged in a matrix, and the electric charge which goes in and out of each pixel electrode is controlled by this thin film transistor.

In such a structure, there is required a structure in which the semiconductor device is covered with an insulating film to prevent entry of moisture and impurities, and further mobile ions (for example, sodium ions), which are the enemy of the semiconductor device. Further, such a structure requires a structure capable of reducing the capacitance formed between the pixel electrode or wiring and the thin film transistor.

Further, it is required that the manufacturing cost is low and the productivity is excellent. However, under the present circumstances, a silicon oxide film or a silicon nitride film which is usually used as an interlayer insulating film cannot satisfy this requirement.

[0005]

An object of the invention disclosed in this specification is to provide a structure required for an interlayer insulating film as described above. That is, it is possible to prevent the ingress of moisture and impurities, further suppress the problem of capacitance formed between the thin film transistor and the pixel electrode or wiring, and further, the interlayer insulating film having a low cost and high productivity. It is an object to provide a structure of a semiconductor device having the above.

[0006]

One of the inventions disclosed in the present specification is to provide an interlayer insulating film made of a resin material, which is disposed above a semiconductor element, and which is used as a base for forming the interlayer insulating film. A silicon oxide film or a silicon nitride film is formed on the entire surface.

According to another aspect of the invention, an interlayer insulating film made of a resin material is provided above the semiconductor element, and the entire surface of the base on which the interlayer insulating film is formed is a silicon oxide film and a silicon nitride film. And a laminated film is formed.

In the above structure, the silicon oxide film and the silicon nitride film may be laminated in either order. When the semiconductor element is covered, the lower layer of the silicon nitride film is preferable in terms of good adhesion and good interface characteristics.

According to another aspect of the invention, an interlayer insulating film made of a resin material is provided above the semiconductor element, and a silicon oxynitride film is formed on the entire surface of the base on which the interlayer insulating film is formed. It is characterized by being

According to another aspect of the invention, an interlayer insulating film made of a resin material is provided above the semiconductor element, and a silicon oxide film or a silicon nitride film is provided between the semiconductor element and the interlayer insulating film. Is formed.

According to another aspect of the invention, an interlayer insulating film made of a resin material is provided above the semiconductor element, and a silicon oxynitride film is formed between the semiconductor element and the interlayer insulating film. It is characterized by

According to another aspect of the invention, an interlayer insulating film made of a resin material is provided above the semiconductor element, and a silicon oxide film and a silicon nitride film are provided between the semiconductor element and the interlayer insulating film. And a laminated film is formed.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION By using a laminated film of a silicon nitride film and a resin film as an interlayer insulating film covering an upper portion of a thin film transistor, it is possible to reduce a capacitance formed between a pixel electrode or wiring and a thin film transistor.

Further, since the surface of the resin material can be flattened, a step overcoming portion of the wiring is not formed, and it is possible to prevent a local change in the wiring resistance and a disconnection.

Further, by providing a silicon nitride film between the resin film and the thin film transistor so that the resin film does not come into direct contact with the thin film transistor, it is possible to prevent moisture in the resin film from adversely affecting the operation of the thin film transistor. it can.

[0016]

[Embodiment 1] FIGS. 1 and 2 show a manufacturing process of a pixel portion of an active matrix type liquid crystal display device shown in this embodiment.

First, as shown in FIG. 1A, a glass substrate 1
A silicon oxide film is formed as a base film 102 on 01 by a plasma CVD method to a thickness of 3000 Å. This base film 102
Has a function of suppressing diffusion of impurities from the glass substrate 101 into a semiconductor layer to be formed later. In addition, it has a function of relieving stress acting between the glass substrate 101 and a semiconductor layer formed later.

It is also useful to use a silicon oxynitride film as the base film 102. Since the silicon oxynitride film is dense and has high adhesion to the glass substrate, the base film 102 is used.
Has a high function as.

The silicon oxynitride film can be formed by a plasma CVD method using a mixed gas of silane, oxygen and N ₂ O. It can also be obtained by a plasma CVD method using a mixed gas of TEOS gas and N ₂ O.

Next, the semiconductor layer 10 of the thin film transistor will be described later.
An amorphous silicon film, which is a starting film of a thin film semiconductor that forms No. 3, is formed on the base film 102. Here, this amorphous silicon film is formed to a thickness of 500 Å by using the low pressure thermal CVD method. A plasma CVD method may be used as a method for forming the amorphous silicon film.

Then, heat treatment or laser light irradiation,
Alternatively, the amorphous silicon film is crystallized by using a method in which heat treatment and laser light irradiation are combined. Thus, a crystalline silicon film (not shown) is obtained.

Then, the crystalline silicon film (not shown) is patterned to obtain the semiconductor layer 103 of the thin film transistor. (Fig. 1 (A))

Next, as shown in FIG. 1A, the semiconductor layer 10 is formed.
A silicon oxide film 10 which covers 3 and functions as a gate insulating film.
4 is formed to a thickness of 1000 Å by plasma CVD method.
In this way, the state shown in FIG.

A silicon oxynitride film is more preferably used as the insulating film functioning as the gate insulating film.

Next, an aluminum film (not shown) containing scandium in an amount of 0.1% by weight is formed by sputtering to a thickness of 4000 Å. This aluminum film will later form the gate electrode 105.

After forming the aluminum film, a dense anodic oxide film (not shown) having a thickness of 100 Å is formed on the surface of the aluminum film. This anodic oxidation is carried out by neutralizing an ethylene glycol solution containing 3% tartaric acid with aqueous ammonia as an electrolytic solution, and using an aluminum film as an anode in this electrolytic solution.

In this anodic oxidation, the film thickness of the anodic oxide film formed by the ultimate voltage can be controlled.

Further, a resist mask (not shown) is arranged and patterning is performed. By performing this patterning, the gate electrode 105 is formed.

After forming the gate electrode 105, anodic oxidation is performed again with a resist mask (not shown) left.
This anodic oxidation is performed by using a 3% oxalic acid aqueous solution as an electrolytic solution.

In this anodic oxidation, the anodic oxidation is selectively performed only on the side surface of the gate electrode 105 because a resist mask (not shown) remains. The anodic oxide film 106 formed in this step has a porous structure.

Thus, the anodic oxide film 106 having a porous film quality is formed on the side surface of the gate electrode 105.

The porous anodic oxide film 106 has a thickness of several μm.
It can be grown to a moderate thickness. The growth distance can be controlled by controlling the anodic oxidation time.

Here, the thickness of the anodic oxide film 106 is set to 300.
Set to 0Å.

Next, anodic oxidation is performed again by using an ethylene glycol solution containing 3% tartaric acid neutralized with aqueous ammonia as an electrolytic solution. In this anodic oxidation process, since the electrolytic solution penetrates into the porous anodic oxide film 106, a dense anodic oxide film 107 is formed around the gate electrode 105.

The dense anodic oxide film 107 has a film thickness of 50.
Set to 0Å. The main role of the dense anodic oxide film 107 is to cover the surface of the gate electrode 106 so that hillocks and whiskers do not occur in a later process.

The gate electrode 105 is also protected so that the gate electrode 105 is not simultaneously etched when the porous anodic oxide film 106 is removed later.

Further, it also has a role of contributing to the formation of the offset gate region in the subsequent impurity ion implantation step. Thus, the state shown in FIG. 1B is obtained.

Impurity ions are implanted in this state. Here, P (phosphorus) ions are implanted in order to obtain an N-channel thin film transistor.

When impurity ion implantation is performed in the state shown in FIG. 1B, impurity ions are selectively implanted in the regions 108 and 111. In this step, the regions 108 and 111 become high concentration impurity regions. The region 108 is a source region and the region 111 is a drain region.

In the semiconductor layer 103, the region 109 immediately below the gate electrode 105 is masked by the gate electrode 105, so that impurity ions are not implanted. Then, this region 109 becomes a channel formation region.

Further, since the porous anodic oxide film 105 and the dense anodic oxide film 107 serve as a mask in the region 110, no impurity ions are implanted. The region indicated by 110 is an offset gate region that does not function as a source / drain region or as a channel forming region 109. The size of the offset gate region 110 can be determined by the film thickness of the dense anodic oxide film 107 and the film thickness of the porous anodic oxide film 106.

The offset gate region 110 functions especially to reduce the strength of the electric field formed between the channel forming region 109 and the drain region 111. The presence of the offset gate region 110 can reduce the OFF current value of the thin film transistor and further suppress the deterioration.

Thus, the source region designated by 108,
A channel forming region 109, an offset gate region 110, and a drain region 111 are formed in a self-aligned manner.

There is also a method in which the porous anodic oxide film 106 is removed after the above impurity ion implantation and the impurity ion implantation is performed again under light doping conditions. in this case,
A lightly doped region can be formed immediately below the porous anodic oxide film 106.

The drain side of this lightly doped region is usually called an LDD (lightly doped drain) region.

After the implantation of the impurity ions is completed, the porous anodic oxide film 106 is selectively removed. here,
The porous anodic oxide film 106 is selectively removed using a mixed acid in which phosphoric acid, acetic acid, and nitric acid are mixed.

Then, an annealing process is performed by irradiation with laser light. At this time, since the laser beam can be applied to the vicinity of the interface between the high concentration impurity region and the offset gate region, the junction portion damaged by the impurity ion implantation can be sufficiently annealed.

The annealing may be performed by irradiating with ultraviolet light or infrared light instead of irradiating with laser light. Further, it is also useful to perform heating in combination with irradiation with laser light or intense light.

After obtaining the state shown in FIG. 1B, a silicon oxide film 112 is formed to a thickness of 2000 Å as a first interlayer insulating film. A silicon nitride film or a laminated film of a silicon oxide film and a silicon nitride film may be used as the first interlayer insulating film.

Next, a contact hole is formed in the first interlayer insulating film 112, and the source region 1 of the thin film transistor is formed.
The source electrode 113 that contacts 08 is formed.
The source electrode 113 is formed as having a laminated structure of a titanium film, an aluminum film and a titanium film. The source electrode 113 is formed so as to extend from the source wiring. That is, it is formed at the same time as the formation of the source lines arranged in a grid pattern in the active matrix region.
Thus, the state shown in FIG. 1C is obtained.

Then, a 1000 Å thick silicon nitride film 114 is formed. The silicon nitride film has a function of suppressing the presence of fixed charges at the interface with the thin film transistor by utilizing its dense film quality (generally, the film quality of the silicon nitride film is dense). Further, by utilizing the dense film quality, it has a function of preventing moisture and mobile ions from entering from the outside.

The silicon nitride film 114 is formed by the plasma CVD method using silane and ammonia. Other than the silicon nitride film, a silicon oxynitride film can be used.

Next, a silicon oxide film 115 is formed to a thickness of 2000 liters by a plasma CVD method. Here, the silicon oxide film 115 is formed in order to increase reliability, but it may not be particularly used.

Further, an interlayer insulating film 116 is formed by using transparent polyimide resin or acrylic resin. The surface of the interlayer insulating film 116 made of this resin material is made flat. The film thickness of the interlayer insulating film 116 made of this resin material is 2 μm.
m. Thus, the state shown in FIG. 1D is obtained.

By forming the interlayer insulating film 116 using a resin material, the capacitance between the element and the electrodes and wirings formed on the interlayer insulating film 116 can be reduced. In addition, the manufacturing cost can be significantly reduced.

The interlayer insulating film 116 made of this resin material is also used.
Since the silicon oxide film 115 is formed on the base, the adhesiveness to the base can be improved. Further, it is possible to adopt a configuration in which moisture does not enter between the base and the base.

This action is achieved by forming the interlayer insulating film 1 made of a resin material on the silicon nitride film 114 without forming the silicon oxide film 115.
It can be obtained also when 16 is formed.

Next, as shown in FIG. 2A, a chrome film which also serves as a light-shielding film of the thin film transistor and a black matrix is formed and further patterned to form a light-shielding film / black matrix 117.

Here, as the resin material forming the interlayer insulating film 116, one having a relative dielectric constant of 3 or less can be selected. Further, the film thickness can be increased to several μm. In the case of a resin material, even if the resin material is made thicker, the manufacturing process time does not become longer, so it is useful for such a purpose.

With such a structure, it is possible to suppress the formation of capacitance between the light shielding film 117 made of chromium and the thin film transistor thereunder.

Further, when the interlayer insulating film 116 is made of a resin material, it is easy to flatten its surface.
The problem of light leakage due to unevenness can be suppressed.

After obtaining the state shown in FIG. 2A, a silicon nitride film 118 is further formed as an interlayer insulating film. Further, a silicon oxide film 119 is formed.

Although the two-layer structure of the silicon nitride film 118 and the silicon oxide film 119 is used here to improve the reliability, any one of the single-layer structures may be used.

Further, an interlayer insulating film 120 made of a resin material is formed. The material may be the same as 116.

By forming the interlayer insulating film 120 with a resin material, it is possible to prevent an unnecessary capacitance from being formed between a pixel electrode and a thin film transistor which will be formed later. Further, since the surface is flattened, it is possible to prevent the electric field from the pixel electrode formed later from being disturbed.

Then, a contact hole is formed,
An ITO electrode for forming a pixel electrode is formed by a sputtering method, and further patterned to form a pixel electrode 121.

Thus, the structure shown in FIG. 2B is completed. In the structure shown in FIG. 2B, the relative dielectric constant of the interlayer insulating film provided between the thin film transistor (in particular, the source electrode 113) and the light-shielding film (and / or the black matrix) 117 can be reduced and the thickness thereof can be reduced. Since it is possible to increase the thickness, it is possible to suppress the formation of unnecessary capacitance.

As described above, it is industrially easy to increase the thickness of the resin film, and since the process time does not increase, the above-mentioned structure can be easily realized.

[Embodiment 2] This embodiment is characterized in that the construction shown in Embodiment 1 is further improved to have a higher reliability.

As described above, a metal material such as chromium is used for the light shielding film and the black matrix. However, considering long-term reliability, there are concerns about the problem of diffusion of impurities from the metal material and the problem of short-circuit with other electrodes or wirings.

Therefore, in the structure shown in this embodiment, an anodizable material is used as a light shielding film for shielding the thin film transistor in the structure shown in the first embodiment, and an anodic oxide film is further formed on the surface thereof.

Aluminum or tantalum can be used as the anodizable material. Particularly when aluminum is used, it is suitable as a light-shielding film because the anodized film can be colored black or a dark color close to it by using the anodizing technology used for industrial products such as aluminum sashes. It will be

FIG. 3 shows an outline of the manufacturing process of this embodiment.
In FIG. 3, the same parts as those in FIG. 2 are not shown.

First, the state shown in FIG. 1D is obtained according to the steps shown in FIGS. Next, as shown in FIG. 3A, the light shielding film 301 is formed. Here, the light-blocking film 301 is formed using aluminum as its material.

Then, anodic oxidation is performed in the electrolytic solution to form an anodic oxide film 302 on the surface of the light shielding film 301 as shown in FIG.

In the figure, the light shielding film 301 is described as a light shielding film which shields the thin film transistor from light. However, it usually extends further to form a black matrix.

After obtaining the state shown in FIG.
As shown in (B), the silicon nitride film 118 and the silicon oxide film 11
And an interlayer insulating film 12 made of a resin material.
0 is deposited in multiple layers.

Further, the pixel electrode 121 is formed of ITO to obtain the state shown in FIG. 3 (B).

The structure shown in this embodiment has the anodic oxide film 302.
Since it is chemically stable, it is possible to suppress the diffusion of impurities from the light shielding film 301 to the surroundings in consideration of long-term reliability. In addition, the light shielding film 3
It is possible to prevent 01 from short-circuiting between other wirings.

[Embodiment 3] This embodiment relates to a structure in which the aperture ratio of a pixel is further increased. In general, it is desired that the pixel aperture ratio be as high as possible. In order to increase the aperture ratio of this pixel, it is necessary to arrange the pixel electrode in a large area.

However, when the pixel electrode and the thin film transistor or the wiring overlap with each other, a capacitance is formed between them, so that there is generally a large limitation in this respect.

The present embodiment provides a structure in which the problem that this capacitance is formed is reduced.

FIG. 4 shows the configuration of this embodiment. The configuration shown in FIG. 4 relates to a configuration in which the source lines and the gate lines arranged in a lattice function as a black matrix and the area of the pixel electrode 402 is maximized.

In the structure shown in FIG. 4, the light shielding film 401 covering the main part of the thin film transistor is arranged by the metal material forming the source electrode (and the source line).

By arranging the pixel electrode 402 so as to partially overlap the source line and the gate line, part of the source line and the gate line can be used as a black matrix.

When the structure shown in FIG. 4 is adopted, the pixel electrodes can be arranged over a wide area.
The aperture ratio of the pixel can be increased.

Even in such a structure, the pixel electrode 4 is formed because the interlayer insulating film 116 made of a resin material exists.
The capacitance formed between the thin film transistor 02 and the thin film transistor can be made small.

Further, by using a resin material for the interlayer insulating film 116, it is possible to reduce unnecessary pressure applied to the thin film transistor in the rubbing process and the panel assembling process after the pixel electrode 402 is formed.

Further, the resin material 116 forming the interlayer insulating film
A silicon oxide film 115 is formed on the entire surface of the underlayer of
Further, a silicon nitride film 114 is formed on the underlying layer. Since the thin film transistor is covered with this silicon nitride film 114, the electrical stability of the thin film transistor can be ensured.

In particular, the silicon nitride film 114 can prevent moisture from diffusing into the thin film transistor portion from the interlayer insulating film 116 made of a resin material, and the electrical stability of the thin film transistor can be improved.

[Embodiment 4] In this embodiment, an example in which an N-channel type thin film transistor and a P-channel type thin film transistor are formed in a complementary type is shown. The structure shown in this embodiment can be used in various thin film integrated circuits integrated on an insulating surface, for example. Further, it can be used, for example, in a peripheral drive circuit of an active matrix type liquid crystal display device.

First, as shown in FIG. 5A, the glass substrate 5
On 01, a silicon oxide film or a silicon oxynitride film is formed as a base film 502. Further, an amorphous silicon film (not shown) is formed by a plasma CVD method or a low pressure thermal CVD method. Further, the amorphous silicon film is irradiated with laser light or heat-treated to transform the amorphous silicon film into a crystalline silicon film.

Then, the obtained crystalline silicon film is patterned to obtain semiconductor layers 503 and 504. Thus, FIG.
The state shown in (A) is obtained.

Further, a silicon oxide film 505 which constitutes a gate insulating film is formed. Then, an aluminum film (not shown) for forming a gate electrode later is formed to a thickness of 4000 Å. Other than the aluminum film, a metal that can be anodized (for example, tantalum) can be used.

After forming the aluminum film, an extremely thin and dense anodic oxide film is formed on the surface thereof by the method described above.

Next, a resist mask (not shown) is placed on the aluminum film, and the aluminum film is patterned to form gate electrodes 506 and 507. Then, anodization is performed using the obtained gate electrodes 506 and 507 as anodes, and the porous anodic oxide films 508 and 50 are formed on the side surfaces thereof.
9 is formed. This porous anodic oxide film 508, 50
The film thickness of 9 is, for example, 5000 Å.

Further, the anodic oxidation is performed again under the condition that the dense anodic oxide film is formed, and the dense anodic oxide films 510 and 511 are formed.
To form. Here, the film thickness of the dense anodic oxide films 510 and 511 is set to 800 Å. Thus, the state shown in FIG. 5B is obtained.

Further exposed portion of the silicon oxide film 50
5 is removed by dry etching to obtain the state shown in FIG.

After obtaining the state shown in FIG. 5C, the porous anodic oxide films 508 and 509 are removed by using a mixed acid obtained by mixing acetic acid, nitric acid and phosphoric acid. Thus, the state shown in FIG. 5D is obtained.

Here, resist masks are alternately arranged so that P ions are implanted into the semiconductor layer 503 of the left thin film transistor and B ions are implanted into the semiconductor layer 504 of the right thin film transistor.

By the implantation of the impurity ions, the source region 514 and the drain region 517 having a high concentration of N type are formed.
Are formed in a self-aligned manner.

Further, a region 515 having a weak N type which is lightly doped with P ions is formed at the same time. Also,
The channel formation region 516 is formed at the same time.

The weak N-type region 515 is formed because of the remaining gate insulating film 512. That is, P that has passed through the gate insulating film 512
This is because some of the ions are shielded by the gate insulating film 512.

Further, according to the same principle, the source region 521 and the drain region 518 having strong P type are formed in a self-aligned manner. Further, the low concentration impurity region 520 is formed at the same time. In addition, the channel formation region 519 is formed at the same time.

When the dense anodic oxide films 510 and 511 have a large thickness of 2000 Å, the offset gate region can be formed in contact with the channel forming region 519 with that thickness.

In the case of this embodiment, the dense anodic oxide film 51 is used.
Since the film thicknesses of 0 and 511 are as thin as 1000 Å or less, their existence can be ignored.

Then, laser light or intense light is irradiated to anneal the region into which the impurity ions are implanted.

Then, as shown in FIG. 5E, a silicon nitride film 522 and a silicon oxide film 523 are formed as an interlayer insulating film. Each film thickness shall be 1000Å. Note that the silicon oxide film 523 may not be formed.

Here, the thin film transistor is covered with the silicon nitride film 522. Since the silicon nitride film is dense and has good interface characteristics, the reliability of the thin film transistor can be improved by adopting such a structure.

Further, an interlayer insulating film 524 made of a resin material is formed by spin coating. Here, the thickness of the interlayer insulating film 524 is 1 μm. (Fig. 5 (E))

Then, a contact hole is formed, and the source electrode 52 of the left N-channel thin film transistor is formed.
5 and the drain electrode 526 are formed. At the same time, the source electrode 527 and drain electrode 5 of the thin film transistor on the right side
26 is formed. Here, the electrode 526 is disposed in common to the two thin film transistors.

In this way, a thin film transistor circuit having a complementary CMOS structure can be formed.

In the structure shown in this embodiment, a thin film transistor is covered with a nitride film and further covered with a resin material. This structure can be made highly durable so that mobile ions and moisture do not easily enter.

Further, it is possible to prevent a capacitance from being formed between the thin film transistor and the wiring when a multilayer wiring is further formed.

[Embodiment 5] This embodiment shows a manufacturing process of a bottom gate type thin film transistor in which a gate electrode is on the substrate side of an active layer.

FIG. 6 shows the manufacturing process of this embodiment. First, as shown in FIG. 6A, a silicon oxide film 602 is formed as a base film on a glass substrate 601 by a sputtering method. Next 6
A gate electrode indicated by 03 is formed of aluminum.

At this time, scandium was added to aluminum.
Contains 0.18% by weight. In addition, other impurities will be sought to reduce their concentration as much as possible. These measures are for suppressing the formation of protrusions called hillocks or whiskers due to abnormal growth of aluminum in the subsequent process.

Thus, the state shown in FIG. 6A is obtained. Next, a silicon oxide film 604 which functions as a gate insulating film is formed to a thickness of 500 Å by the plasma CVD method.

Further, an amorphous silicon film (not shown) (which will later become a crystalline silicon film 605) which is a starting film forming a semiconductor layer of a thin film transistor is formed by a plasma CVD method.
A low pressure thermal CVD method may be used instead of the plasma CVD method.

Next, by irradiating laser light,
An amorphous silicon film (not shown) is crystallized. Thus, the crystalline silicon film 605 is obtained.

Thus, the state shown in FIG. 6B is obtained. After obtaining the state shown in FIG. 6B, the semiconductor layer 606 is obtained by performing patterning.

Next, a silicon nitride film (not shown) is formed, and exposure is performed from the back surface side of the substrate 601 using the gate electrode 603 to expose the mask pattern 6 made of a silicon nitride film.
07 is formed.

The mask pattern 607 is formed as follows. First, the pattern of the gate electrode 603 is used to form a resist mask pattern by exposure from the back surface side of the substrate 601. Further, ashing is performed to retreat the resist mask pattern. Then, the pattern of the recessed resist mask (not shown)
By patterning the silicon nitride film using
The pattern indicated by 607 is obtained.

Thus, the state shown in FIG. 6C is obtained. Next, impurity doping is performed using the mask pattern 607. Here, P (phosphorus) is used as a dopant, and a plasma doping method is used as a means for performing doping.

In this step, P is doped in the regions 608 and 610. The region 609 is not doped with P.

After the doping is completed, laser light is irradiated from the upper surface to activate the doped region and anneal damage caused by impact of the dopant ions.

Thus, the region 608 is formed as the source region. Also, 610 is formed as a drain region. Further, 609 defines a channel region.

Thus, the state shown in FIG. 6D is obtained. Next, an interlayer insulating film 611 made of a silicon nitride film is formed by plasma CVD.
The film is formed to a thickness of 2000Å by the method.

As the interlayer insulating film 611 used here,
A silicon nitride film is most preferable. This is because the silicon nitride film exerts its effect most strongly in order to prevent the effect of water present in the resin interlayer film 612 formed later (effect on the semiconductor layer 606).

Other than the silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a laminated film of a silicon oxide film and a silicon nitride film (whichever may be laminated first) can be used.

Next, a resin film 612 made of polyimide is formed as an interlayer insulating film. As a film forming method, a spin coating method is used.

Further, contact holes are formed to form a source electrode 613 and a drain electrode 614.

When a resin material is used for the interlayer insulating film, there is a problem that the effect of moisture (especially OH group) present in the resin material affects the element characteristics. However, as shown in this embodiment, by providing the silicon nitride film for preventing the movement of moisture, the above-mentioned problems that occur when the resin material is used for the interlayer insulating film can be suppressed.

[0134]

By utilizing the invention disclosed in this specification, it is possible to suppress the problem of capacitance formed between the thin film transistor and the pixel electrode or wiring with high reliability. An inexpensive and highly productive structure can be obtained. The invention disclosed in this specification can be applied not only to an active matrix type liquid crystal display device but also to an EL type display device or an IC circuit.

[Brief description of drawings]

1A to 1C are manufacturing process diagrams of a pixel portion of an active matrix circuit of Embodiment 1. FIGS.

2A to 2C are manufacturing process diagrams of a pixel portion of the active matrix circuit of Embodiment 1. FIGS.

3A to 3C are manufacturing process diagrams of a pixel portion of an active matrix circuit of Embodiment 2. FIGS.

FIG. 4 is a pixel partial view of an active matrix circuit according to a third embodiment.

5A to 5D are manufacturing process diagrams of a complementary thin film transistor of Example 4. FIGS.

6A to 6C are manufacturing process diagrams of a thin film transistor of Example 5. FIGS.

[Explanation of symbols]

101 glass substrate 102 base film (silicon oxide film or silicon oxynitride film) 103 semiconductor layer (crystalline silicon film) 104 gate insulating film (silicon oxide film or silicon oxynitride film) 105 gate electrode 106 porous anodic oxide film 107 dense anodic oxide film 108 source region 109 channel formation region 110 offset gate region 111 drain region 112 interlayer insulating film (silicon oxide film) 113 source electrode 114 interlayer insulating film (silicon nitride film) 115 interlayer insulating film (silicon oxide film) 116 interlayer insulating film (resin material) 117 light shielding film (chrome film) 118 interlayer insulating film (silicon nitride film) 119 interlayer insulating film (silicon oxide film) 120 interlayer insulating film (resin material) 121 pixel electrode (ITO electrode)

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 G02F 1/1368 G09F 9/00

Claims (10)

(57) [Claims] 1. A thin film transistor having a substrate, a semiconductor layer formed on the substrate and having a source region, a drain region and a channel forming region, a gate insulating film and a gate electrode, the semiconductor layer and the gate insulating film. A silicon oxide film, a silicon nitride film, a silicon oxide film and a silicon nitride film above the film and the gate electrode.
A first insulating film made of a resin material, which is formed through any one of laminated films of films, and a silicon oxide film or a silicon nitride film formed on the first insulating film.
A second insulating film made of an elemental film, a third insulating film made of a resin material and formed on the second insulating film, and a third insulating film formed on the third insulating film and contacting the drain region.
A liquid crystal display device having a continuous pixel electrode , wherein the entire surface of the base of the first insulating film is a silicon nitride film or an oxide film.
A liquid crystal display device having a silicon nitride film formed thereon . 2. A thin film transistor having a substrate, a semiconductor layer formed on the substrate and having a source region, a drain region and a channel forming region, a gate insulating film and a gate electrode, the semiconductor layer and the gate insulating film. A silicon oxide film, a silicon nitride film, a silicon oxide film and a silicon nitride film above the film and the gate electrode.
A first insulating film made of a resin material, which is formed through any one of laminated films of the films; a silicon nitride film formed on the first insulating film;
A second insulating film made of a laminated film of a silicon oxide film, is formed on the second insulating film, a third insulating film made of a resin material, is formed on the third insulating film, wherein Contact drain area
A liquid crystal display device having a continuous pixel electrode , wherein the entire surface of the base of the first insulating film is a silicon nitride film or an oxide film.
A liquid crystal display device having a silicon nitride film formed thereon . 3. A thin film transistor having a substrate, a semiconductor layer formed on the substrate and having a source region, a drain region and a channel forming region, a gate insulating film, and a gate electrode, the semiconductor layer and the gate insulating film. A silicon oxide film, a silicon nitride film, a silicon oxide film and a silicon nitride film above the film and the gate electrode.
A first insulating film made of a resin material, which is formed through any one of laminated films of films, and a silicon oxide film or a silicon nitride film formed on the first insulating film.
A second insulating film made of an elemental film, a third insulating film made of a resin material and formed on the second insulating film, and a third insulating film formed on the third insulating film and contacting the drain region.
A liquid crystal display device having a continuous pixel electrode , wherein the entire surface of the base of the first insulating film is a silicon nitride film or an oxide film.
A silicon nitride film is formed, and the first insulating film and the nitride film are formed.
The first insulating film is provided between the silicon film and the silicon oxynitride film.
A liquid crystal display device, wherein a silicon oxide film is formed in contact with the film . 4. A substrate, a semiconductor layer formed on the substrate, having a source region, a drain region and a channel forming region, a gate insulating film, and a thin film transistor having a gate electrode, the semiconductor layer and the gate insulating film. A silicon oxide film, a silicon nitride film, a silicon oxide film and a silicon nitride film above the film and the gate electrode.
A first insulating film made of a resin material, which is formed through any one of laminated films of the films; a silicon nitride film formed on the first insulating film;
A second insulating film made of a laminated film of a silicon oxide film, is formed on the second insulating film, a third insulating film made of a resin material, is formed on the third insulating film, wherein Contact drain area
A liquid crystal display device having a continuous pixel electrode , wherein the entire surface of the base of the first insulating film is a silicon nitride film or an oxide film.
A silicon nitride film is formed, and the first insulating film and the nitride film are formed.
The first insulating film is provided between the silicon film and the silicon oxynitride film.
A liquid crystal display device, wherein a silicon oxide film is formed in contact with the film . 5. The resin material according to claim 1, wherein the resin material is a polyimide resin or an acrylic resin .
The liquid crystal display device according to any one. 6. A substrate, a semiconductor layer formed on the substrate, the semiconductor layer having a source region, a drain region, and a channel forming region, a gate insulating film, and a thin film transistor having a gate electrode, the semiconductor layer, the gate insulating film. A silicon oxide film, a silicon nitride film, a silicon oxide film and a silicon nitride film above the film and the gate electrode.
A first insulating film made of a resin material, which is formed through any one of laminated films of films, and a silicon oxide film or a silicon nitride film formed on the first insulating film.
A second insulating film made of an elemental film, a third insulating film made of a resin material and formed on the second insulating film, and a third insulating film formed on the third insulating film and contacting the drain region.
In the EL display device having a continuous pixel electrode, the entire surface of the base of the first insulating film is a silicon nitride film or an oxide film.
An EL display device having a silicon nitride film formed thereon . 7. A substrate, a semiconductor layer formed on the substrate, the semiconductor layer having a source region, a drain region, and a channel forming region, a gate insulating film, and a thin film transistor having a gate electrode, the semiconductor layer, the gate insulating film. A silicon oxide film, a silicon nitride film, a silicon oxide film and a silicon nitride film above the film and the gate electrode.
A first insulating film made of a resin material, which is formed through any one of laminated films of the films; a silicon nitride film formed on the first insulating film;
A second insulating film made of a laminated film of a silicon oxide film, is formed on the second insulating film, a third insulating film made of a resin material, is formed on the third insulating film, wherein Contact drain area
In the EL display device having a continuous pixel electrode, the entire surface of the base of the first insulating film is a silicon nitride film or an oxide film.
An EL display device having a silicon nitride film formed thereon . 8. A substrate, a semiconductor layer formed on the substrate, having a source region, a drain region and a channel forming region, a gate insulating film, and a thin film transistor having a gate electrode, the semiconductor layer and the gate insulating film. A silicon oxide film, a silicon nitride film, a silicon oxide film and a silicon nitride film above the film and the gate electrode.
A first insulating film made of a resin material, which is formed through any one of laminated films of films, and a silicon oxide film or a silicon nitride film formed on the first insulating film.
A second insulating film made of an elemental film, a third insulating film made of a resin material and formed on the second insulating film, and a third insulating film formed on the third insulating film and contacting the drain region.
In the EL display device having a continuous pixel electrode, the entire surface of the base of the first insulating film is a silicon nitride film or an oxide film.
A silicon nitride film is formed, and the first insulating film and the silicon nitride film or silicon oxynitride film are formed.
An EL type display device characterized in that a silicon oxide film is formed in contact with the first insulating film between the film and the film . 9. A thin film transistor having a substrate, a semiconductor layer formed on the substrate and having a source region, a drain region and a channel forming region, a gate insulating film, and a gate electrode, the semiconductor layer and the gate insulating film. A silicon oxide film, a silicon nitride film, a silicon oxide film and a silicon nitride film above the film and the gate electrode.
A first insulating film made of a resin material, which is formed through any one of laminated films of the films; a silicon nitride film formed on the first insulating film;
A second insulating film made of a laminated film of a silicon oxide film, is formed on the second insulating film, a third insulating film made of a resin material, is formed on the third insulating film, wherein Contact drain area
In the EL display device having a continuous pixel electrode, the entire surface of the base of the first insulating film is a silicon nitride film or an oxide film.
A silicon nitride film is formed, and the first insulating film and the nitride film are formed.
The first insulating film is provided between the silicon film and the silicon oxynitride film.
An EL type display device characterized in that a silicon oxide film is formed in contact with the film . 10. The resin material according to claim 6 , wherein the resin material is a polyimide resin or an acrylic resin.
13. The EL type display device according to any one of 1 .