JP3383280B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulating gate type semiconductor device on a substrate and a method for improving the reliability of an integrated circuit having a large number of them. The semiconductor device according to the present invention includes a drive circuit such as an active matrix such as a liquid crystal display using a thin film transistor (TFT) or an image sensor, an SOI integrated circuit or a conventional semiconductor integrated circuit (microprocessor, microcontroller, microcomputer, semiconductor, or semiconductor). It is used for memory).

[0002]

2. Description of the Related Art In recent years, an insulating gate type semiconductor device (MI) has been formed on an insulating substrate, or even on a semiconductor substrate, on a surface (insulating surface) separated from the semiconductor substrate by a thick insulating film.
Researches for forming SFET) have been actively conducted. In particular, a semiconductor device having a thin semiconductor layer (active layer) is called a thin film transistor (TFT). In such a semiconductor device, it is difficult to obtain an element having good crystallinity such as a single crystal semiconductor, and a non-single crystal semiconductor having crystallinity but not single crystal is usually used.

In such a non-single-crystal semiconductor, the defect density is large, and the defects are filled by neutralizing them with an element such as hydrogen or fluorine. For example, such a process is realized by hydrogenation. It was But,
The bond between hydrogen and the semiconductor element (silicon etc.) was weak, and it was decomposed by thermal energy of a hundred and several tens of degrees Celsius. Therefore, when voltage and current are applied for a long time and the semiconductor locally generates heat, hydrogen is easily released, and the characteristics are significantly deteriorated. In particular, in a TFT for controlling a large current, for example, in a monolithic active matrix circuit having an active matrix circuit and a peripheral circuit for driving the same, the driver TFT of the peripheral circuit has a channel width of 200 μm or more, which causes a large current to flow. It was a big heat source because it turned on and off.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is a semiconductor in which local heat generated when the device is used is quickly dissipated so that the entire thin film circuit device can be uniformly heated. It is an object to provide a structure of a device and a method of manufacturing such a semiconductor device.

[0005]

A first aspect of the present invention is, in a thin film semiconductor device, a film containing aluminum nitride as a main component on a substrate, and a semiconductor film containing silicon as a main component directly or indirectly thereon. And a wiring such as a metal or a semiconductor directly or indirectly thereon. The present invention also relates to a method for manufacturing a thin film semiconductor device having such a structure, which is the second aspect of the present invention.
Is a process of forming a coating film containing aluminum nitride as a main component on a substrate, particularly a glass substrate having poor heat conduction and good heat retention, and a semiconductor coating film containing silicon as a main component directly or indirectly thereon. It is characterized in that it has a step of forming and a step of directly or indirectly forming wiring of metal, semiconductor or the like on it.

Aluminum nitride has an extremely high thermal conductivity and is transparent to visible light and near-ultraviolet light (optical bandgap of 6.2 eV), so that it is suitable for the purpose requiring transparency. Aluminum nitride is sputter method, reactive sputter method, MOCVD (metal organic chemical vapor deposition)
Method, plasma CVD method. In order to obtain an aluminum nitride film by the reactive sputtering method, it is advisable to carry out in a nitrogen atmosphere with aluminum as a target. As in the present invention, the thickness of aluminum nitride is preferably 500 Å to 5 μm, typically 1000 to 5,000 Å for the purpose of sufficient heat dissipation. 5
The thick aluminum nitride having a thickness of μm or more was easily peeled off and was not suitable for use.

Further, since the aluminum nitride film has a blocking effect on mobile ions such as sodium, it also has an effect of preventing these ions from penetrating into the semiconductor device from the substrate. The ratio of nitrogen to aluminum in the aluminum nitride coating may be stoichiometric or non-stoichiometric as long as there is no problem in heat conduction.
Typically, the ratio of nitrogen to aluminum is preferably (aluminum / nitrogen) = 0.9 to 1.4, and the thermal conductivity is 0.6 W / cmK or more (the thermal conductivity of an aluminum nitride single crystal is 2 W / cmK) gave favorable results.

Further, the stress of the coating may be optimized by changing the ratio of nitrogen and aluminum. Furthermore, in addition to nitrogen and aluminum, by adding a trace amount of boron, silicon, carbon, oxygen, etc. in an amount of 0.01 to 20 atomic%, stress matching with the substrate can be optimized, and stress strain can be minimized. is there. The coating film containing aluminum nitride as a main component may be crystalline or amorphous.

For the purpose of improving the thermal conductivity, it is usually considered to use a diamond-based material (for example, a polycrystalline diamond thin film, a hard carbon film, a diamond-like carbon film, etc.). In such a minute region, the diamond-based material generally does not have good adhesion to the silicon oxide-based material, and therefore a sufficient effect cannot be obtained. Further, a silicon nitride film which is often used as a blocking layer or a passivation layer in a normal semiconductor process has a low thermal conductivity and is not suitable for carrying out the present invention. Table 1 below
Then, the characteristics of the main thin film materials were compared. (○ indicates excellent, Δ indicates medium, and × indicates inferior.)

[0010]

[Table 1]

In the present invention, heat generated from metal or semiconductor wiring (gate wiring or the like) is transferred to the underlying semiconductor film (active layer or the like), or a current is passed through the semiconductor film. Although heat is generated and the temperature of the semiconductor film rises, it is quickly transferred to the underlying aluminum nitride film without staying there. Therefore, the temperature of the wiring and the semiconductor film is kept low, and Hydrogen desorption is reduced. In particular, it is possible to suppress local deterioration due to local heat generation due to generation of hot carriers due to application of a high reverse bias voltage between the drain and channel of the TFT, by soaking.

In the present invention, the direct deposition of the semiconductor film on the aluminum nitride film has good adhesion, but semiconductor carriers are trapped in the aluminum nitride, and the parasitic channel by the trapped carriers (trapping center) is obtained. Is likely to occur and, as a result, adversely affects the electrical characteristics of the semiconductor film, which is not preferable. There is no problem as long as such trap centers can be removed. However, if it cannot be easily removed, a material such as a silicon oxide film that is electrically and chemically preferable for a semiconductor film (a silicon oxide film is an aluminum nitride film). It was preferable to provide a trapping center density of only several tens of minutes in comparison with (1). Furthermore, in the silicon oxide film, the effect of stress relaxation can be expected.

Further, a silicon nitride film is formed on the aluminum nitride in a thickness of 100 to 1000Å, for example, 200Å, and a silicon oxide film is formed on the silicon nitride film in a thickness of 100 to 2000Å, for example, 200.
Å It was okay to form. In the present invention, as the material of the gate electrode, silicon (including those doped with impurities to increase conductivity), aluminum, tantalum, chromium, tungsten, molybdenum, etc., or their alloys or multilayers are used. A film may be used.
Moreover, as shown in the examples, the surface thereof may be oxidized.

Further, aluminum nitride is not etched by a fluorine-based etchant, and therefore is not etched by a method of etching a material used in a usual semiconductor process such as silicon oxide, silicon, or aluminum. You may use it as a stopper. That is, as the source and drain contacts of the TFT, not only the upper surfaces of the source and drain but also the side surfaces can be used as contacts. For example, even if the contact hole is formed so as to protrude from the source and drain, aluminum nitride does not act as an etching stopper and the substrate is not etched.

As a result, the source and drain regions can be formed smaller than before, which is advantageous for circuit integration. On the contrary, this also means that the contact hole can be made larger, and a more reliable contact can be obtained, which is advantageous in terms of mass productivity and reliability.

[0016]

EXAMPLES Example 1 An example of producing a TFT according to the present invention is shown in FIG. First, the substrate (Corning 705
9 glass substrates, size 300 mm x 300 mm or 100 mm x 100 mm) 101, thickness 2000
An aluminum nitride film 102 of up to 5000 Å was deposited by the reactive sputtering method. Sputtering was performed in an atmosphere of nitrogen and argon with aluminum as a target. When the proportion of nitrogen was 20% or more, a coating having good thermal conductivity was obtained. Sputtering pressure is 1 ×
Preferable results were obtained at 10 ⁻⁴ to 1 × 10 ⁻² Torr. The film formation rate was 20 to 200Å / min. Further, the substrate temperature may be raised to 100 to 500 ° C. during the film formation.

The aluminum nitride film 102 was formed on both sides of the substrate. This is because foreign elements such as sodium contained in the substrate or attached to the surface after shipping are
With the meaning of containing so as not to deteriorate the characteristics of
It has the effect of strengthening the substrate and making it difficult to scratch the surface.
In particular, when a TFT is used in an active matrix type liquid crystal display device, the surface not provided with the TFT is in contact with the external environment. However, this surface is apt to have minute scratches, and such scratches diffusely reflect light. And then dim the screen.

Next, the glass substrate on which aluminum nitride is formed is heated to 600 to 680 ° C., for example, 640 ° C. to 4-1.
Annealing was performed for 2 hours in an atmosphere of nitrogen, ammonia (NH ₃ ) or nitrous oxide (N ₂ O). And
It was slowly cooled at 0.01 to 0.5 ° C / min, for example, 0.2 ° C / min, and taken out when the temperature dropped to 350 to 450 ° C. By this step, the substrate which was colored yellow immediately after the reactive sputtering became transparent, and the electrical insulating property was improved. Further, in this annealing step, thermal contraction of the glass substrate occurred, and the stress was relaxed, so that the irreversible contraction was reduced. Therefore, shrinkage of the substrate disappeared in the subsequent heat treatment process, and the mask shift was significantly reduced.

After completion of the annealing, a silicon oxide film having a thickness of 2000 to 500 Å was formed as a base oxide film 103 on the surface on which the TFT was formed. As a method of forming this oxide film,
A sputtering method in an oxygen atmosphere and TEOS were decomposed and deposited by a plasma CVD method in an oxygen atmosphere. Further, the film thus formed may be annealed at 450 to 650 ° C.

Then, in FIG. 1A, plasma C
An amorphous silicon film is formed by the VD method or the LPCVD method in the range of 100 to 1500Å, preferably 300 to 800.
Å Deposit and pattern this to form island-shaped silicon regions 104. And the thickness of 200 ~ 1500Å,
Preferably, the silicon oxide 105 having a thickness of 500 to 1000 Å is formed. This silicon oxide film also functions as a gate insulating film. Therefore, sufficient care must be taken in its production. Here, TEOS is used as a raw material, and the substrate temperature is 1 with oxygen.
RF at 50-600 ° C, preferably 300-450 ° C
It was decomposed and deposited by the plasma CVD method. The pressure ratio of TEOS and oxygen is 1: 1 to 1: 3, and the pressure is 0.05 to 0.
The RF power was set to 5 torr and 100 to 250 W. Alternatively, TEOS is used as a raw material and ozone C
The substrate temperature is set to 35 by the VD method or the atmospheric pressure CVD method.
It was formed at 0 to 600 ° C, preferably 400 to 550 ° C. After film formation, 400 ~ in an atmosphere of oxygen or ozone
Annealed at 600 ° C. for 30-60 minutes.

Then, as shown in FIG. 1A, a KrF excimer laser (wavelength 248 nm, pulse width 20 ns) is used.
ec) was irradiated to crystallize the silicon region 104. Laser energy density is 200 ~ 400mJ /
cm ² , preferably 250 to 300 mJ / cm ² ,
The substrate was heated to 300 to 500 ° C. during laser irradiation. Silicon film 104 thus formed
Was investigated by Raman scattering spectroscopy, it was different from the peak of single crystal silicon (521 cm ^-1 ).
A relatively broad peak was observed near 515 cm ^-1 . Then, it was annealed in hydrogen at 350 ° C. for 2 hours.

After that, an aluminum film having a thickness of 2000 Å to 1 μm was formed by electron beam evaporation, and this was patterned to form a gate electrode 106. The aluminum may be doped with scandium (Sc) in an amount of 0.15 to 0.2% by weight. Next, set the substrate pH
It was dipped in an ethylene glycol solution of tartaric acid of 7 to 1-3% and anodized using platinum as a cathode and this aluminum gate electrode as an anode. The anodic oxidation was completed by first increasing the voltage to 220 V with a constant current and maintaining the state for 1 hour. In the present example, in the constant current state, the rate of increase in voltage was 2 to 5 V / min. In this way, the anodic oxide 107 having a thickness of 1500 to 3500Å, for example 2000Å, was formed. (Fig. 1 (B))

After that, an impurity (phosphorus) was self-alignedly injected into the island-shaped silicon film of each TFT by an ion doping method (also referred to as a plasma doping method) using the gate electrode portion as a mask. Phosphine (PH ₃ ) was used as the doping gas. The dose amount is 1 to 4 × 10
^{It was set to 15} cm ^-2 .

Further, as shown in FIG. 1C, a KrF excimer laser (wavelength 248 nm, pulse width 20 ns) is used.
ec) was applied to improve the crystallinity of the portion where the crystallinity was deteriorated by the introduction of the impurity region. The energy density of the laser was 150 to 400 mJ / cm ² , preferably 200 to 250 mJ / cm ² . Thus N
The type impurity (phosphorus) regions 108 and 109 are formed. The sheet resistance in these regions was 200 to 800 Ω / □.
In this step, instead of using a laser, a flash lamp is used to raise the temperature to 1000 to 1200 ° C. (temperature of silicon monitor) in a short time to heat the sample, so-called RTP (rapid thermal process).
May be used.

After that, an interlayer insulator 110 is formed on the entire surface.
Plasma CVD with TEOS as raw material and oxygen
Method, low pressure CVD method with ozone, or atmospheric pressure CV
A silicon oxide film having a thickness of 3000 Å was formed by the D method. The substrate temperature was 250 to 450 ° C., for example 350 ° C.
After the film formation, the silicon oxide film was mechanically polished in order to obtain the flatness of the surface. Further, an ITO film was deposited by the sputtering method and patterned to form a pixel electrode 111. (Fig. 1 (D))

Then, the interlayer insulator 110 is etched to form contact holes in the source / drain of the TFT as shown in FIG. 1E, and wirings 112 and 113 of chromium or titanium nitride are formed, and the wiring 113. Was connected to the pixel electrode 111. At this time, FIG. 1 (F)
Alternatively, the contact holes may be formed by protruding the source / drain regions (island silicon) as shown in FIG. In this case, the area of the contact hole where the island-shaped silicon protruded was 30 to 70%. In this case, contacts are formed not only on the upper surfaces of the source / drain but also on the side surfaces. Hereinafter, such a contact is referred to as a top side contact. In the conventional structure, when the top side contact was formed, the underlying silicon oxide film other than the island-shaped silicon and further the substrate were etched by the etching process of the interlayer insulator. The aluminum nitride film 102 serves as an etching stopper to stop the etching.

In the usual case, it was necessary to make the size of the contact hole smaller than that of the source / drain, but in the case of the top side contact, the size of the island can be made smaller than that of the contact hole. As a result, the island can be miniaturized. On the contrary, since the contact hole can be increased, mass productivity and reliability can be improved. Finally, 300 ~ in hydrogen
Annealing at 400 ° C. for 0.1 to 2 hours completed the hydrogenation of silicon. In this way, the TFT was completed.
A large number of TFTs manufactured at the same time were arranged in a matrix to obtain an active matrix type liquid crystal display device.

Example 2 An example of manufacturing a TFT according to the present invention is shown in FIG. First, on a substrate (NH Techno Glass NA35 glass) 201, a thickness of 1000Å ~
A 5 μm aluminum nitride film 202 was deposited by the reactive sputtering method. Targeting aluminum
Sputtering was performed in an atmosphere of nitrogen and argon. When the proportion of nitrogen was 20% or more, a coating having good thermal conductivity was obtained. The pressure during sputtering is 1 x 10
Preferable results were obtained at ^-4 to 1 x 10 ^-2 Torr. The film formation rate was 20 to 200Å / min. Further, the substrate temperature may be raised to 100 to 500 ° C. during the film formation.

Next, a base oxide film 203 having a thickness of 100 is formed.
A silicon oxide film having a thickness of about 1000 Å, for example, 500 Å, was formed. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere or TEOS was decomposed and deposited by a plasma CVD method in an oxygen atmosphere. Then, this film is 550-700.
Nitrous oxide (N ₂ O) for 4 hours at 650 ° C.
Was annealed in a nitrogen atmosphere containing 20%. By doing so, the aluminum nitride film became transparent and the silicon oxide film thereon could be densified.

After that, an amorphous silicon film of 200 to 150 is formed by a plasma CVD method or an LPCVD method.
0 Å, preferably 300 to 800 Å was deposited and annealed in a nitrogen atmosphere at 600 ° C. for 48 hours. The crystalline silicon film thus obtained was patterned to form island-shaped silicon regions 204. The gate insulating film 207 has a thickness of 200 to 1500Å, preferably 500 to 1
000Å silicon oxide was formed.

Then, a silicon film having a thickness of 2000Å to 5 μm to which phosphorus is added is formed by a low pressure CVD method,
This was patterned to form a gate electrode 209 and a wiring 208. After that, an impurity (phosphorus) was self-alignedly injected into the island-shaped silicon film of the TFT by an ion doping method (also referred to as a plasma doping method) using the gate electrode portion as a mask. Phosphine (PH ₃ ) was used as the doping gas. The dose amount is 1-8x
It was set to 10 ¹⁵ cm ^-2 .

Further, by irradiating a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) and introducing the above-mentioned impurity region, the crystallinity of the portion where the crystallinity was deteriorated was improved. Laser energy density is 150
~ 400 mJ / cm ² , preferably 200-250 mJ
Was / cm ² . Thus, the N-type impurity (phosphorus) region 2
05 and 206 were formed. The sheet resistance in these regions was 200 to 800 Ω / □. (Fig. 2 (A))

After that, a plasma CVD method, a low pressure CVD method, or a normal pressure C is used as an interlayer insulator 210 on the entire surface.
A silicon oxide film having a thickness of 3000 Å was formed by the VD method.
Further, a photoresist 211 was selectively formed. Such a photoresist is preferably formed at the intersection of the wirings or the portion where the wiring is provided with a contact. (FIG. 2 (B)) And, as shown in FIG. 2 (C),
Using the photoresist 211 as a mask, the interlayer insulator 21
0, gate insulator 207, and underlying silicon oxide film 203
Was etched. The underlying silicon oxide film was etched, but the aluminum nitride film served as a stopper and the substrate was not etched. Therefore, a flat surface was obtained. (Fig. 2 (C))

Then, as a wiring material, a titanium film (thickness: 2
2,000 Å ~ 5 μm), and patterning this, wiring 212 connected to the source and drain of the TFT,
213 was formed. Further, ITO was selectively formed to form a pixel electrode 214. Finally, the substrate thus treated was annealed in hydrogen at 1 atm and 350 ° C. for 30 minutes to complete the hydrogenation. In this way, the TFT was completed. A large number of TFTs manufactured at the same time were arranged in a matrix to obtain an active matrix type liquid crystal display device.

Example 3 An example of manufacturing a TFT according to the present invention is shown in FIG. The TFT of the present embodiment is a TFT of a peripheral circuit in a monolithic active matrix circuit having an active matrix circuit and a peripheral circuit for driving the active matrix circuit, particularly, a channel width of 200 to 800.
The present invention relates to a μm driver TFT. Since such a driver TFT controls a large current, it generates a large amount of heat. Therefore, rapid heat dissipation by the underlayer film of the present invention is desired.

First, the substrate (Corning 7059) 301
An aluminum nitride film 302 having a thickness of 2000 to 5000 Å was deposited on the upper surface by a reactive sputtering method. Sputtering was performed in an atmosphere of nitrogen and argon with aluminum as a target. When the proportion of nitrogen was 20% or more, a coating having good thermal conductivity was obtained. A preferable result was obtained when the sputtering pressure was 1 × 10 ⁻⁴ to 1 × 10 ⁻² Torr. The film formation rate was 20 to 200Å / min. Further, the substrate temperature is 100 to 500 ° C. during film formation.
May be raised to.

Next, a base oxide film 303 having a thickness of 100 is formed.
A silicon oxide film having a thickness of 0 to 2000 Å was formed. As a method of forming this oxide film, a sputtering method in an oxygen atmosphere or TE
OS may be a plasma CVD method in an oxygen atmosphere.
Then, an amorphous silicon film of 1000 to 3000 Å, preferably 1000 to 1500 Å was deposited by plasma CVD method or LPCVD method, and annealed in a nitrogen atmosphere at 600 ° C. for 48 hours. The crystalline silicon film thus obtained is patterned to form the island-shaped silicon regions 3
04 was formed. Then, as the gate insulating film 305,
Thickness 200-1500Å, preferably 500-1000
Å Silicon oxide was formed.

Then, an aluminum film having a thickness of 2000Å to 5 μm is formed by the electron beam evaporation method, and this is patterned, and further anodized under the same conditions as in Example 1, and the gate electrode 306, and Wiring 30
Formed 7. (FIG. 3A) After that, TF is performed by an ion doping method (also referred to as a plasma doping method).
Impurities (phosphorus) were self-alignedly implanted into the island-shaped silicon film of T using the gate electrode portion as a mask. Phosphine (PH ₃ ) was used as the doping gas. The dose amount was 2 to 8 × 1015 cm ⁻² . (Fig. 3 (B))

Then, the underlying silicon oxide film 303 was etched. The etching stopped with the aluminum nitride film 302 serving as a stopper. In this state, KrF excimer laser (wavelength 248 nm, pulse width 20 nsec)
By irradiating the substrate, the crystallinity of the portion where the crystallinity was deteriorated was improved by introducing the impurity region. The energy density of the laser is 100 to 400 mJ / cm ² , preferably 1
It was from 00 to 150 mJ / cm ² . Since the silicon oxide film containing phosphorus or boron absorbs ultraviolet light, a strong laser beam was required for subsequent laser annealing after through doping as in Example 1.
However, in this example, if the silicon oxide film (gate insulating film) was removed after the doping, the energy of the laser may be small. Therefore, the throughput of laser processing could be improved. Thus, N-type impurity (phosphorus) regions 308 and 309 were formed. The sheet resistance in these regions was 200 to 800 Ω / □. (Fig. 3 (C))

After that, a plasma CVD method, a low pressure CVD method, or a normal pressure C method is used as the interlayer insulator 310 on the entire surface.
A silicon oxide film having a thickness of 2000 to 3000 Å is formed by the VD method.
An aluminum film (thickness 2000 is formed as a wiring material.
Å ~ 5 μm) is formed and patterned, and TF
Wirings 311 and 312 connected to the source and drain of T were formed. The wiring 312 and the wiring 307 intersect as shown in the figure. (Fig. 3 (C))

Finally, the substrate thus treated is
The hydrogenation was completed by annealing in hydrogen at 350 ° C. for 30 minutes. In this way, the TFT was completed. Similarly, a P-channel type TFT was manufactured by doping the impurity region with boron to manufacture a CMOS circuit. N-channel type, a typical field-effect mobility of P-channel type, respectively, 80~150cm ² / Vs, 40~100cm ²
Was / Vs. It was also confirmed that the shift register manufactured by this TFT operates at 11 MHz at a drain voltage of 17V.

In addition, the gate and drain must be stored for a long time (~ 9
Even if a high voltage (> 20 V) was applied for 6 hours, the deterioration of the characteristics was small. This is because the heat locally generated in the TFT was quickly dissipated, and the desorption of hydrogen from the interface with the semiconductor film or the gate insulating film was suppressed. Actually, a bias application state (gate voltage 11V,
When the state of heat generation at a drain voltage of 14 V) was confirmed by thermography (manufactured by Nippon Avionics Co., Ltd.), a constant temperature rise was not observed in the TFT according to this example, and the temperature rose to about 50 ° C. at most. . However, in the conventional TFT (which does not have an aluminum nitride film as a base film), under the same conditions, it was heated to 100 ° C. or higher in a short time, and the device characteristics were significantly deteriorated. Thus, the effect of the present invention was remarkably confirmed.

[Embodiment 4] This embodiment shows a method of forming a pixel portion of an active matrix type liquid crystal display. This embodiment is shown in FIGS. 4 and 5. First, as the substrate 401, Corning 705 is used.
9 was used. The substrate can be either before or after the formation of the base film,
After annealing at a temperature higher than the strain temperature,
When gradually cooled to a strain temperature of 0.1 to 1.0 ° C./minute or less,
Substantial shrinkage of the substrate in the subsequent process with temperature rise,
Mask alignment is ready. For Corning 7059 substrate, after annealing at 620-660 ° C for 1-4 hours,
0.03 to 1.0 ° C./min, preferably 0.1 to 0.3
It is advisable to perform gradual cooling at ° C / min and take out when the temperature has dropped to 450-590 ° C. In this example, after annealing at 630 ° C. for 4 hours, it was gradually cooled at 0.2 ° C./min.

The thickness of the substrate 401 is 0.1 to 2 μm.
An aluminum nitride film 402 having a thickness of m, preferably 0.2 to 0.5 μm, for example 0.3 μm, was deposited by a reactive sputtering method. Sputtering was performed in an atmosphere of nitrogen and argon with aluminum as a target. When the proportion of nitrogen was 20% or more, a coating having good thermal conductivity was obtained. The pressure during sputtering is 1 × 10 ⁻⁴ to 1 × 1.
Preferable results were obtained at 0 ^-2 Torr. Deposition rate is 2
It was 0-200Å / min. Further, the substrate temperature may be raised to 100 to 500 ° C. during the film formation. The aluminum nitride film 402 may be formed even before the substrate annealing process. After that, a very thin base film 403 of silicon oxide having a thickness of 0 to 1000 Å, preferably 20 to 500 Å, for example, 200 Å was formed by a sputtering method.

After forming the base film, an intrinsic (I-type) amorphous silicon film 404 having a thickness of 300 to 1500 Å, for example, 1000 Å was formed by plasma CVD.
Furthermore, the thickness of 200 to 20 is formed by the plasma CVD method.
A mask film 405 of 00Å, for example 500Å, of silicon oxide or silicon nitride was formed. Then, the mask film 40
5, holes 406 were selectively formed. Further, a nickel film 407 having a thickness of 5 to 200 Å, for example, 20 Å was formed by the sputtering method. A nickel silicide film (chemical formula NiSix, 0.4≤x≤2.
5, for example x = 2.0) may be used. Further, in addition to nickel, copper, palladium, and the like also have a catalytic action for crystallizing amorphous silicon, so that they may be used. (Fig. 4 (A))

Then, under an inert atmosphere (nitrogen or argon, atmospheric pressure) at 550 ° C. for 4 to 8 hours, eg 8
It was annealed for a time to crystallize. In this step, nickel was introduced into the silicon film through the hole 406. Nickel acts catalytically on amorphous silicon to promote crystallization, so that the region 410 immediately below the hole 406 was first crystallized. However, the crystallinity was random in this region. After that, the crystallization spreads from the hole 406 to the periphery along with the diffusion of nickel, the crystallization progressed in the direction of the arrow in the figure, and the region 409 was crystallized. Area 4
In No. 09, crystallization proceeded in one direction, so that good crystallinity was obtained. The region 408 is an uncrystallized region. The size of the crystallized region depended on the annealing time. Mask film 4
When 05 is thin, nickel penetrates from other than the holes 406,
Since crystallization is started, for the purpose of obtaining good crystallinity,
Not good. Therefore, the mask film 405 requires at least 500Å as in the present embodiment.
(Fig. 4 (B))

After this step, the silicon film 404 was patterned by a known photolithography method to form the island-shaped active layer 411 of the TFT. On this occasion,
The tip of the crystal growth in the lateral direction (that is, the crystallized region 409 and the uncrystallized region 408) is formed in the portion to be the channel formation region.
Boundary), and the region 41 into which nickel is directly introduced.
It is important that 0 (both have a high nickel concentration) not exist. By doing this,
It is possible to prevent carriers moving between the source / drain from being affected by the nickel element in the channel formation region. In this embodiment, nickel is selectively introduced into the silicon film, and only the lateral crystallization region 409 is subjected to TF.
Although it was used for the active layer of T, it is also possible to use a crystallized silicon film in which nickel is uniformly introduced without such selective introduction of nickel. However, the characteristics of the TFT in that case are slightly inferior to the former.

4C shows a state during the etching of the silicon film 404. That is, the mask film and the photoresist 41 are formed on the island-shaped active layer 411.
There are two. In this etching process, the underlying silicon oxide film 403 was also etched. (FIG. 4C) After this step, it is necessary to remove the photoresist and also etch the mask film on the active layer 411. This is usually performed using a hydrofluoric acid-based etchant, but in the conventional TFT process, since only the silicon oxide film is used as the base film, the base film is also etched when the mask film is etched. Similarly, there is a problem in that it is etched (in this case, the underlying film is etched at least by the thickness of the mask film of 500 Å). 500
The step of Å was a major cause of disconnection of the gate electrode when the gate electrode was formed later. Therefore, it is necessary to make the mask film thin, but if the mask film is too thin, there is a problem in performing selective crystallization as described above.

However, in this embodiment, since the aluminum nitride film which is hardly etched by hydrofluoric acid is used as the base film, only the mask film can be selectively etched. The step in question was suppressed by adding the thickness t (= 200 Å) of the underlying silicon oxide film 403 to the thickness of the silicon film (1000 Å), and the problem of disconnection of the gate electrode thereafter did not occur.

After forming the active layer in this manner, 0.5 to
4 μm Here, infrared light having a peak at 0.8 to 1.4 μm was irradiated for 30 to 180 seconds to further promote crystallization of the active layer (light annealing (lamp annealing) step or RTP). The temperature is 800 to 1300 ° C, typically 9
The temperature was set to 00 to 1200 ° C, for example, 1100 ° C. This temperature is the temperature of the thermocouple in the single crystal silicon substrate set as a monitor at the same time, not the actual temperature of the substrate surface. Irradiation was carried out in an H 2 atmosphere in order to improve the surface condition of the active layer. In this step, since the active layer is selectively heated, the heating of the glass substrate can be minimized. And, it is very effective in reducing defects and dangling bonds in the active layer. The problem at this time is that the absorption of infrared rays differs depending on the location of the silicon film because the selective crystallization process is used in this embodiment. For example, the active layer 411
In the figure, a phenomenon was observed in which, on the right side of the figure, the above infrared rays were easily absorbed due to the large amount of crystalline components, while on the left side, it was difficult to absorb the infrared rays due to the large amount of amorphous components.

However, in this embodiment, since the aluminum nitride film having good thermal conductivity is used for the base film, the heat absorbed by the silicon film due to the above infrared irradiation is applied to a specific place of the silicon film. Since the silicon film is immediately diffused through the base film without being accumulated, the silicon film is uniformly heated, and thermal distortion is not generated, and the uniformity of the silicon film can be improved. After that, a silicon oxide film 413 having a thickness of 1000 Å was formed as a gate insulating film by the plasma CVD method. TEO as a CVD source gas
S (tetra ethoxy silane, Si (OC ₂ H ₅ ))
₄ ) and oxygen, the substrate temperature during film formation is 300 to 550.
℃, for example 400 ℃.

A silicon oxide film 413 which becomes the gate insulating film
After the film formation, the photo-annealing by irradiation with visible / near infrared light was performed again. By this annealing, it was possible to eliminate the levels mainly at the interface between the silicon oxide film 413 and the silicon active layer 411 and in the vicinity thereof. This is extremely useful for an insulating gate type field effect semiconductor device in which the interface characteristics between the gate insulating film and the channel formation region are extremely important.

Subsequently, by the sputtering method,
A film of aluminum (containing 0.01 to 0.2% scandium) having a thickness of 3000 to 8000 Å, for example, 5000 Å was formed. Then, the aluminum film was patterned to form a gate electrode and a wiring. Further, the surfaces of the aluminum electrodes and wirings were anodized to form an oxide layer on the surfaces. Tartaric acid is 1 to 5 for this anodic oxidation.
% Ethylene glycol solution. The thickness of the obtained oxide layer was 2000Å. Thus, the gate electrode portion (that is, the gate electrode and the oxide layer around it) 414 and the wiring portion 415 were formed. In addition to this, the gate electrode may be made of a metal such as polycrystalline silicon, titanium, tungsten, or tantalum, or a silicide of these metals in a single layer or a multilayer. (Fig. 4 (D))

Next, by the ion doping method (also referred to as plasma doping method), the N conductivity type is imparted in a self-aligned manner to the active layer region (which constitutes the source / drain and the channel) by using the gate electrode portion 414 as a mask. Impurities were added. Phosphine (P
H ₃ ) and an acceleration voltage of 60 to 90 kV, for example 80
It was set to kV. Dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ c
m ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . As a result, N
The impurity regions 416 and 417 of the mold are formed. A silicide such as titanium may be formed in the impurity regions 416 and 417.

After that, annealing was performed by irradiation with laser light. As the laser light, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was used, but another laser may be used. The laser light irradiation conditions are energy density of 200 to 400 mJ / cm ² ,
For example, 250 mJ / cm ² and ² to 10 per place
Shot, for example, 2 shots were irradiated. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the irradiation of the laser light.

Further, this step may be performed by lamp annealing with visible / near infrared light. In the visible / near infrared, crystallized silicon, or phosphorus or boron is 10 ¹⁹ to 10 10.
It is easily absorbed by the amorphous silicon added with ²¹ cm ^-3.
Effective annealing comparable to thermal annealing at 000 ° C. or higher can be performed. When phosphorus or boron is added, the light is sufficiently absorbed even in the near infrared due to the impurity scattering. This can be fully inferred because it is black even when observed with the naked eye. On the other hand, since it is difficult to be absorbed by the glass substrate, it does not require heating the glass substrate to a high temperature and requires only a short treatment time, so it can be said that this is the most suitable method in processes where shrinkage of the glass substrate is a problem. . In this embodiment, since the aluminum nitride film having high thermal conductivity is used as the base film, even in such an annealing process, heat is not accumulated in one place and thermal destruction does not occur. In particular, it was preferable to use an aluminum nitride film as a base film because only a gate electrode is used for thermally weak aluminum.

After that, a silicon oxide film 418 having a thickness of 3000 to 8000 Å, for example, 6000 Å, was formed as an interlayer insulator by the plasma CVD method. As this interlayer insulator, polyimide or a two-layer film of silicon oxide and polyimide may be used. Further, an ITO film having a thickness of 800 Å was formed by a sputtering method and patterned to form a pixel electrode 419. Then, the interlayer insulator is etched with buffered hydrofluoric acid (HF / NH ₄ F = 0.01 to 0.2, for example, 0.1) to contact hole 42.
2, 423 are formed, and a TFT electrode / wiring 4 is formed by a metal material, for example, a multilayer film of titanium nitride and aluminum.
20, 421 was formed. Finally, annealing was carried out at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm to complete a semiconductor circuit having a complementary TFT structure. (Fig. 4 (E))

Particularly in this embodiment, the contact hole 42 is formed.
Nos. 2, 423 were formed at the ends of the active layer, and a part thereof was formed so as to protrude from the active layer. Even with this shape,
In this embodiment, since the aluminum nitride film is used as the base film, there is almost no over-etching on the substrate and the TFT can be formed with good reproducibility. It was manufactured according to the present invention in FIG. As shown in the figure when the TFT is viewed from above, the active layer 411 has a linear shape, and contact holes 422 and 423 are formed at both ends thereof so as to protrude from the active layer. The distance between the active layer and the gate wiring 415 was set to x _{1 and} the distance between the active layer and the pixel electrode 419 was set to x ₂ . This is to prevent the lines from overlapping due to misalignment. In this embodiment, since the area of the active layer is small, the area of the pixel electrode can be increased and the area occupied by the wiring can be reduced.

FIG. 5B shows a conventional TFT viewed from above, and FIG. 5C shows a cross section thereof, which is apparent from FIG. 5B. The active layer is thin and narrow at the gate electrode portion and thick at the source and drain regions. This is the contact holes 522, 5
This is because 23 is surely formed in the source 516 and the drain 517 of the active layer, and the contact hole is formed in the active layer portion even if there is misalignment due to fear of overetching.

However, in such a structure, the active layer area becomes large, and the gate wiring 515 and the pixel electrode 519 are formed.
In order to prevent the overlap with x and x, they are formed separately from the active layer by x ₁ and x ₂ , respectively, and as is clear from the figure, the wiring becomes large and the area of the pixel electrode is reduced. The dotted rectangles in FIGS. 5 (A) and 5 (B) show the same area.
It can be seen that the area occupied by T and the wiring connected thereto is large and the area of the pixel is small, and conversely, in the present embodiment, the area occupied by the TFT and its wiring is small and the area of the pixel is large. As described above, according to the present embodiment, it is possible to improve the pixel / wiring ratio, and consequently to improve the aperture ratio of the liquid crystal display device and miniaturize the pixels. All of these contribute to the improvement of the quality of the liquid crystal display device.

[Embodiment 5] This embodiment shows a method of forming a pixel portion of an active matrix liquid crystal display. FIG. 6 shows this embodiment. First, Corning 7059 was used as the substrate 601. First, an aluminum nitride film 602 having a thickness of 0.1 to 2 μm, preferably 0.2 to 0.5 μm, for example, 0.3 μm was deposited on the substrate 601 by the reactive sputtering method as in Example 4. After that, the thickness is 0 to 1000Å, preferably 20 to 500Å by the sputtering method,
For example, a very thin silicon oxide base film 603 having a thickness of 200 Å was formed. After forming the base film, an island-shaped crystalline silicon region 604 having a thickness of 300 to 1500 Å, for example, 800 Å was formed. Further, the thickness is 1000 by the plasma CVD method.
A silicon oxide film 605 of Å was formed as a gate insulating film.
TEOS and oxygen were used as source gases for CVD.

Thereafter, an aluminum film (containing 1 wt% Si or 0.1 to 0.3 wt% Sc) having a thickness of 1000 Å to 3 μm, for example, 6000 Å was formed by the electron beam evaporation method or the sputtering method. Then, a photoresist (for example, OFPR8 manufactured by Tokyo Ohka) is used.
00/30 cp) was formed by spin coating.
Before forming the photoresist, if an aluminum oxide film with a thickness of 100 to 1000Å is formed on the entire surface of the aluminum film by the anodic oxidation method, the adhesion with the photoresist is good and the By suppressing the current leakage, it was effective in forming the porous anodic oxide only on the side surface in the subsequent anodic oxidation step. After that, the photoresist and the aluminum film were patterned and etched together with the aluminum film to form a wiring 606 and a gate electrode 607. The photoresist 60 is formed on these wirings and gate electrodes.
8 and 609 are left, which will function as a mask for preventing anodization in the subsequent anodization process. (Fig. 6
(A))

Then, an electric current is applied to the above wiring and the gate electrode in an electrolytic solution to carry out anodization to obtain a thickness of 3000Å to 25 μm.
m, for example, 0.5 μm thick anodic oxide 610, 61
1 was formed on the side surface of the gate electrode. Anodization is
5 to 30% using an acidic aqueous solution of 3 to 20% citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, etc.
A constant current of V, for example, 8 V was applied to the gate electrode. The anodic oxide thus formed was porous. In this example, the oxalic acid solution (30
The voltage was set to 8 V in ˜80 ° C.) and anodization was performed for 20 to 240 minutes. The thickness of the anodic oxide was controlled by the anodic oxidation time and temperature. (Fig. 6 (B))

Next, the masks 608 and 609 were removed, and a current was applied again to the gate electrode / wiring in the electrolytic solution. This time, a PH≈7 ethylene glycol solution containing 3 to 10% tartar solution, boric acid, and nitric acid was used. A better oxide film was obtained when the temperature of the solution was lower than room temperature around 10 ° C. Therefore, the gate electrodes / wirings 606 and 607
Barrier type anodic oxides 612, 61 on the top and side surfaces of the
3 was formed. The thickness of the barrier type anodic oxide is proportional to the applied voltage, and for example, the applied voltage was 100 V and 1200 Å anodic oxide was formed. In this embodiment, the voltage is 100
Since the temperature was increased to V, the thickness of the obtained barrier type anodic oxide was 1200Å. The thickness of the barrier type anodic oxide is arbitrary, but if it is too thin, there is a risk that aluminum will be eluted when the porous anodic oxide is etched later, so 500 Å or more was preferable. .

It should be noted that although the barrier type anodic oxide is obtained in a later step, the barrier type anodic oxide is not formed on the outside of the porous anodic oxide, but the porous anodic oxide is formed. A barrier type anodic oxide is formed between the oxide and the gate electrode. (FIG. 6C) After that, the silicon oxide film 605 was etched by a dry etching method. In this etching, a plasma mode of isotropic etching or a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being deeply etched by sufficiently increasing the selection ratio of silicon and silicon oxide. For example, when CF ₄ is used as the etching gas, the anodic oxide is not etched, and therefore the silicon oxide films 614 and 615 existing under the gate electrodes / wirings are left unetched. Also in this etching step, since the aluminum nitride film 602 serves as a stopper, further etching does not proceed and the step difference can be minimized.

Then, the porous anodic oxides 612 and 613 were etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. Then, the active layer 6 of the TFT is formed by the ion doping method.
Impurities were implanted in 04 in a self-aligned manner using the gate electrode portion (that is, the gate electrode and the anodic oxide film around it) and the gate insulating film 615 as masks. In this case, various combinations of impurity regions are possible depending on the acceleration voltage of ions and the dose amount. For example, the acceleration voltage is 50 to
Set to a high value of 90 kV and the dose amount is 1 × 10 ^{13 to} 5 ×
If it is made as low as 10 ¹⁴ cm ⁻² , most of the impurity ions in the regions 616 and 617 pass through the active layer and show the maximum concentration in the base film. Therefore, the regions 616 and 617 are extremely low concentration impurity regions. On the other hand, in the region 618 where the gate insulating film 615 is present, the high speed ions are decelerated by the gate insulating film so that the impurity concentration is just maximized and a low concentration impurity region can be formed.

On the contrary, if the acceleration voltage is set to a low value of 5 to 30 kV and the dose amount is set to a large amount of 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ^-2 , many impurity ions are formed in the regions 616 and 617. Are implanted to form high-concentration impurity regions. On the other hand, in the region 618 where the gate insulating film 615 exists, the gate insulating film blocks low-speed ions, so that the impurity ion implantation amount is low and a low-concentration impurity region can be formed. As described above, whichever method is used, the region 618 becomes a low-concentration impurity region, and any method may be adopted in this embodiment. In this way, the ion doping is performed and the N-type low-concentration impurity region 618 is formed.
After forming the KrF excimer laser (wavelength 248
nm, pulse width 20 nsec) to activate the impurity ions introduced into the active layer. (Fig. 6
(D))

Further, a film of an appropriate metal, for example, titanium, nickel, molybdenum, tungsten, platinum, palladium, etc., for example, a titanium film 619 having a thickness of 50 to 500 Å is formed on the entire surface by sputtering. As a result, the metal film (titanium film here) 619 was formed in close contact with the high-concentration (or extremely low-concentration) impurity regions 616 and 617. (Fig. 6 (E))

Then, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) is irradiated to react the metal film (here, titanium) with silicon of the active layer,
Metal silicide (here, titanium silicide) regions 620, 62
1 was formed. Laser energy density is 200-4
00 mJ / cm ² , preferably 250 to 300 mJ / c
m ² was suitable. Further, if the substrate was heated to 200 to 500 ° C. during laser irradiation, peeling of the titanium film could be suppressed.

After that, the unreacted titanium film was etched with an etching solution in which hydrogen peroxide, ammonia and water were mixed at 5: 2: 2. The titanium film (for example, the titanium film existing on the gate insulating film or the anodic oxide film) other than the portion in contact with the exposed active layer remains in the metal state as it is.
It can be removed by this etching. On the other hand, since titanium silicides 620 and 621 which are metal silicides are not etched,
It was able to remain. In this embodiment, the silicide region 6
The sheet resistance of 20,621 was 10 to 50Ω / □. On the other hand, in the low concentration impurity region 618, 10 to 100 k
It was Ω / □.

After that, an interlayer insulator 622 is formed on the entire surface,
A silicon oxide film having a thickness of 2000Å to 1 μ is formed by the CVD method.
m, for example 5000Å. Then, an ITO film was formed by a sputtering method, and this was patterned and etched to form a pixel electrode 623. Further, the interlayer insulator 622 was etched to form a contact hole. At this time as well, similar to Example 1 and Example 4,
The pattern was such that the contact hole protruded from the source / drain. As described above, such a pattern improves the mass productivity and reliability of the TFT.
Then, wiring / electrodes 624 and 625 made of a multilayer film of titanium nitride and aluminum having a thickness of 2000 Å to 1 μm, for example, 5000 Å were formed. (Fig. 6 (F))

[0072]

According to the present invention, it is possible to manufacture a highly reliable TFT which exhibits sufficient reliability even when a voltage is applied for a long time. Further, it is possible to obtain an unprecedented degree of freedom in arrangement of the active layer and contacts, and it is possible to realize miniaturization of the device. As described above, the present invention has a great industrial value, but in particular, forming a TFT on a large-area substrate and using the TFT in an active matrix or a driving circuit has a large industrial impact.

Although not shown in the embodiments, the present invention may be used for forming a so-called three-dimensional IC in which a semiconductor circuit is further stacked on a single crystal IC or other IC. In addition, although the present invention is mainly used in various LCDs in the embodiments, it is needless to say that the present invention can be applied to other circuits required to be formed on an insulating substrate such as an image sensor.

[Brief description of drawings]

FIG. 1 shows a method for manufacturing a TFT according to the present invention. (Example 1)

FIG. 2 shows a method for manufacturing a TFT according to the present invention. (Example 2)

FIG. 3 shows a method for manufacturing a TFT according to the present invention. (Example 3)

FIG. 4 shows a method for manufacturing a TFT according to the present invention. (Example 4)

FIG. 5 shows a comparison between a TFT according to the present invention and a conventional TFT. (Example 4)

FIG. 6 shows a method for manufacturing a TFT according to the present invention. (Example 5)

[Explanation of symbols]

Reference Signs List 101 substrate 102 coating film containing aluminum nitride as a main component 103 coating film containing silicon oxide as a main component 104 island-shaped semiconductor region (silicon) 105 gate insulating film (silicon oxide) 106 gate electrode (aluminum) 107 anodic oxide (aluminum oxide) 108, 109 N-type impurity region 110 Interlayer insulator (silicon oxide) 111 Pixel electrode (ITO) 112, 113 Metal wiring (chrome or titanium nitride)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 29/78 627E 627G (56) References JP-A-63-142807 (JP, A) JP-A-62-298151 (JP, A) ) JP-A-61-256663 (JP, A) JP-A-59-121876 (JP, A) JP-A-4-192466 (JP, A) JP-A-2-140915 (JP, A) JP-A-2- 153896 (JP, A) E.I. V. Gerova, Deposition of fo ALN thin film by magnetron e active sputtering, Thin Solid Films, 1981, Vol. 81, No. 3, pp. 201-206 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/316 H01L 21/336

Claims (2)

(57) [Claims] 1. A first step of forming an aluminum nitride film on a glass substrate by a sputtering method, and the glass substrate having the aluminum nitride film formed thereon.
Annealed at a temperature higher than the strain point of the glass substrate
Second step of gradually cooling at 0.1 to 1.0 ° C./minute, and third step of forming a silicon oxide film on the aluminum nitride film.
And a fourth step of forming an amorphous silicon film on the silicon oxide film, a fifth step of forming a mask on the amorphous silicon film to expose a part of the amorphous silicon film, a step of the sixth, for thermal processing on the amorphous silicon film, the amorphous silicon layer using the nickel by moving in the amorphous silicon film crystals to form a film containing nickel on the amorphous silicon film formed by the exposed A method of manufacturing a semiconductor device, comprising a seventh step of forming a crystalline silicon film. 2. A method for manufacturing a pre-Symbol heat treatment device according to claim 1, wherein the performed 4-8 hours at 550 ° C..