JP3382026B2 - Clock signal distribution circuit, buffer circuit and design method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of distributing a clock signal by a process using a computer in a layout of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In digital logic integrated circuits, sequential circuits represented by flip-flops are used.
The entire circuit operates while synchronizing with a plurality of clock signals having different phases and cycles. The clock signal is generated inside the chip or supplied from the outside, but is usually supplied to the circuit block via some stages of buffer cells, and CAD is generally provided between the buffer cells and between the buffer cells and the flip-flops. It is automatically connected by the technology.

The propagation delay time (hereinafter referred to as delay) of the clock signal supplied to the flip-flops is usually different for each flip-flop, and the phase difference is called clock skew (hereinafter referred to as skew). A common problem in the design of digital logic integrated circuits is that this skew becomes too large to allow the circuit to operate synchronously at the desired clock frequency. Therefore, it is important to determine the positions of the buffer cells and the wiring paths so that the clock signals arrive at all the flip-flops on the chip at the same timing as possible. It is also important to reduce the clock delay within the chip in order to reduce the skew between chips.

In order to solve these problems, Japanese Patent Laid-Open No.
A clock wiring method represented by 54100 has come to be used. In this method, in the binary tree type wiring structure, the position of each path branch point is determined so that the delay on the downstream side is balanced, and the buffer cell is optimized to minimize the on-chip delay. The position has been determined.

Further, in Japanese Patent Application No. 5-8932,
For the purpose of suppressing an increase in delay due to an increase in wiring resistance, a method of determining an optimum wiring width so as to minimize the delay has been proposed. In this method, the path is formed such that the wiring width becomes thicker from the driven cell side toward the output terminal side of the driving cell. However, in these methods, the delay inside the driving cell was not optimized, so
When performing multi-stage buffering, there was a problem that the delay reduction effect was halved.

On the other hand, as a method for minimizing the delay including the internal structure of the driving cell, reference is made to "HBBakoglu," Ci.
rcuits, Interconnections, and Packaging for VLS
I ”, Chapter 5, Addison-Wesley Publishing Co, Read
ing, Mass., 1990 ”, there is an optimization method when the driving cell is made into a cascade structure (structure in which the size of transistors connected in series is made geometrically large). That is, the drive cell is realized by connecting several CMOS inverters as shown in FIG.
The delay time t _delay when the channel width ω ₀ of the input stage inverter and the load capacitance value C _L of the output stage are given can be expressed by the channel width ω _i of each inverter as follows.

[0007]

[Equation 4] However, τ is a device-dependent constant. When the channel width ω _i and the number of stages N + 1 of each inverter are determined so as to minimize the delay time using the above expression,

[Equation 5] I get the result. However, e is the base of natural logarithm, and ω
_{N + 1} is a constant proportional to the C _L. The above is the conventional technique called the e-times rule. According to the e-fold rule, the total delay time is as follows.

T _delay = τ (N + 1) e (4) If the channel widths of the inverters are all set to the same magnitude ω ₀ with the same number of stages, the total delay time t _delay ′ is t _delay ′ = τ (N + e ^{N +1} ) (5), and t _delay ≦ t _delay ′ is true.

According to this method, when the wiring load on the output side of the driving cell is known, the number of cascade stages and the cascade ratio (ratio of the transistor size of the latter stage to the transistor size of the preceding stage) that minimizes the delay are obtained. But,
Since the wiring RC delay due to the wiring resistance is ignored in the calculation method, there is a problem that the delay is not minimized when the wiring resistance is large.

On the other hand, the total power consumption P due to charging and discharging is

[Equation 6] Is expressed as However, c is a device-dependent constant,

[Equation 7] Is defined as If you follow the e-fold rule

[Equation 8] Becomes However, if all the inverters have the same channel width ω ₀ with the same number of stages, the power consumption P ′ is

[Equation 9] And P ≧ P ′ for N of 0 or more.

Therefore, even if the delay time is minimized, the power consumption is not always so. Since the buffer includes a large inverter, its power consumption is not necessarily small. Therefore, it is of great significance to minimize the power consumption of the buffer.

[0012]

In the conventional method, the intra-chip skew minimization has already reached a high level, but the intra-chip delay minimization for reducing the inter-chip skew is still unsatisfactory. Was enough. In particular, a method of simultaneously optimizing both the internal delay of the drive cell and the wiring shape of the tree wiring portion to minimize the delay has not been established.

A first object of the present invention is to provide a clock signal distribution method including a method for optimizing an internal structure of a driving cell and a wiring width of a wiring tree portion so as to minimize a delay and minimizing a skew. It is to be.

However, as shown in "Prior Art",
Minimizing the delay and minimizing the power consumption may conflict with each other. If the delay is within a certain allowable range, the circuit will be satisfactory.

Therefore, a second object of the present invention is to provide a method of determining the size of each inverter so that the power consumption by the load is minimized under the delay time constraint.

[0016]

Here, in order to minimize both the skew and the delay, as described in Japanese Patent Application No. 5-8932, "the wiring width is fixed and the path branch point that minimizes the skew is determined. The process and the process of fixing the route branch point and determining the wiring width that minimizes the delay are alternately repeated, and the route when the delay converges is the final solution of the clock wiring route. To use.

Then, the above-mentioned process for determining the wiring width is performed by using an approximate model in which the wiring width is a geometric series with respect to the depth on the tree, and the cascade stage number / cascade ratio and The processing step 2A for determining the common ratio of the wiring width and the number of cascade stages / cascade ratios determined in the processing step 2A are fixed, and the wiring width determined in the processing step 2A is used as an initial value and is not necessarily a geometric progression. Process step 2 for determining the optimum wiring width
And B and.

Further, in the processing step 2A,
The delay from the input terminal of the driving cell to the input terminal of the driven cell is expressed by the Elmore equation using the number of cascade stages, the cascade ratio, and the wiring width common ratio as parameters, and then the partial derivative for each parameter of the delay is expressed. Then, the value of each parameter is determined so that the values of the partial derivatives are all zero, or at least one of them is zero.

According to another aspect of the present invention, the CMOS of the circuit input stage of a buffer in which CMOS inverters are connected in series is used.
The channel width of the inverter and the load capacitance value of the output stage are set in advance, and the channel width of each inverter is determined based on the values, and the delay time of the buffer is set so that it does not exceed the maximum allowable value. The ratio of the channel width of the inverter to the rear stage side to the front stage side is increased as the output stage is approached.

[0020]

[0021]

According to the above method, the overall delay including both the internal delay of the driving cell and the wiring delay can be minimized while the skew is extremely small.

Further, by determining the size of each inverter, it is possible to obtain an output buffer circuit which minimizes power consumption under the delay time constraint.

[0023]

EXAMPLES Examples of the present invention will be described below.

In the present embodiment, the overall processing flow for minimizing both skew and delay is as follows: "processing for fixing the wiring width and determining the path branch point where the skew is minimized;
The process of fixing the path branching point and determining the wiring width that minimizes the delay is alternately repeated, and the path when the delay converges is the final solution of the clock wiring path. " It is similar to the one in flat 5-8932.

That is, FIG. 1 is a flowchart showing this processing. However, it is assumed that the topology (tree structure) of the path is previously determined by another method.

First, in step 1, an appropriate initial value is set for the wiring width. In step 2, the path branch point that minimizes the skew in this wiring width is obtained. Here, Japanese Patent Laid-Open No. 3-1
The conventional technique described in 37851 is used. In step 3, the convergence determination is performed, but the first time, the process immediately shifts to the next step. In step 4, the path branch point is fixed as it is, and the wiring width is optimized. After that, the process returns to step 2 and the wiring width is fixed to the value optimized in step 4, and the route branch point that minimizes the skew is obtained. And
The convergence judgment is performed in step 3, and if it is converged, the process is ended.
If it does not converge, steps 2 to 4 are repeated until it converges.

Of these, the step 4 characterizes the present invention.

That is, as shown in FIG. 2, the above-described process for determining the wiring width is performed by using an approximation model in which the wiring width is a geometric series with respect to the depth on the tree. The processing step 2A for determining the number of stages / cascade ratio and the common ratio of the wiring width, and the number of cascade stages / cascade ratio determined in the processing step 2A are fixed, and the wiring width determined in the processing step 2A is used as an initial value. , Processing step 2B for determining an optimum wiring width which is not necessarily a geometric series.

As for the processing for determining the path branching point that minimizes the skew in the overall processing flow and the processing step 2B, the method described in Japanese Patent Application No. 5-8932 may be used as it is, and the description thereof will be omitted.

With respect to the processing step 2A, an optimization method of the number of cascade stages / cascade ratio of the cascade driver cell and the wiring width of the tree wiring path on the output side according to the present invention will be described below.

(1) Model clock signal for clock distribution As shown in FIG. 3, it is assumed that a clock signal is supplied to a driven cell through a cascade type driving cell through a binary tree type tree wiring path. The driver cell 1 forming each stage of the cascade is usually composed of two inverters. The drive cell has a cascade structure in which the transistor size increases in geometric progression, the cascade ratio is b, and the number of cascade stages is n. In the wiring tree part driven by the driving cell, the depth of the tree (the number of tree edges passing through in the path from the driver cell to the driven cell) is m, and the wiring width is geometrically thick from the end side. And the common ratio is a.
In fact, when the wiring width is determined so as to minimize the delay, the model is empirically close to a geometric series, so this model is considered to be a good approximation for optimization.

At this time, the delay T from the input terminal of the cascade driver cell to the input terminal of the driven cell, that is, the combination of the internal delay of the driving cell and the delay of the wiring is given by the formula of Elmore,

[Equation 11] Is expressed as

Here, C (K): load capacity on the downstream side of the node of the tree depth k in the wiring tree part L _k : node of the tree depth k in the wiring tree part and its wiring distance R _{g to} its parent node : ON resistance of the minimum size transistor C _g : Input terminal capacitance w of the minimum size transistor w: Minimum wiring width (tree depth m in the wiring tree portion)
Wiring width of the portion) ζ: Proportional coefficient of wiring width in calculation of wiring load capacitance f: Constant not depending on wiring width in calculation of wiring load capacitance (fringe effect) ρ: Sheet resistance of wiring

In the above equation, the first term on the right side represents the internal delay of the cascade driver, the second term represents the delay for charging and discharging the wiring tree portion by the on-resistance of the final stage of the cascade driver, and the third term. Represents the RC delay of the wiring tree portion. In the calculation of the wiring load capacitance, the wiring load capacitance value per unit length when the wiring width is ω is approximated to ζ (ω + f).

(2) Method of obtaining n, b, and a that minimizes the delay To obtain the minimum value of the delay T, partial derivatives for respective parameters of n, b, and a are obtained, and the values of the partial derivatives are calculated. The value of each parameter may be determined so that all are zero. That is, the numerical value of each variable may be determined so that ∂T / ∂n = ∂T / ∂b = ∂T / ∂a = 0. Among them, when ∂T / ∂n = 0 is solved, C (0) = C _g b ⁿ · lnb is obtained, and when ∂T / ∂b = 0 is solved, C (0) = C _g b ⁿ is obtained. can get. Therefore, b = en = ln (C (0) / _Cg ) is obtained from these two equations. This is a well known e-law.

Next, substituting this result into the equation of T gives: T = eR _g C _g · ln (C (0) / C _g ) + D (a). Here, if ∂T / ∂a = 0,

[Equation 12] Becomes

To obtain a that satisfies this equation, it is easy to use the Newton-Raphson method or the like. Note that C
Since (k) is a polynomial of a and its degree is m−k−1, ∂T / ∂a is a rational function with respect to a.

Further, by substituting the solution a into the equation 2, b is obtained, and from the above, each parameter of n, b, and a can be determined.

(3) Minimization of delay when b and n are fixed In an actual design, in order to reduce the cell area,
Often b and n are predetermined. The delay minimization method for such a case will be described below.

First, the method when b is fixed will be described. In this case, when solving ∂T / ∂n = 0, C ( 0) = C g b n · lnb than n = (lnC (0) -ln (C g · lnb)) becomes / LNB. Substituting this into Equation 11,

[Equation 13] T = R _g C _g b {(lnC (0) −ln (C _g · ln
b)) / lnb + lnb-1} + D (a).

Further, if ∂T / ∂a = 0, then

[Expression 14] (b / lnb) R _g C _g · (∂C (0) / ∂a)
/ C (0) + D '(a) = 0. This formula differs from the formula in the previous section only in that the coefficient (b / lnb) is attached instead of e. The definition of D '(a) is the same as in the previous section. Therefore, the solution of this equation can be obtained in the same way as in the previous section.

Next, a method when n is fixed will be described. In this case, when solving ∂T / ∂b = 0, a _{C (0) = C g b} n from b = (C (0) / C g) 1 / n. Substituting this into equation 1, the _{T = nR g C g (C} (0) / C g) 1 / n + D (a). Furthermore, if ∂T / ∂a = 0,

[Equation 15] R _g C _g (C (0) / C _g ) ^{1 / n} ) ∂C (0) / ∂
a) / C (0) + D '(a) = 0. The solution of this equation can also be easily solved by the Newton-Raphson method.

As described above, even when n and b are fixed, the parameter that minimizes the delay can be determined in the same manner as the method described in the previous section.

(4) Upper limit values of parameters n and b In the following, in the practical use range, parameters n and b
How to give the upper limit of b will be described. This upper limit is
This is to serve as a guideline for actual design.

In calculating the upper limit value, it is approximated that the wiring path of the wiring tree portion is a completely symmetrical H-shaped repetition, and the tree depth m is an even number.

At this time, ignoring the input terminal capacitance of the driven cell at the end of the tree,

Equation 16] _{L 1 = L 2, L 3} = L 4 = L 1/2, L 5 =
^{_{L 6 = L 1/2 2}} , ..., from the _{L 2m-1 = L 2m =} L 1/2 m / 2-1

[Equation 17] Becomes

[0047] ^{Here, (a 2/2) m} / 2 »1» (1 /
2) When approximated to ^{m / 2} ,

[Equation 18] C (0) = ζL ₁ {wa ^m (a + 2) / (a ²
/ 2-1) + 6f2 ^{m / 2} .

It is empirically known that the parameter a for minimizing the delay is 1≤a≤3. Therefore, the upper limit of C (0) is the numerical value when a = 3, that is,

[Equation 19] C (0) ≤ C (0) _max = ζL ₁ {w (10/7) 3 ^m
+ 6f2 ^{m / 2} }.

On the other hand, the parameter n for minimizing the delay
The condition that ∂T / ∂n = 0, i.e., n = (lnC (0) -ln (C g · lnb)) / satisfies the LNB. Therefore, the upper limit of the parameter n is

N ≦ n _max = (1 / lnb) ln [{w (10/7) 3 ^m
+ 6f2 ^{m / 2} } ζL ₁ / (C _g · lnb)]. Especially when b = e,

N _max = ln [{w (10/7) 3 ^m + 6f2 ^{m / 2} } ζ
L ₁ / C _g ].

Similarly, the parameter b that minimizes the delay satisfies the condition of ∂T / ∂b = 0, that is, b = (C (0) / C _g ) ^{1 / n, so} that the upper limit of this parameter b is satisfied. value is,

B ≦ b _max = [ζL ₁ {w (10/7) 3 ^m + 6f
2 ^{m / 2} } / C _g ] ^{1 / n} .

As described above, by using the above equations, the upper limits of n and b can be set, and a guideline for layout design can be obtained.

In the above embodiments, the case where the wiring tree has one stage has been described. However, even in the case of a multi-stage wiring tree, it is possible to easily extend and apply it by applying the above processing to each stage. .

In the above embodiment, the conditions for minimizing the delay time were obtained. That is, the cascade ratio is always constant,
Ideally, it will be e. However, as mentioned above, this is not the most advantageous design in terms of power consumption. If there is a margin in the delay time, the power consumption should be completely turned over for the over-spec. In the following, a design that minimizes power consumption will be considered on the condition of the maximum delay time T allowed in the driving cell.

Consider an output buffer circuit as shown in FIG. 5 in which the channel width ω ₀ of the first stage inverter and the load capacitance value C _L of the output stage are given.

First, let's obtain the delay time of this circuit.

The contribution t _delay ⁱ from the i-th inverter to the delay time is

[Equation 23] Is. Where C _i is the load capacitance for the i-th inverter, β _i is the gain coefficient of the MOS transistor of the i-th inverter, V _DD is the power supply voltage, and V _T is the threshold voltage. C _i and β _i can be expressed as follows by the channel widths ω _i and ω _{i + 1} of the i-th and i + 1-th inverters.

C _i = cω _{i + 1} , β _i = γω _i (i = 0, ..., N) (11) Here, the load capacitance C _i is approximated by the gate capacitance of the next-stage inverter, and c is The gate capacitance C _ox per unit area and the channel length L can be expressed as c = C _ox L. Normally, L is set to the same value for all inverters, so c is a constant independent of the inverter. Further, γ can be expressed as γ = K _P / L by the process gain coefficient K _P and the channel length L. I = N in the above formula
, The left side is C _L , so ω _{N + 1} is ω _{N + 1} = C _L /
It is a constant defined by c. From the above, the total delay time t _delay can be expressed as follows.

[0058]

[Equation 24] However,

[Equation 25] Was defined.

On the other hand, the total power consumption P due to charging and discharging is

[Equation 26] Becomes

From the above, under the constraint condition that the total delay time is T, the condition for minimizing the power consumption is:
According to Lagrange's undetermined coefficient method

[Equation 27] Is obtained by minimizing Here, λ is a Lagrange's undetermined coefficient and is a real number of 0 or more. Also

[Equation 28] Was defined. The condition for minimizing L is ω _i (i
= 1, ..., N), and is obtained by setting the differential coefficient for λ to 0. In particular

[Equation 29] Becomes It should be noted here that when λ = 0, e
It means that the rule is doubled. Moreover, since λ ≧ 0 from the condition of the minimum value that the second derivative is positive, the inequality

[Equation 30] Holds.

In order to make the above equation easier to handle, the following definitions are made.

[0062]

[Equation 31] Then (16)

[Equation 32] Becomes further

[Expression 33] It must also be noted that the relationship By definition, ω ₀ and ω _{N + 1} are constants. If x ₀ , ..., X _{N + 1} are determined by the above equations, ω ₁ ,
…, Ω _N can be expressed as follows.

Ω _i = ω ₀ x ₁ ... X _i (i = 1, ..., N) (22) Substituting these equations into the equation of power consumption, the power consumption is expressed as a function of the number N of stages of the inverter. Can be done. N is the optimum number of inverter stages that minimizes power consumption at that time. On the other hand, the possible value of N is limited by (16). Let f (N) be the minimum value on the left-hand side of the second equation of (16) as a function of N. Then

[Equation 34] Becomes N must satisfy f (N) ≦ S. The maximum non-negative integer N that satisfies this is N _max , and the minimum non-negative integer N is N _min . Also, f (N) is N = logR-1
Since the minimum value elog R is taken at, elog R ≦ S (24) must be satisfied for the solution to exist.

Now, let us describe a method for obtaining x ₀ , ..., X _{N + 1} .

For N = 0, (20) and (21) result in the equation R = S. If this is not the case, N
The solution of = 0 is impossible. Also, the power consumption at this time is

[Equation 35] Becomes

When N = 1, x ₁ and x ₂ are quadratic equations x
Becomes a ² -Sx + 2 roots of R = 0, the power consumption when x ₁ ≦ x ₂ is optimized.

The power consumption is

[Equation 36] Given in. However,

[Equation 37] Is. Of these two solutions, the one with the smaller value reduces the power consumption, so the minus sign is the solution.

When N ≧ 2, it becomes more complicated. By (19), x ₂ , ..., x _{N + 1} can be expressed as x ₀ , x ₁ , but by substituting them into (20), (21), we obtain two equations for x ₀ , x _1. . However, the expression is complicated and it is almost impossible to obtain the solution in the form of mathematical expression for arbitrary N ≧ 2. Therefore, there is no choice but to use the numerical solution.
As the method, the Newton-Raphson method in the case of two dimensions is used. Let us briefly describe the Newton-Raphson method for the two-dimensional case.

Consider numerically obtaining a solution that satisfies the two equations f ₀ (x ₀ , x ₁ ) = 0 and f ₁ (x ₀ , x ₁ ) = 0 (28). First, numerical values x ₀ and x ₁ are given appropriately. Then δx ₀ , x ₁

[Equation 38] Then, x ₀ + δx ₀ , x ₁ + δx ₁ are newly defined as x ₀ and x ₁ . The above procedure is repeated until δx ₀ ² + δx ₁ ² ≤δ _max is satisfied for a preset value δ _max . X at that time
₀ and x ₁ are approximate solutions of (28). If the above is two-dimensional
Newton-Raphson method.

In order to actually carry out what has been described above, the following algorithm may be followed as shown in FIG.

As the 1 ° input, the channel width ω ₀ of the first stage inverter, the load capacitance value C _L for the last stage, and the maximum value T of the allowable delay time are given (step 1). The 2 ° constants S and R are determined by the following formula (step 2).

[0072]

[Formula 39] Here, c, γ, V _DD and V _T have already been described.

The minimum non-negative integer N _min and the maximum non-negative integer N _max satisfying 3 ° (N + 1) R ^{1 / N + 1} ≦ S are obtained (step 3). If such an integer N _min , N
_{If max} does not exist, stop. Set 4 ° N = N _min (step 4). If 5 ° N ≠ 0, go to 8 ° (step 5). If 6 ° R ≠ S, set ω ₁ = ∞ and proceed to 14 ° (steps 6 and 7). If 7 ° R = S, then ω ₁ = C _L / c is set to 14 ° (steps 6 and 8). 8 ° Appropriate values x ₀ and x ₁ are given (step 9). 9 ° recurrence formula

[Formula 40] By

[Formula 41] Ask for.

10 °

[Equation 42] And substituting them into an expression that is partially differentiated with respect to x ₀ and x ₁ .

11 ° δx ₀ , δx ₁

[Equation 43] (Step 10).

If 12 ° δx ₀ ² + δx ₁ ² > δ _max , x ₀ + δx ₀ , x ₁ + δx ₁ are newly set as x ₀ and x ₁ to 9 ° (step 11).

[0077] 13 [deg recurrence formula _{ω i = ω 0 x 1 ...} x i (i = 1, ..., N + 1) obtaining the omega _i by (37) (step 12).

14 ° power consumption

[Equation 44] Is calculated (step 13).

15 ° N + 1 is newly set as N (step 14). If 16 ° N ≦ N _max , go to 8 ° (step 15). 17 ° finish.

In the above algorithm, some P
(N) is obtained, but the smallest one is adopted.
As described above, the buffer with the minimum power consumption due to charge and discharge is obtained under the delay time constraint. FIG. 4 shows a flow showing the above algorithm.

In the above method, the Newton-Raphson method may fail. That is, the solution does not converge. In such a case, either the initial value is bad or there is really no solution. In the former case, the initial value may be appropriately retaken and the Newton-Raphson method may be applied again. However, since it cannot be repeated infinitely, it is necessary to round up at an appropriate point and regard it as the latter case, and perform the trial for the next N. In some cases, a negative x _i (i
= 1, ..., N) may be obtained as an unrealistic case such as obtaining a solution, but in such a case, the same treatment may be necessary.

In Table 1, V _DD = 5 (volt), V _T = 0.6
(Volt), K _P = 35.0 (μA / V ² ), L = 4.0
(Μm) and C _ox = 3.5 × 10 ⁻⁴ (pF / μm ² ), ω ₀ = 2 (μm) and C _L = 0.2494
3 (pF), T = 0.0094656 (nsec), and the delay time and power consumption for the input are compared with those of the e-fold rule.

Although the above method is a method of determining the channel width and the number of stages of each inverter by giving the channel width of the input stage and the load capacitance of the output stage, the load capacitance of the output stage and the inverter are determined in exactly the same manner. Can be applied when the channel width of each inverter and the channel width of the input stage are determined by giving the number of stages of. Alternatively, it can be applied to a case where the channel width of each inverter and the load capacity of the output stage are determined by giving the channel width of the input stage and the number of stages of the inverter.

[0084]

[Table 1] The above method has general applications. For example, as shown in FIG. 6, even when the chains 31 and 32 of separate inverters are connected as inputs to the gates of the PMOS and NMOS of the final stage inverter,
A similar method can be applied to chains. in this case,
The load capacitance for each inverter chain can be approximated by the gate capacitance of the connected MOS transistors.

[0085]

As described in detail above, according to the present invention, it is possible to obtain a drive cell structure and a clock wiring path having a skew value close to zero and a minimum delay value. In particular, with respect to the delay, it is possible to further reduce the delay as compared with the case where only the wiring width is optimized and the delay is minimized.

Further, when the size of each inverter is determined according to the present invention, an output buffer circuit can be obtained in which the power consumption is minimized under the delay time constraint.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall processing flow of the present invention.

FIG. 2 is a diagram showing a processing flow representing a feature of the present invention.

FIG. 3 is a diagram schematically showing a structure of clock supply.

FIG. 4 is a flowchart showing a feature of the present invention suitable for power saving.

FIG. 5 is an output circuit composed of a chain of CMOS inverters.

FIG. 6 is a final stage C in which a chain of two CMOS inverters is provided.
It is an output circuit connected to a MOS inverter.

[Explanation of symbols]

1 Transistor constituting a cascade type drive cell 2 Tree wiring 21 Load capacity for inverter at output stage 31 Inverter chain connected to PMOS gate at final stage 32 Inverter chain connected to NMOS gate at final stage

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 H01L 27/04 H01L 21/822 H01L 27/08 H03K 19/00 G06F 17/50

Claims (4)

(57) [Claims] 1. A cell having a cascade structure in which the size of transistors connected in series is enlarged in a geometric progression is used as a drive cell, and the drive cell is used as a starting point.
In a clock signal distribution circuit for supplying a signal to a plurality of driven cells by a branch tree type tree wiring path, the ratio (cascade ratio) of the transistor size of the driving cell to the preceding transistor size is b, the number of cascade stages is n, and the driving cell is , M is the number of tree edges passing through the path from the driven cell to the driven cell, L1 is the wiring distance between the branch node having a tree depth of 1 in the wiring tree part and its parent node, and Cg is the input terminal capacitance of the minimum size transistor. Let w be the minimum wiring width of the tree wiring path, and let ζ be a proportional coefficient to the wiring width when the wiring load capacitance value per unit length when the wiring width is ω is approximated to ζ, and express the fringe effect. If a constant that does not depend on the wiring width is f, and the b, n, m are n ≦ (1 / lnb) ln [{w (10/7) 3 m + 6f2 m / 2} ζL 1 / (Cg · ln )] Of inequality _{or,, b ≦ [ζL 1 {} w (10/7) 3 m + 6f2 m / 2} Cg] 1 / n
The clock signal distribution circuit is characterized by satisfying at least one of the inequalities. 2. A clock signal is driven by a cascade type drive cell, and the wiring shape on the output side is a binary tree type, and the topology structure of the path is determined in advance, and each wiring of the path between adjacent branch points. A first process for minimizing the skew by recursively repeating the process of fixing the width and determining the branch points so that the delays on the downstream side from the respective branch points are balanced from the lower part of the tree to the upper part; The second process of fixing the position of each path branch point and determining each wiring width so as to minimize the delay, and the process of repeating these processes alternately, the delay change amount after the process step is within the allowable value. In the method of designing the clock signal distribution circuit, which comprises a third process for determining whether or not the line width has reached, the second process has a wiring width A first step of determining the number of cascade stages / cascade ratio of the cascade-type drive cell and the common ratio of the wiring width using an approximate model that forms a geometric series with respect to the depth on the Lee; A second step of fixing the number of cascade stages and the cascade ratio determined in the step and using the wiring width determined in the first step as an initial value, and determining an optimal wiring width without using the approximation model based on the geometric series. In the first step, the delay function from the input terminal of the driving cell to the input terminal of the driven cell is obtained with the number of cascade stages, the cascade ratio, and the wiring width common ratio as parameters, and for each parameter A method for designing a clock signal distribution circuit, characterized in that the value of each parameter is determined so that at least one of the partial derivative values becomes zero. 3. A channel width of a CMOS inverter in a circuit input stage of a buffer in which CMOS inverters are connected in series,
Set the load capacitance value of the output stage in advance, and based on that value,
A method of designing a buffer circuit for determining each channel width of each inverter, wherein the delay time of the buffer does not exceed the maximum allowable value, and the ratio of the channel width of the adjacent inverter to the latter stage side of the former stage side, A method of designing a buffer circuit, comprising increasing the number as it approaches the output stage. 4. A buffer circuit in which CMOS inverters are connected in series, wherein a ratio of a channel width of an adjacent inverter to a rear stage side to a front stage side increases as it approaches an output stage of the buffer circuit. A buffer circuit characterized in that.