JP3375583B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using a compound semiconductor substrate.

[0002]

2. Description of the Related Art Semi-insulating compound semiconductor substrates such as Ga
A metal-semiconductor contact field effect transistor (hereinafter referred to as MESFET) formed on an As substrate is a power device capable of obtaining high gain and high efficiency in a high frequency band, and in recent years, as a transmission device such as mobile communication equipment. Demand is increasing. In this MESFET manufacturing method, there are two methods of forming an active layer: one using an epitaxial growth method and one using an ion implantation method.
The methods are roughly classified.

29 and 30 show each process of manufacturing a conventional MESFET using the selective ion implantation method (Source: Takuo Sugano, edited by Masamichi Omori, "Ultra High Speed Compound Semiconductor Device" page 75: Baifukan Published).

First, as shown in FIG. 29 (a), GaA
a silicon nitride film 2 on a semi-insulating substrate 200 made of s.
01 is deposited on the silicon nitride film 201.
The resist mask 202 is formed. Then, Si ions are implanted using the first resist mask 202 to form a channel region on the semi-insulating substrate 200.
The mold region 203 is formed.

Next, as shown in FIG. 29B, Si ions are implanted using the second resist mask 204 formed on the silicon nitride film 201, so that the semi-insulating substrate 200 is formed. An n + type region 205 to be a source / drain region is formed.

Next, as shown in FIG. 29C, after forming an insulating film 206 on the silicon nitride film 201, the silicon nitride film 201 and the insulating film 206 are used as protective films to form the n-type regions 203 and n +. Annealing treatment is performed on the mold region 205.

Next, as shown in FIG. 30A, the n + type region 2 in the silicon nitride film 201 and the insulating film 206 is formed.
After forming an opening above 05, an ohmic electrode 207 connected to the n + type region 205 is formed in the opening.

Next, as shown in FIG. 30B, the n-type region 20 in the silicon nitride film 201 and the insulating film 206.
After the opening is formed on the upper side of 3, the gate electrode 208 is formed in the opening and the first-layer metal wiring 209 is formed on the ohmic electrode 207.

Next, as shown in FIG. 30C, after depositing an interlayer insulating film 210, the interlayer insulating film 210 is deposited on the interlayer insulating film 210.
A second metal wiring 211 that is electrically connected to the first layer metal wiring 209 is formed.

By the way, a power MES that handles large signals
To improve the high frequency characteristics and efficiency of the FET, M
Characteristics of ESFET (for example, transfer conductance: gm
And K value), and for that purpose, it is important to make the active layer highly concentrated and thin.

However, in the power MESFET, it is necessary to improve the characteristics of the MESFET and maintain a high gate-drain breakdown voltage. However, the improvement of the breakdown voltage between the gate and drain is due to the MESFET.
, That is, transfer conductance: There is a trade-off relationship with improvement of gm and K value.

Therefore, in order to improve the breakdown voltage between the gate and the drain, as shown in FIG. 31, the semi-insulating substrate 22 is used.
Gate electrode 22 in the active layer 221 formed on
A structure in which a portion immediately below 2 is removed by etching (hereinafter,
Recess structure) is used. In FIG. 31, 223 is an insulating layer, 224 is a source electrode, 225 is a drain electrode, and 226 is a recessed space. still,
In order to improve the breakdown voltage between the gate and the drain, FIG.
, The gate electrode 222 and the drain electrode 225
An asymmetric structure in which the distance between and is larger than the distance between the gate electrode 222 and the source electrode 224 is often used.

Further, in order to improve the miniaturization of dimensions and the improvement of withstand voltage characteristics, in the conventional self-alignment type MESFET using ion implantation, an MESFET adopting the LDD structure shown in FIG. 32 is also known. M shown in the figure
In the ESFET manufacturing process, the semi-insulating GaAs substrate 23 is used.
Active layer 233 is formed in a predetermined region of 0, and semi-insulating GaA
After the WSi, which is a refractory metal, is deposited on the entire surface of the s substrate 230 to form a WSi film, the WSi film is patterned to form the gate electrode 236. Next, low concentration impurity ions are implanted using the gate electrode 236 as a mask to form low concentration source / drain n − type regions 241 and 242.
After the formation, the high-concentration impurity is ion-implanted to the outside by photolithography to form n + type regions (high-concentration layers) 238 and 239 to be the source / drain. Furthermore, after depositing the SiN film 243, the SiN film 2 is deposited.
A part of a portion of the portion 43 immediately above the n + type regions 238 and 239 is opened, and ohmic electrodes 244 and 245 made of AuGe.Ni.Au are formed in this opening. In the MESFET shown in the figure, n + type regions 238, 2
39 and the active layer 233 which is a channel region, an n − -type region 24 functioning as a low concentration source / drain is formed.
1, 242 are provided, and the source-side n--type region 24 is provided.
1 is narrower than the drain side n-type region 242. That is,
Similar to the FET shown in FIG. 31, the structure of the FET shown in FIG. 32 is left-right asymmetric. That is, the source side n +
The source region is reduced by bringing the type region 238 and the gate electrode 236 close to each other, while the n + type region 2 on the drain side is formed.
By separating 39 and the gate electrode 236, the breakdown voltage between the gate and the drain is improved.

[0014]

However, the MESFET formed on the conventional compound semiconductor substrate has the following problems.

First, the recess structure shown in FIG. 31 and the structure shown in FIG.
There is a limit to the improvement of the breakdown voltage between the gate and the drain only with the asymmetric structure of the source and the drain shown in FIG.

Secondly, in the MESFET using a compound semiconductor substrate such as a GaAs substrate, it is known that the stress applied to the gate electrode causes piezo electric charges to change the threshold voltage. There is a problem in that improvement and yield cannot be expected sufficiently.

In view of the above, an object of the present invention is to form a steep carrier profile in the vicinity of the surface of a compound semiconductor substrate, thereby making it possible to form a high-performance semiconductor device utilizing the characteristics of this carrier profile. Another object of the present invention is to provide a method of manufacturing a semiconductor device.

[0018]

A first method of manufacturing a semiconductor device according to the present invention is the method of manufacturing a semiconductor device mounted on a compound semiconductor substrate, wherein a metal film for forming an electrode is formed on the compound semiconductor substrate. A step of depositing, and a step of implanting impurity ions into the compound semiconductor substrate through the metal film to form an active layer of the first conductivity type at a portion of a predetermined depth from the surface of the compound semiconductor substrate, Impurity ions are implanted into a surface region of the active layer including a region located directly below and on both sides of the gate electrode through the metal film, and a high concentration is implanted in at least a part of the surface region of the active layer. Forming a resistance layer; and implanting impurity ions into a portion of the high resistance layer directly below the gate electrode to form a second conductivity type impurity diffusion layer shallower than the high resistance layer. Patterning the metal film and a step of forming an electrode of a semiconductor device on said impurity diffusion layer.

According to this method, the impurity ion through implantation through the metal film makes the impurity profile near the surface of the compound semiconductor substrate steep, and by using this steep profile, it is possible to form a device such as a high-performance FET. become. Further, since the portion directly under the electrode is a high resistance layer, it is possible to form a device such as an FET having a high gate-drain breakdown voltage. Then, since a pin junction including an active layer, a high resistance layer on the active layer, and an impurity diffusion layer having a conductivity type opposite to that of the active layer is formed below the electrode, the pin junction is formed. It is possible to form a device such as a pin junction gate FET having a high performance and a high degree of freedom of design by utilizing the above.

A second semiconductor device manufacturing method according to the present invention comprises:
In a method of manufacturing a semiconductor device mounted on a compound semiconductor substrate, depositing a metal film for forming an electrode on the compound semiconductor substrate, and implanting impurity ions into the compound semiconductor substrate through the metal film. Forming a first conductivity type active layer at a predetermined depth from the surface of the compound semiconductor substrate, and directly below and on both sides of the gate electrode in the surface region of the active layer via the metal film. Impurity ions are implanted into a region including a region located on the one side,
Forming a high resistance layer in at least a part of a surface region of the active layer; and implanting impurity ions into a portion of the high resistance layer directly below the gate electrode to form a shallower region than the high resistance layer. The method includes a step of forming an impurity diffusion layer of one conductivity type and a step of patterning the metal film to form an electrode of a semiconductor device on the impurity diffusion layer.

By this method, similar to the method of manufacturing the first semiconductor device, the impurity profile near the surface of the compound semiconductor substrate becomes steep, and the steep profile can be used to form a device such as a high-performance FET. become.
Further, since the portion directly under the electrode is a high resistance layer, it is possible to form a device such as an FET having a high gate-drain breakdown voltage. Then, unlike the first method for manufacturing a semiconductor device, an active layer, a high resistance layer thereabove, and an impurity diffusion layer having the same conductivity type as that of the active layer are formed below the electrode. Therefore, by adjusting the depth and width of the high resistance layer and the impurity diffusion layer, F having a large driving force and a high degree of design freedom can be obtained.
It is possible to form devices such as ET.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A method for manufacturing a field effect transistor according to a first embodiment of the present invention will be described below with reference to FIGS.

First, as shown in FIG. 1A, a first resist mask 11 is formed by photolithography on one main surface of a semi-insulating GaAs substrate 10 as a compound semiconductor substrate, and then the first resist mask 11 is formed. Using the first resist mask 11, Si ions are implanted into a predetermined region of the GaAs substrate 10 at an acceleration voltage of 80 keV to form an n-type active layer 12.

Next, as shown in FIG. 1 (b), GaAs
A second resist mask 13 is formed on one main surface of the substrate 10 by a photolithography technique, and then Si ions are implanted into a predetermined region of the active layer 12 at 150 keV using the second resist mask 13 to n +. Source region 14 of mold
And the drain region 15 is formed.

Next, as shown in FIG.
After depositing a silicon oxide film 16 as a first insulating film over the entire main surface of the substrate 10, an annealing process is performed at a temperature of 820 ° C. for 15 minutes using the silicon oxide film 16 as a protective film. As a result, the implanted Si is activated.

Next, as shown in FIG. 2A, after depositing a silicon nitride film 17 as a second insulating film on the silicon oxide film 16, a photolithography technique is applied on the silicon nitride film 17. Thus, a third resist mask 18 having an open source / drain electrode formation region is formed.

Next, as shown in FIG. 2B, an opening is formed by etching the silicon oxide film 16 and the silicon nitride film 17 using the third resist mask 18. After that, AuGe / N is placed in the opening.
After i / Au is vacuum-deposited, sintering is performed in an Ar gas atmosphere at a temperature of 450 ° C. for 3 minutes to form the source electrode 19 and the drain electrode 20 made of ohmic electrodes.

Next, as shown in FIG. 2C, a fourth resist mask 21 having a gate electrode formation region opened is formed on the silicon nitride film 17 by photolithography.

Next, as shown in FIG. 3A, dry etching is performed on the silicon nitride film 17 by reactive dry etching (hereinafter referred to as RIE) using CF ₄ gas. In the present embodiment, since the silicon nitride film 17 has a film thickness of 0.5 μm, the etching of the silicon nitride film 17 is completed in about 4 minutes and 30 seconds.
However, in the present embodiment, the silicon nitride film 17
By performing over-etching for 60 seconds, the upper layer portion of the silicon oxide film 16 in the gate electrode formation region is removed and the carrier concentration in the active layer 12 immediately below the gate electrode is reduced. In this case, since the etching rate of the silicon oxide film 16 by RIE is slower than the etching rate of the silicon nitride film 17 by RIE, about 60 to 80% of the silicon oxide film 16 is in a state of being etched.

Next, as shown in FIG. 3B, the silicon oxide film 16 in the gate electrode forming region is removed by wet etching with an HF solution.

Next, as shown in FIG. 3C, a recess structure is formed by etching the gate electrode formation region with a tartaric acid solution. This recess structure is for adjusting to a predetermined current value, and the recess depth may be about 10 nm at maximum. Since the conventional recess depth is 50 to 100 nm, the recess depth of this embodiment is significantly smaller than the conventional recess depth. For this reason, in the present embodiment, in-plane variations in the recess depth hardly pose a problem.

Next, as shown in FIG. 4A, a metal film 22 to be a gate electrode is vapor-deposited on the entire surface, and then lift-off is performed on the metal film 22 as shown in FIG. The electrode 23 is formed.

An important point in the first embodiment is that
The point is that the silicon oxide film 16 is slightly etched by overetching the silicon nitride film 17. Due to this over-etching, the carrier concentration in the active layer 12 which becomes the channel region via the silicon oxide film 16 immediately below the gate electrode 23 is reduced, and the breakdown voltage between the gate and the drain is improved. it is conceivable that.

FIG. 5 shows the field effect transistor according to the first embodiment (gate width: Wg = 36 mm, gate length: Lg).
= 1.0 μm), the silicon nitride film 1
7 shows the relationship between the overetching time for No. 7 and the current value Idss flowing between the source / drain and the current value Igd flowing between the gate / drain. The current value Idss between the source and drain is 0 when the gate potential is 0.
(V), the larger the power FE
The characteristics of T are good. The current value Igd between the gate and the drain is a current value that flows when 15 V is applied between the gate and the drain in the Schottky reverse direction, and the smaller the absolute value, the better the breakdown voltage between the gate and the drain. .

As is apparent from FIG. 5, the source-drain current Idss hardly changes and the gate-drain current Igd decreases during the overetching time of 0 to 80 seconds for the silicon nitride film 17. . However, if over-etching is performed for 90 seconds, the source-drain current Idss sharply decreases. Therefore, by setting the overetching time to 80 seconds or less, the gate-drain current Igd can be reduced to about 1/10 while maintaining the FET characteristics equivalent to those of the conventional FET. It is considered that this is because the carrier concentration of the active layer 12 immediately below the gate electrode was controlled by optimizing the overetching time.

FIG. 6 shows the measurement result of the high frequency characteristics of the power FET manufactured by the method for manufacturing the field effect transistor according to the first embodiment.

FIGS. 6A and 6B show 50 kHz, which is the most important element in a communication system using digital modulation.
Adjacent channel leakage power suppression ratio (A
It is a measurement result of dj). Here, Adj is 900 MH
It is the ratio of the peak of the signal at z to the noise level.
Further, in FIG. 6A, that is, Adj of −50 kHz is 90
This is a value of noise at a position apart from 0 MHz by 50 kHz, and is shown in FIG. 6B, that is, −100 kHz.
Adj is a value of noise at a position separated from 900 MHz by 100 kHz (see FIG. 7). The larger the absolute value of the ratio of the signal peak to the noise level, the better. The smaller the absolute value of the gate-drain current Igd, the better.

When the gate-drain current Igd is on the positive side of -6, the non-defective rate is judged as follows.
About 80% of the field effect transistors manufactured by the method of the first embodiment are good products in FIG. 6A, and about 90% are good products in FIG. 6B. 6B shows the noise at a point 100 kHz away from the peak of the signal, the non-defective rate is naturally higher than that in the case of FIG. 6A and is about 90%. As described above, according to the method of manufacturing the field-effect transistor of the first embodiment, the gate
The drain current Igd can be reduced. That is, even if the recess depth is reduced, the breakdown voltage between the gate and the drain can be improved, so that the recess depth can be prevented from varying and the yield can be significantly improved.

FIG. 8 shows the relationship between the gate-drain current Igd and the power added efficiency. The power addition efficiency is the ratio of the power input to the gate electrode of the field effect transistor and the output power. It can be seen from FIG. 7 that the power addition efficiency is improved as the absolute value of the gate-drain current Igd is reduced, and the field effect transistor obtained by the method of the first embodiment contributes to the extension of the talk time of the mobile phone. be able to.

In the MESFET using a compound semiconductor substrate such as a GaAs substrate, it is generally known that the stress applied to the gate electrode causes piezo electric charges to change the threshold voltage. According to the method, the carrier concentration can be lowered only in the portion directly below the gate electrode in the active layer, so that it is difficult for the piezoelectric charge itself to be generated and the fluctuation of the threshold voltage is small.

As can be seen from the description based on FIGS. 5, 6 and 8, the method of the first embodiment has a great influence on the stability of the characteristics of the MESFET and the improvement of the yield.

FIG. 9 shows variations in Vth (threshold voltage) due to the influence of stress applied to the gate electrode which changes with the progress of the manufacturing process of the field effect transistor. In FIG. 9, the solid line shows the case of the first embodiment, and the broken line shows the case of the conventional method. It can be seen that the method of the first embodiment can alleviate the fluctuation of Vth.

In the first embodiment, the lower layer portion of the silicon oxide film 16 left by over-etching the silicon nitride film 17 is removed by wet etching. Instead of this, low damage such as chemical dry etching is performed. May be removed by dry etching.

(Second Embodiment) The above-described first embodiment is a MESFET using an ion implantation method for forming an active layer.
However, according to the present invention, the same effect can be obtained for the MESFET using the crystal growth method for forming the active layer. Hereinafter, a MESFET using a crystal growth method will be described as a second embodiment with reference to FIGS.

First, as shown in FIG. 10A, MBE
A GaAs active layer 31 formed by doping Si as an impurity at a concentration of 1 × 10 ¹⁷ cm ⁻³ on a GaAs substrate 30 by a (Molecular beam epitaxy) method, and a concentration of Si as an impurity of 5 × 10 ¹⁸ cm ⁻³ . The GaAs high-concentration layers 32 doped with are crystal-grown. In this case, the thickness of the GaAs active layer 71 is 0.2 μm, and the thickness of the GaAs high concentration layer 72 is 50 nm.

Next, as shown in FIG. 10B, GaA
s The first resist mask 3 is formed in a predetermined region on the high concentration layer 32.
3 is formed, the GaAs active layer 31 and the GaAs high concentration layer 32 are mesa-etched using the first resist mask 33 as a mask to form an FET region 34 as shown in FIG. 10C. .

Next, as shown in FIG. 11A, GaA
After the silicon oxide film 35 and the silicon nitride film 36 are sequentially formed on the entire surface of the s substrate 30, a second resist mask 37 having source / drain formation regions opened is formed on the silicon nitride film 36.

Next, as shown in FIG. 11B, the silicon oxide film 35 and the silicon nitride film 36 are etched using the second resist mask 37 to form openings for forming the source / drain regions. After forming the part,
A source electrode 38 and a drain electrode 39 are formed by embedding an electrode metal in the opening.

Next, as shown in FIG. 11C, a third gate electrode forming region is opened on the silicon nitride film 36.
A resist mask 40 of is formed.

Next, as shown in FIG. 12A, the silicon nitride film 36 is etched using the third resist mask 40. In this case, as in the first embodiment, the silicon nitride film 36 is over-etched for about 60 seconds to remove the upper portion of the silicon oxide film 35 together with the silicon nitride film 36. in this case,
The effect of over-etching on the silicon nitride film 36 is that not only the GaAs high concentration layer 32 but also the GaAs active layer 3
It reaches to 1.

Next, as shown in FIG. 12B, after removing the lower layer portion of the silicon oxide film 36 by wet etching, recess etching is performed on the GaAs high concentration layer 32. Here, the reason why the GaAs high concentration layer 32 is removed is to adjust the threshold voltage of the field effect transistor to a predetermined value.

Next, as shown in FIG. 12C, a gate electrode 41 is formed on the GaAs active layer 31 by embedding an electrode metal in the opening of the gate electrode forming region, thus completing the field effect transistor. To do.

In the second embodiment, the epitaxial growth method is used to form the active layer, but the advantage of using the epitaxial growth method is that the thickness and concentration of the active layer can be easily controlled, so that the FET as designed is manufactured. It is easy to do.

In each of the above-mentioned embodiments, the active layer has a structure of n-type alone. Instead of this, (1) a p-type layer is buried under the n-type active layer, and a pn junction is used. The method of each of the above-described embodiments can be applied to a p-layer embedded structure in which the n-type active layer can be effectively thinned by utilizing the depletion layer thus formed, or (2) a structure using the p-type active layer. Needless to say.

(Third Embodiment) In the first and second embodiments, the number of insulating layers is two, but the technical idea of the present invention can be applied to the case where the number of insulating layers is one. . As a third embodiment, the case where the number of insulating layers is one is shown in FIGS.
Will be described with reference to.

First, as shown in FIG. 13A, GaA
After forming the first resist mask 51 on the one main surface of the s substrate 50, the GaA is formed using the first resist mask 51.
s Substrate 50 is irradiated with Si ions in a predetermined region at an acceleration voltage of 80 ke
Implanted with V to form an n-type active layer 52.

Next, as shown in FIG. 13B, GaA
After the second resist mask 53 is formed on one main surface of the s substrate 50, Si ions are implanted into a predetermined region of the active layer 52 at 150 keV by using the second resist mask 53 to form an n + type source. A region 54 and a drain region 55 are formed.

Next, as shown in FIG. 13C, GaA
The first insulating film 56 made of, for example, a silicon oxide film is deposited over the entire main surface of the s substrate 50, and then an annealing process is performed using the first insulating film 56 as a protective film. The activated Si is activated.

Next, as shown in FIG. 14A, after removing the first insulating film 56, a second insulating film made of, for example, a silicon nitride film is entirely formed on one main surface of the GaAs substrate 50. After depositing the film 57, a third resist mask 58 having source / drain electrode formation regions opened is formed on the second insulating film 57.

Next, as shown in FIG. 14B, an opening is formed by etching the second insulating film 57 using the third resist mask 58. After that, a source electrode 59 and a drain electrode 60 are formed by depositing an electrode forming metal in the opening.

Next, as shown in FIG. 14C, a fourth resist mask 61 having a gate electrode formation region opened is formed on the second insulating film 57.

Next, as shown in FIG. 15A, the second insulating film 57 is etched by reactive dry etching. In this case, the second gate electrode formation region
Etching is completed when the film thickness of the insulating film 57 is about 30 nm. This film thickness is such that the carrier concentration immediately below the gate electrode in the active layer 52 is reduced by the reactive dry etching. Thereby, the active layer 5
The part directly under the gate electrode in 2 is favorably affected, and the breakdown voltage between the gate and drain of the field effect transistor is improved. Therefore, it is preferable that the thickness of the second insulating film 57 left during the reactive dry etching is appropriately selected by an experiment.

Next, as shown in FIG. 15B, the second insulating film 57 left during the reactive dry etching is removed by wet etching. At this time, since the etchant for wet etching penetrates in the direction parallel to the one main surface of the GaAs substrate 50, side etching is simultaneously performed on the second insulating film 57. Therefore, the opening in the gate electrode formation region in the second insulating film 57 is not shown in FIG.
The shape is as shown in FIG.

Next, as shown in FIG. 15C, GaA
Recess etching is performed on the substrate 50 to form a recess structure.

Next, as shown in FIG. 16A, after a metal film 62 to be a gate electrode is vapor-deposited on the entire surface, FIG.
As shown in (b), when the gate electrode 63 is formed by performing lift-off on the metal film 62, a field effect transistor is obtained.

As described above, the characteristics similar to those of the first embodiment can be obtained also by the manufacturing method in which the insulating film is a single layer.

In the third embodiment, wet etching was used to remove the second insulating film 57 remaining during the reactive dry etching, but instead of this, dry etching with low damage such as chemical dry etching is used. It is also possible to use etching.

Further, in the third embodiment, the annealing process is performed using the first insulating film 56 as the protective film, but the annealing process may be performed without using the protective film.

Further, in the third embodiment, the silicon oxide film is used as the first insulating film 56 and the silicon nitride film is used as the second insulating film 57, but these can be appropriately changed.

(Fourth Embodiment) Next, in the fourth embodiment, the technical idea of the present invention will be described.
An example applied to the FET will be described. FIG. 17 (a)-
18C and 18A to 18D are cross-sectional views of the semiconductor device in the manufacturing process according to the fourth embodiment.

First, as shown in FIG. 17A, a WSi film 71a having a thickness of 6 nm is deposited on one main surface of the semi-insulating GaAs substrate 70 by the sputtering method. And WSi
On the film 71a, using a photolithography process,
The first opening where the active layer of the FET is to be formed
The resist mask 72 is formed, and using this, Si ions are implanted at an accelerating voltage of 30 keV to form an active layer 74a.

Next, as shown in FIG. 17B, a second resist mask 73 having an opening in a region where a gate is to be formed is formed on the semi-insulating GaAs substrate 70, and this resist mask 73 is formed. Is used to accelerate B ions to an acceleration voltage of 10 k, which is weaker than the acceleration voltage at the time of Si ion implantation.
Inject at eV. By this ion implantation, semi-insulating G
Disturbance occurs in the crystal structure of the aAs substrate 70, and the portion where the ions are implanted has a high resistance. That is, the high resistance layer 75 is formed near the center of the active layer 74a so as to be shallower than the active layer 74a.

Next, as shown in FIG. 17C, an Au film is deposited on the entire surface by vapor deposition with the second resist mask 73 left, and then lift-off is performed to form a metal film on the gate made of Au. To form 76.

Next, as shown in FIG. 18A, the WSi film 71a is subjected to reactive ion etching using CF4 gas with the on-gate metal film 76 as a mask, and the same as the on-gate metal film 71a. A gate electrode 71 having a planar shape is formed.

Next, using a photolithography process, the active layer 7 is formed on the semi-insulating substrate GaAs substrate 70.
After forming a third resist mask 78 having an opening above the portion 4a, Si ions are accelerated at an acceleration voltage of 100 keV.
To form a source region 80 and a drain region 81 which are n + type regions. At this time, since the acceleration voltage of Si ions is higher than the acceleration voltage of ion implantation when the active layer 74a is formed, the source region 80 and the drain region 81 are formed deeper than the active layer 74a. Then, a portion of the active layer 74a located below the gate electrode 71, that is, directly below the high resistance layer 75 remains as the channel region 74.

Next, as shown in FIG. 18C, the third resist mask 78 is removed and annealing is performed to activate the implanted Si.

Finally, as shown in FIG. 18D, Si
After depositing the N film 84, a part of the portion of the SiN film 84 above the source region 80 and the drain region 81 is opened by using a photolithography process. Then, AuGe.Ni.Au is vacuum-deposited in this opening, and sintering is performed at 450 ° C. for 3 minutes in an Ar gas atmosphere to directly form a source electrode 82 and a drain, which are ohmic electrodes, on the source region 80 and the drain region 81, respectively. The electrode 83 is formed. As a result, the MESFET is formed.

In the self-alignment MESFET having the structure shown in FIG. 18D, the carrier concentration in the semi-insulating GaAs substrate 70 below the gate electrode 71 has a characteristic distribution. The points will be considered below.

In FIG. 19, the thickness in this embodiment is 6n.
m shows the carrier profile when through-injection is performed through the WSi film (the state in which the high resistance layer is not formed) and the carrier profile when bare-injection (WSi = 0 nm) is performed. It was obtained as a result of analysis. In the figure, the horizontal axis represents the depth from the surface of the semi-insulating GaAs substrate, and the vertical axis represents the n-type carrier concentration. As can be seen by comparing the carrier profiles of the two, in the present embodiment, a steep carrier profile is obtained with a shallow depth of the region having a high impurity concentration. This means that the thickness of the channel region can be made extremely thin, which means that the K value inversely proportional to the thickness of the channel region increases and the transfer conductance gm also increases.

Therefore, in this embodiment, FIG.
In the step of forming the active layer 74a shown in (a), the WSi film 71a is formed.
Since through implantation of Si ions is performed via
A steep injection profile is obtained in the channel region 74, and a high-performance M having a high transfer conductance gm and a high K value.
ESFET can be realized.

On the other hand, according to the process shown in FIG.
Since the high resistance layer 75 is formed in the region immediately below the gate electrode 71, the high gate-drain breakdown voltage BVg
also has d.

That is, in the present embodiment, two effects, which are generally in a trade-off relationship, of an improvement in gm and K values and an improvement in gate-drain breakdown voltage can be realized at the same time. In addition, since the channel region 84 is separated from the gate electrode via the high resistance layer 75 which is a low carrier concentration layer, the generation of piezo electric charges is suppressed and the performance of the FET is improved.

In the MESFET having the LDD structure as shown in FIG. 32, the present embodiment is also obtained by performing the through implantation of the impurity ions and the formation of the high resistance layer just below the gate as in the present embodiment. The same effect can be obtained. In particular, in that case, there is an advantage that the MESFET having the LDD structure can be miniaturized and the withstand voltage characteristic can be improved. However, the structure is not limited to the asymmetric structure shown in FIG.

Further, when performing the through implantation, it is not always necessary to use the WSi film 71a as in the present embodiment, and it has a function of reducing the implantation energy of the impurity ions by a certain ratio by using another metal film, an insulating film or the like. The same effect can be obtained by using a film.

In this embodiment, the active layer 74a of the MESFET is formed by implanting impurity ions. However, even if the active layer 74a is formed by introducing impurities during epitaxial crystal growth, the high resistance layer 75 is not formed thereafter. The effect obtained by forming is not reduced.

In the present embodiment, the n-channel type MESFET in which the source / drain region and the channel region are all formed by the n-type region has been described. However, the MESFET or the p-channel type MESFET having the active layer having the p-layer embedded structure is described. Also in this case, it is needless to say that the same effect as that of the present embodiment can be obtained by the through implantation of the impurity ions and the formation of the high resistance layer.

(Fifth Embodiment) Next, a fifth embodiment which is an example in which the technical idea of the present invention is applied to a pn junction gate FET (hereinafter referred to as JFET) will be described. Figure 2
0 (a) to (c) and FIGS. 21 (a) to (d) are cross-sectional views of the semiconductor device in the manufacturing process according to the fifth embodiment.

First, in the steps shown in FIGS. 20A to 20C, FIGS.
Almost the same process as the step shown in (c) is performed. However,
In the present embodiment, in the step shown in FIG. 20B, the resist mask 73 is used and the M is formed through the WSi film 71a.
Through implantation of g ions is performed to form a p-type region 90 shallower than the active layer 74a near the center of the active layer 74a.

Then, in the steps shown in FIGS. 21A to 21D, FIGS. 18A to 18D in the fourth embodiment are used.
The same process as the process shown in is performed. However, in FIG.
In the step shown in (c), after removing the resist mask 78, annealing is performed to activate the implanted Si / Mg.

Through the above steps, in the present embodiment, finally, as shown in FIG.
On the substrate 70, a gate electrode 71, a source region 80 and a drain region 81 which are n + -type regions, respectively, a channel region 74 which is a low-concentration n-type region, and immediately above the channel region 74 and directly below the gate electrode 71. A JFET having a p-type region 90 is formed.

JFET having the structure shown in FIG.
In the same manner as in the fourth embodiment, the effect of improving the JFET performance by the through implantation of the impurity ions is obtained, and the gate electrode 71 is formed in self-alignment with the p-type region 90 immediately below. A JFET with high uniformity is easily realized. In particular, the gate electrode 7
Since the electric charge of the conductivity type opposite to that of the carrier in the channel region 74 exists immediately below 1, the generation of the piezoelectric charge can be effectively prevented.

Instead of the channel region 233 of the MESFET having the LDD structure as shown in FIG. 32, the channel region 74 formed by the through implantation of the impurity ions as in the present embodiment and the p-type region immediately below the gate electrode 71. By forming 90 and 90, the same effect as this embodiment can be obtained. In particular, in that case, there is an advantage that the JFET having the LDD structure can be miniaturized and the withstand voltage characteristic can be improved. However, the structure is not limited to the asymmetric structure shown in FIG.

Further, when performing the through implantation, it is not always necessary to use the WSi film 71a as in the present embodiment, and it has a function of reducing the implantation energy of the impurity ions by a certain ratio with another metal film, an insulating film or the like. The same effect can be obtained by using a film.

Further, in the present embodiment, the active layer 74a of the JFET is formed by implanting impurity ions, but the active layer 7a is formed by introducing impurities during epitaxial crystal growth.
Even if 4a is formed, the effect obtained by forming the p-type region 90 thereafter is not reduced.

In the present embodiment, the n-channel JFET in which the source / drain region and the channel region are all formed of the n-type region has been described. However, a JFET having an active layer having a p-layer embedded structure or a p-channel JFE is used.
Regarding T, needless to say, the same effect as that of the present embodiment can be obtained by through implantation of impurity ions and formation of a high resistance layer.

(Sixth Embodiment) Next, a sixth embodiment, which is an example in which the technical idea of the present invention is applied to a pin junction gate FET (hereinafter referred to as pinFET), will be described. 22A to 22C, 23A to 23C, and 24A and 24B are cross-sectional views of the semiconductor device in the manufacturing process according to the present embodiment.

First, in the steps shown in FIGS. 22 (a) and 22 (b), almost the same processes as the steps shown in FIGS. 17 (a) and 17 (b) in the fourth embodiment are performed. However, in FIG.
In the step shown in (b), B is formed using the resist mask 73.
Ions are implanted at an accelerating voltage of 15 keV to form a high resistance layer 75 deeper and wider than in the fourth embodiment.

Next, as shown in FIG.
A third resist mask 78 having an opening narrower than the opening of the second resist mask 73 used in (b) is formed, and Mg ions are accelerated at an accelerating voltage of 10 keV using this third resist mask 78. And p is injected into the high resistance layer 75.
A mold region 90 is formed. That is, the high resistance layer 75 shallower than the active layer 74 a is formed near the center of the active layer 74 a, and the p-type region 90 shallower than the high resistance layer 75 is formed near the center of the high resistance layer 75.

Next, in the steps shown in FIGS. 23 (a) to 23 (c), almost the same processes as the steps shown in FIGS. 17 (c), 18 (a), and 18 (b) of the fourth embodiment, respectively. Is performed to form a gate electrode 71 made of WSi and an on-gate metal film 76 made of Au just above the p-type region 90, and at the same time, on both sides of the high resistance layer 75, a source region 80 and a drain which are n + -type regions. A region 81 is formed (FIG. 23)
(See (c)). However, in the present embodiment, FIG.
Fourth resist mask 9 used in the step shown in FIG.
1 also covers the portions corresponding to the upper side of the high resistance layer 75 on both sides of the gate electrode 71 and the metal film on the gate 76.

Next, in the steps shown in FIGS. 24A and 24B, the steps shown in FIGS.
The same processing as the step shown in (d) is performed. That is, the Si / Mg implanted in the semi-insulating GaAs substrate 70 is activated to form the source / drain electrodes 82 and 83 on the source region 80 and the drain region 81, respectively. As described above, the pinFET is formed.

In the pinFET shown in FIG. 24C, the effect of improving the performance of the pinFET by the through implantation of impurity ions is obtained as in the fourth and fifth embodiments, and the width of the i layer (high resistance layer 75) is obtained. Since the depth and the depth can be arbitrarily changed, an FET having a high degree of freedom in design can be easily realized.

Incidentally, instead of the channel region 233 of the MESFET having the LDD structure as shown in FIG. 32, the channel region 74 by the through implantation of impurity ions as in this embodiment, the high resistance layer 75, and the gate electrode. 7
The same effect as that of the present embodiment can be obtained by forming the p-type region 90 immediately below. In particular, in that case, there is an advantage that the pinFET having the LDD structure can be miniaturized and the withstand voltage characteristic can be improved. However,
It is not limited to the asymmetric structure as shown in 2.

Further, when performing the through implantation, it is not always necessary to use the WSi film 71a as in the present embodiment, and it has a function of reducing the implantation energy of the impurity ions by a certain ratio by using another metal film, an insulating film or the like. The same effect can be obtained by using a film.

Further, in the present embodiment, the active layer 74a of the pinFET is formed by implanting impurity ions.
Even if active layer 74a is formed by introducing impurities during epitaxial crystal growth, the effect obtained by forming p type region 90 thereafter is not reduced.

In the present embodiment, the n-channel pinFET in which the source / drain region and the channel region are all formed of the n-type region has been described. However, the pinFET or the p-channel pinFET having the active layer having the p-layer embedded structure is described. Also in this case, it is needless to say that the same effect as in the present embodiment can be obtained by through implantation of impurity ions and formation of a high resistance layer.

In the present embodiment, in the step shown in FIG. 23C, the active layer 7 of the semi-insulating GaAs substrate 70 is used.
The resist mask is used to cover not only the regions other than 4a but also the portions corresponding to the upper side of the high resistance layer 75 on both sides of the gate electrode 71 and the metal film on the gate 76.
Side walls may be formed by depositing a silicon nitride film or the like on both sides of 1 and the on-gate metal film 76 and then performing anisotropic etching. Even in that case, the width of the high resistance layer 75 can be adjusted to some extent by changing the thickness of the deposited silicon nitride film, and the inner end portions of the source region 80 and the drain region 81 are gated. The electrode 71 can be defined in a self-aligned manner.

In place of the second resist mask 73 used in the step shown in FIG. 22B, the first resist mask 72 used in FIG. 22A is used as it is, and the active layer 74a is initially used. The high resistance layer 75 may be entirely formed immediately above, and the high resistance layer 75 may be narrowed by implanting impurity ions for forming the source region 80 and the drain region 81 in the step shown in FIG. .

Further, although illustration of the embodiment is omitted, by forming an n-type region in place of the p-type region 90 in the sixth embodiment, a high drain is provided between the n-type region and the side drain. While maintaining a high breakdown voltage with the presence of the resistance layer, n
An FET having a high driving force can be easily formed by appropriately adjusting the distance between the mold region and the channel region below.

(Seventh Embodiment) Next, in a seventh embodiment,
An example in which the technical idea of the present invention is applied to a MESFET having a damage layer wider than the gate length will be described. 25A to 25E are cross-sectional views of the semiconductor device in the manufacturing process according to the seventh embodiment.

First, as shown in FIG. 25A, an active layer 102, a source region 104, a drain region 105, a silicon oxide film 106, and a silicon nitride film are formed on a part of a semi-insulating GaAs substrate 100. 107 and the source electrode 10
9 and the drain electrode 110 are formed. The steps up to this state can be easily understood from each of the above-described embodiments, and therefore illustration and description thereof will be omitted.

Next, as shown in FIG. 25B, a first resist mask 108 having an opening only above a part (a part excluding both ends) of the active layer 102 is formed by a photolithography technique. . The opening includes a gate formation region.

Next, as shown in FIG. 25C, RIE
The silicon nitride film 107 and the silicon oxide film 106 are
Dry etching is performed. At this time, the thickness of the silicon oxide film 106 initially formed in this embodiment is about 50 nm, and the thickness of the silicon oxide film 106 after dry etching is several angstroms to 20 nm.
It is about nm. Then, by this dry etching, similarly to the first embodiment, the first resist mask 1 is formed.
A damage layer Rdm is formed near the surface of the active layer 102 below the opening of 08.

Next, as shown in FIG. 25D, after removing the first resist mask 108, a second resist mask 111 having a gate electrode formation region opened is formed. In this state, the silicon oxide film 106 in the gate electrode formation region is removed by wet etching with an HF solution. Then, the GaAs substrate 100 in the gate electrode formation region is etched with a tartaric acid solution to form a recess structure. At this time, a portion of the active layer 102 near the surface of the damaged layer Rdm is removed, but the damaged layer Rdm remains in the surface region of the active layer 102.

Next, as shown in FIG. 25E, after depositing a metal film to be a gate electrode, lift-off is performed on the metal film to form a gate electrode 113.

The point of this embodiment is that, in the state shown in FIG. 25E, the damage layer Rdm (low level) is formed not only directly under the gate electrode 113 but also in a surface region wider than the gate electrode 113 in the surface region of the active layer 102. That is, a carrier concentration layer) is formed. In the MESFET formed according to this embodiment, the damage layer Rdm has the gate electrode 1
13 is formed in the surface region between the drain region and the drain region 13 in particular, so that a higher gate-drain breakdown voltage (BVg
d) can be exhibited.

(Eighth Embodiment) Next, in the eighth embodiment,
An example in which the technical idea of the present invention is applied to an offset type MESFET will be described. 26 (a) to 26 (e)
FIG. 16A is a sectional view of a semiconductor device in a manufacturing process according to an eighth embodiment.

First, in the steps shown in FIGS. 26A to 26C, the same processing as the steps shown in FIGS. 25A to 25C in the seventh embodiment is performed.

Also in this embodiment, the initially formed silicon oxide film 106 has a thickness of about 50 nm.
The thickness of the silicon oxide film 106 after dry etching shown in FIG. 6C is about several angstroms to 20 nm. The damage layer Rd is formed near the surface of the active layer 102 below the opening of the first resist mask 108.
m is formed.

Next, as shown in FIG. 26D, after removing the first resist mask 108, a second resist mask 111 having an opening in the gate electrode formation region is formed. At this time, the opening of the second resist mask 111 is biased toward the source region 104 side to the extent that it extends over the active layer 102 far from the drain region 105 and over the silicon nitride film 107 over the source region 104. Is formed in. In this state, the silicon oxide film 10 in the gate electrode formation region is wet-etched with an HF solution.
Remove 6. Then, the GaAs substrate 100 in the gate electrode formation region is etched with a tartaric acid solution to form a recess structure. At this time, the damage layer R of the active layer 102
Although part of dm is removed, a damaged layer Rdm having a low carrier concentration remains near the surface of the active layer 102.

Next, as shown in FIG. 26E, after depositing a metal film to be a gate electrode, lift-off is performed on the metal film to form a gate electrode 113.
As a result, the gate electrode 113 is formed on the source region 104 side in a self-aligned manner at the end of the opening of the silicon nitride film 107. In other words, the gate electrode 113 is formed on the damage layer Rdm near the source side end portion.

The point of this embodiment is that the damage layer Rdm (low carrier concentration layer) is formed in the active layer 102 immediately below the gate electrode 113 in the state shown in FIG. Are the first and second insulating films 10
6, 107 has an offset type structure formed at the open ends in a self-aligning manner. The MESFET formed according to this embodiment has the same advantages as the above-described seventh embodiment due to the formation of the damage layer Rdm, and due to such an offset type gate structure, the source resistance is remarkably low and the remarkably high. The gate-drain breakdown voltage (BVgd) can be exhibited.

(Ninth Embodiment) Next, in a ninth embodiment,
An example in which the technical idea of the present invention is applied to a MESFET having two types of low carrier concentration layers will be described. FIG. 27
27A to 27E are cross-sectional views of the semiconductor device in the manufacturing process according to the ninth embodiment.

First, in the steps shown in FIGS. 27 (a) and 27 (b), the same processing as the steps shown in FIGS. 25 (a) to 25 (c) in the seventh embodiment is performed (FIG. 25 ( b)
The state shown in is omitted from the drawing).

In the present embodiment, in the state shown in FIG. 27B, the first damage layer Rdm1 is formed near the surface of the active layer 102 below the opening of the first resist mask 108.
Are formed.

Next, as shown in FIG. 27C, after removing the first resist mask 108, a second resist mask 111 having an opening in the gate electrode formation region is formed. In this state, the silicon oxide film 106 in the gate electrode formation region is removed by wet etching with an HF solution. Then, the GaAs substrate 100 in the gate electrode formation region is etched with a tartaric acid solution to form a recess structure. At this time, a portion of the first damage layer Rdm1 near the surface is removed, but the first damage layer Rdm1 remains in the surface region of the active layer 102.

Next, as shown in FIG. 27D, after depositing a metal film to be the gate electrode, lift-off is performed on the metal film to form the gate electrode 113.

Next, as shown in FIG. 27 (e), RIE
Thus, dry etching is performed on the exposed portion of the silicon oxide film 106. However, silicon oxide film 1
Dry etching is performed to the extent that only the upper layer portion is removed instead of removing all 06. At this time, FIG.
First damage layer Rdm1 formed in the step shown in (b)
The carrier concentration in a portion of the portion other than the region directly below the gate electrode 113 is further reduced, and the second damage layer Rdm2 having an extremely low carrier concentration is formed.

The point of this embodiment is that the first damage layer Rdm1 (first low carrier concentration layer) is formed in the active layer 102 immediately below the gate electrode 113 in the state shown in FIG. 27 (e). That is, the second damage layer Rdm2 (second low carrier concentration layer) is formed in the active layer 102 on both sides of the gate electrode 113. The MESFET formed according to this embodiment has the advantages of the first and seventh embodiments described above by forming the first damage layer Rdm, and is activated by the second damage layer Rdm2 having an extremely low carrier concentration. Since the electric field of the layer 102 is relaxed, the gate-drain breakdown voltage (BVgd) of the MESFET is dramatically improved.

(Tenth Embodiment) Next, in a tenth embodiment, an example in which the technical idea of the present invention is applied to a second offset type MESFET having two types of low carrier concentration layers will be described. 28A to 28E show the first
It is sectional drawing of the semiconductor device in the manufacturing process which concerns on 0 embodiment.

First, in the steps shown in FIGS. 28A and 28B, the same processing as the steps shown in FIGS. 26A to 26C in the eighth embodiment is performed (see FIG. b)
The state shown in is omitted from the drawing).

In this embodiment, the thickness of the silicon oxide film 106 after dry etching shown in FIG. 28B is about several angstroms to 20 nm. Then, a first damage layer Rdm1 is formed near the surface of the active layer 102 below the opening of the first resist mask 108.

Next, as shown in FIG. 28C, after removing the first resist mask 108, a second resist mask 111 having a gate electrode formation region opened is formed. At this time, the opening of the second resist mask 111 is biased toward the source region 104 side to the extent that it extends over the active layer 102 far from the drain region 105 and over the silicon nitride film 107 over the source region 104. Is formed in. In this state, the silicon oxide film 10 in the gate electrode formation region is wet-etched with an HF solution.
Remove 6. Then, the GaAs substrate 100 in the gate electrode formation region is etched with a tartaric acid solution to form a recess structure. At this time, part of the first damage layer Rdm1 of the active layer 102 is removed, but the first damage layer Rdm1 remains in the surface region of the active layer 102.

Next, as shown in FIG. 28D, after depositing a metal film to be a gate electrode, lift-off is performed on the metal film to form a gate electrode 113.
As a result, the gate electrode 113 is formed on the source region 104 side in a self-aligned manner at the end of the opening of the silicon nitride film 107. In other words, the gate electrode 113 is formed on the source side end region of the first damage layer Rdm1.

Next, as shown in FIG. 28E, RIE is performed.
Thus, dry etching is performed on the exposed portion of the silicon oxide film 106. However, silicon oxide film 1
Dry etching is performed to the extent that only the upper layer portion is removed instead of removing all 06. At this time, FIG.
First damage layer Rdm1 formed in the step shown in (b)
The carrier concentration in a portion of the portion other than the region directly below the gate electrode 113 is further reduced, and the second damage layer Rdm2 having an extremely low carrier concentration is formed.

The point of this embodiment is that the active layer 102 wider than the gate electrode 113 is in the state shown in FIG.
The first damage layer Rdm1 (first low carrier concentration layer) is formed in the surface region of the gate electrode 113, and the opening of the first and second insulating films is formed on the gate electrode 113 on the source side end portion of the active layer 102. It has an offset type structure formed in self-alignment with the edge, and that the second damage layer Rdm2 (second low carrier concentration layer) is formed on the active layer 102 on one side of the gate electrode 113. It is that you are. The MESFET formed according to the present embodiment has the advantages of the first and seventh embodiments as described above due to the formation of the damage layer Rdm, and the active layer 102 is formed by the second damage layer Rdm2 having an extremely low carrier concentration. , The gate-drain breakdown voltage (BVgd) of the MESFET is dramatically improved.

In the first to tenth embodiments, the depth of the low carrier concentration layer is preferably about 20 to 50 nm, and the thickness of the channel portion of the active layer excluding the low carrier concentration layer is preferably about 80 to 150 nm. The carrier concentration in the active layer is preferably about 1 to 3 × 10 ¹⁷ cm ⁻³ . The carrier concentration in the low carrier concentration layer is preferably 10 ¹⁶ cm ⁻³ or less, and further 5 × 10 ¹⁴ cm 3.
It is more preferably in the range of ^{−3 to} 5 × 10 ¹⁵ cm ⁻³ .

[0137]

According to the first method of manufacturing a semiconductor device of the present invention, through implantation of impurity ions is performed through the metal film for forming electrodes to make the impurity profile in the active layer below the electrodes steep. However, a part of the active layer is made a high resistance layer, and below the electrode, the active layer, a high resistance layer on the active layer, and an impurity diffusion layer of a conductivity type opposite to that of the active layer are further formed. Since the pin junction was formed, this p
It is possible to form a device such as a pin-junction gate FET having a high performance and a high degree of freedom in design using the in-junction.

According to the second method of manufacturing a semiconductor device of the present invention, through implantation of impurity ions is performed through the metal film for forming electrodes to make the impurity profile in the active layer below the electrodes steep, Since a part of the active layer is made a high resistance layer, an active layer, a high resistance layer on the active layer, and an impurity diffusion layer of the same conductivity type as the active layer on the active layer are formed below the electrode. Depth of high resistance layer and impurity diffusion layer,
By adjusting the width, it is possible to form a device such as an FET having a large driving force and a high degree of freedom in design.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a change in a semiconductor structure in each step of depositing a first insulating film in the manufacturing steps of the first embodiment.

FIG. 2 is a cross-sectional view showing a change in a semiconductor structure in a process of forming a resist mask for forming a gate in the manufacturing process of the first embodiment.

FIG. 3 is a cross-sectional view showing a change in the semiconductor structure in a process up to the end of recess etching in the manufacturing process of the first embodiment.

FIG. 4 is a cross-sectional view showing a change in a semiconductor structure in a process up to forming a gate electrode in the manufacturing process of the first embodiment.

FIG. 5 is a characteristic diagram showing a relationship between an over-etching time for a silicon nitride film and a current value Idss flowing between a source / drain and a current value Igd flowing between a gate / drain in the method for manufacturing an FET according to the first embodiment. Is.

6A and 6B show measurement results of high-frequency characteristics of a power FET manufactured by the method of manufacturing the FET according to the first embodiment, where FIG. 6A shows a current value Igd flowing between the gate and the drain.
And the adjacent channel leakage power suppression ratio at the time of detuning 50 kHz, and (b) is the relationship between the current value Igd flowing between the gate and the drain and the adjacent channel leakage power suppression ratio at the time of detuning 100 kHz.

FIG. 7 shows the case of detuning at 50 kHz and 100 kHz shown in FIG.
It is a figure explaining the time of z detuning.

FIG. 8 is a characteristic diagram showing a relationship between a current value Igd flowing between the gate and the drain and power added efficiency in the power FET manufactured by the method for manufacturing the FET according to the first embodiment.

FIG. 9 is a graph showing V due to the influence of the stress applied to the gate electrode which changes with the progress of the manufacturing process of the FET according to the first embodiment.
It is a figure which shows the fluctuation | variation of th (threshold voltage).

FIG. 10 is a cross-sectional view showing a change in the semiconductor structure in the process up to patterning the first and second insulating films in the manufacturing process of the second embodiment.

FIG. 11 is a cross-sectional view showing a change in the semiconductor structure in a process up to forming a gate formation resist mask in the manufacturing process of the second embodiment.

FIG. 12 is a cross-sectional view showing a change in the semiconductor structure in a process up to forming a gate electrode in the manufacturing process of the second embodiment.

FIG. 13 is a cross-sectional view showing a change in the semiconductor structure in the steps up to depositing the first insulating film in the manufacturing steps of the third embodiment.

FIG. 14 is a cross-sectional view showing a change in semiconductor structure in a process up to forming a gate electrode in the manufacturing process of the third embodiment.

FIG. 15 is a cross-sectional view showing a change in the semiconductor structure in a process up to recess etching in the manufacturing process of the third embodiment.

FIG. 16 is a cross-sectional view showing a change in semiconductor structure in a process up to forming a gate electrode in the manufacturing process of the third embodiment.

FIG. 17 is a cross-sectional view showing a change in the semiconductor structure in the steps up to forming the metal film on the gate in the manufacturing steps of the fourth embodiment.

FIG. 18 shows a source electrode in the manufacturing process of the fourth embodiment,
It is sectional drawing which shows the change of a semiconductor structure in the process until a drain electrode etc. are formed.

FIG. 19 is SIMS analysis data comparing a carrier profile by through implantation of impurity ions through the film of the present invention and a carrier profile by conventional bare implantation.

FIG. 20 is a cross-sectional view showing a change in the semiconductor structure in the steps up to forming the metal film over the gate in the manufacturing steps of the fifth embodiment.

FIG. 21 shows a source electrode in the manufacturing process of the fifth embodiment,
It is sectional drawing which shows the change of a semiconductor structure in the process until a drain electrode etc. are formed.

FIG. 22 is a cross-sectional view showing a change in the semiconductor structure in the process up to forming the p-type region in the manufacturing process of the sixth embodiment.

FIG. 23 is a cross-sectional view showing a change in the semiconductor structure in the process up to forming the source / drain regions in the manufacturing process of the sixth embodiment.

FIG. 24 is a cross-sectional view showing a change in the semiconductor structure in the steps up to forming the source electrode and the drain electrode in the manufacturing process of the sixth embodiment.

FIG. 25 is a cross-sectional view showing a change in the semiconductor structure in the manufacturing process of the seventh embodiment.

FIG. 26 is a cross-sectional view showing a change in the semiconductor structure in the manufacturing process of the eighth embodiment.

FIG. 27 is a sectional view showing a structural change in the manufacturing process of the ninth embodiment.

FIG. 28 is a sectional view showing a structural change in the manufacturing process of the tenth embodiment.

FIG. 29 is a cross-sectional view showing a change in the semiconductor structure in the steps of depositing the first and second insulating films in the manufacturing steps of the first conventional FET manufacturing method.

FIG. 30 is a cross-sectional view showing a change in the semiconductor structure in the steps of forming the wiring in the manufacturing steps of the first conventional FET manufacturing method.

FIG. 31 is a cross-sectional view of an FET obtained by a second conventional method of manufacturing an FET.

FIG. 32 is a cross-sectional view of a conventional FET having an LDD structure.

[Explanation of symbols]

10 GaAs substrate (compound semiconductor substrate) 12 Active layer 14 Source area 15 drain region 16 Silicon oxide film (first insulating layer) 17 Silicon nitride film (second insulating layer) 19 Source electrode 20 drain electrode 22 Fourth resist mask (resist mask) 23 Gate electrode 30 GaAs substrate (compound semiconductor substrate) 31 GaAs active layer 32 GaAs high concentration layer 34 FET area 35 Silicon oxide film (first insulating layer) 36 Silicon nitride film (second insulating layer) 38 Source electrode 39 drain electrode 40 Third resist mask (resist mask) 41 Gate electrode 50 GaAs substrate (compound semiconductor substrate) 52 Active layer 54 Source Area 55 Drain region 57 Second insulating film (insulating film) 59 Source electrode 60 drain electrode 61 Fourth resist mask (resist mask) 63 Gate electrode 70 GaAs substrate (compound semiconductor substrate) 71a WSi film 71 Gate electrode 72 First resist mask 73 Second resist mask 74a Active layer 74 channel area 75 High resistance layer (Low carrier concentration layer) 76 Metal film on gate 78 Third resist mask 80 Source Area 81 drain region 82 Source electrode 83 Drain electrode 84 SiN film 90 p-type region (low carrier concentration layer) 91 Fourth resist mask

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyuki Shodo 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Toshinobu Matsuno 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial (56) References JP-A 1-251665 (JP, A) JP-A 63-62274 (JP, A) JP-A 60-34073 (JP, A) JP-A 61-112383 (JP, A) JP-A-4-132232 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 21/265 H01L 29/812

Claims (2)

(57) [Claims] 1. A method of manufacturing a semiconductor device mounted on a compound semiconductor substrate, the method comprising depositing a metal film for forming an electrode on the compound semiconductor substrate, and impurities in the compound semiconductor substrate via the metal film. Forming an active layer of a first conductivity type at a predetermined depth from the surface of the compound semiconductor substrate by implanting ions, and the gate electrode in a surface region of the active layer via the metal film. Forming a high resistance layer in at least a part of the surface region of the active layer by implanting impurity ions into a region including a region located immediately below and on both sides of the gate electrode of the high resistance layer. The impurity ions are implanted into a portion immediately below the second resistance layer, and the second impurity layer is shallower than the high resistance layer.
A method of manufacturing a semiconductor device, comprising: a step of forming a conductive type impurity diffusion layer; and a step of patterning the metal film to form an electrode of the semiconductor device on the impurity diffusion layer. 2. A method of manufacturing a semiconductor device mounted on a compound semiconductor substrate, the step of depositing a metal film for forming an electrode on the compound semiconductor substrate, and impurities in the compound semiconductor substrate via the metal film. Forming an active layer of a first conductivity type at a predetermined depth from the surface of the compound semiconductor substrate by implanting ions, and the gate electrode in a surface region of the active layer via the metal film. Forming a high resistance layer in at least a part of the surface region of the active layer by implanting impurity ions into a region including a region located immediately below and on both sides of the gate electrode of the high resistance layer. Impurity ions are implanted into a portion immediately below the first resistance layer to make the first shallower than the high resistance layer.
A method of manufacturing a semiconductor device, comprising: a step of forming a conductive type impurity diffusion layer; and a step of patterning the metal film to form an electrode of the semiconductor device on the impurity diffusion layer.