JP3369875B2 - LCD drive circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive circuit for driving a liquid crystal display element.

[0002]

2. Description of the Related Art Generally, a liquid crystal display device is one in which a liquid crystal composition is sandwiched between two substrates each having an electrode formed thereon.
The orientation of the liquid crystal composition is changed by applying a voltage between the electrodes to display an image on the display screen.

A general structure of this liquid crystal display device is shown in FIG. While a plurality of gate lines 62 ₁ to a substrate of the above two substrates, ..., 62 ₃ are arranged in parallel, and the gate lines 62 _1, ..., 62 data lines so as to be substantially perpendicular to ₃ (signal 61 ₁ , ..., 61 ₃ are arranged. Then, at each intersection of the gate line and the signal line, TF
A T (Thin Film Transistor) 63 is formed, and the gate of the TFT 63 is connected to the gate line, one of the source and the drain is connected to the signal line, and the other is connected to the pixel electrode 65. A common electrode 66 is formed on the other of the two substrates.
Then, the surface of the one substrate on which the pixel electrode 65 is formed,
It is arranged so as to face the surface of the other substrate on which the common electrode 66 is formed, and the liquid crystal composition is sandwiched therebetween.

Such a liquid crystal display device is driven by applying an alternating voltage to the pixel electrode 65 as shown in FIG. 5 in order to prevent polarization and thus deterioration of the liquid crystal composition. That is, applying a voltage to the negative relative voltage V _com is after applying the voltage as a positive relative to the voltage V _com to a constant voltage V _com to the application, the pixel electrode 65 to the common electrode 66 Common symmetry drive is performed.

As a result, as shown in FIGS. 6A and 6B, the pixel electrode 65 to which a positive voltage is applied in one frame of the display screen is applied to the pixel electrode 65 in the next frame. Become. 6A and 6B show the case of the dot inversion display. Regarding the voltage of the common electrode 66, the pixel electrode corresponding to any one pixel and the pixel adjacent to this pixel is related to the voltage of the common electrode 66. Voltages of opposite polarity are applied. For example, as shown in FIG. 6A, the pixel electrodes corresponding to each pixel in the even-numbered pixel columns have +, −, +,
Voltages of − and + polarities are applied, and voltages of −, +, −, + and − polarities are applied to the pixel electrodes corresponding to the pixels of the odd-numbered pixel columns adjacent to the even-numbered pixel column. Will be done.

The structure of a conventional liquid crystal drive circuit for driving such a liquid crystal display element will be described with reference to FIG.

In the conventional liquid crystal drive circuit, as shown in FIG. 3, the data bus 22 includes a data bus 22 ₁ for transmitting n-bit image data to odd-numbered data lines of the liquid crystal display element and an even-numbered data bus 22 _1. And a data bus 22 ₂ for sending n-bit image data to the data line. In this conventional liquid crystal drive circuit, assuming that the number of data lines of the liquid crystal display element driven by the liquid crystal drive circuit is 2 m, 2m sampling registers 2 are provided.
4 ₁ , ..., 24 _2m and 2m load registers 26 ₁ ,
..., 26 _2m , D / A converter 27, and output circuit 29
It has and. The D / A converter has 2m L decoders 27a ₁ , ..., 27a _2m and 2m H decoders 27
b _1, ..., it has a 27b _2m, and the gradation potential setting section 27c. Further, the output circuit 29 is composed of 4m operational amplifiers 29a.
_{1, ..., 29a 2m, 29b} 1, ..., has a 29b _2m. In addition, in FIG. 3, 2i-1th (odd number)
And only the part connected to the 2i-th (even-numbered) data line is shown.

The sampling register 24 _2i-1 provided corresponding to the 2i-1 (i = 1, ..., M) th (odd number) data line receives a command from a data control unit (not shown). N of the pixel corresponding to the 2i−1th data line
Bit image data is fetched from the data bus 22 ₁ .
The sampling register 24 provided corresponding to the 2i (i = 1, ..., M) th (even number) data line.
_{The 2i} takes in n-bit image data of the pixel corresponding to the 2i-th data line from the data bus 22 ₂ based on the instruction from the data control unit.

Load register 26 _i (i = 1, ..., 2)
m) latches the image data held in the sampling register 24 _i in response to the LOAD signal supplied from the outside. Load register 26 _i (i = 1, ..., 2 m)
The image data latched at is supplied to the L decoder 27a _i and the H decoder 27b _i in the D / A converter 27.

The gradation potential setting section 27c divides the reference voltage by, for example, resistance division or capacitance division, so that 2 ⁿ (on the negative side and 2 ⁿ (on the positive side) with respect to the potential V _com applied to the common electrode of the liquid crystal display element. n is the number of bits of image data) and sets the gradation level potential.

L decoder 27a _i (i = 1, ..., 2m)
Is the potential V set by the gradation potential setting unit 27c.
Of the 2 ⁿ gradation levels on the minus side of _com , one gradation level corresponding to the n-bit image data latched in the load register 26 _i is selected, and the operational amplifier 29 is selected.
Output to a _i . Further, the H decoder 27b _i (i = 1,
, 2m) corresponds to the n-bit image data latched in the load register 26 _i among the 2 ⁿ gradation levels on the plus side with respect to the potential V _com set by the gradation potential setting unit 27c. One gradation level is selected and output to the operational amplifier 29b _i .

Operational amplifier 29a _2i-1 (i = 1, ..., m)
Supplies the output of the L decoder 27a _2i-1 to the 2i-1th data line of the liquid crystal display element via the output terminal OUT _2i-1 of the liquid crystal drive circuit based on the polarity inversion signal POL supplied from the outside. To do.

Further, the operational amplifier 29b _2i-1 (i = 1, ...,
m) indicates the output of the H decoder 27b _2i-1 based on the inversion signal POL of the polarity inversion signal POL, _2i-1 of the liquid crystal display element via the output terminal OUT _2i-1 of the liquid crystal drive circuit.
Supply to the second data line.

Similarly, the operational amplifier 29a _2i (i = 1, ...,
m) supplies the output of the L decoder 27a _2i based on the inverted signal POL of the polarity inverted signal POL to the 2i-th data line of the liquid crystal display element via the terminal OUT _2i of the output circuit 29.

Further, the operational amplifier 29b _2i (i = 1, ...,
m) is an H decoder 27 based on the polarity inversion signal POL.
The output of b _2i is supplied to the 2i-th data line of the liquid crystal display element via the terminal OUT _2i of the output circuit 29.

With such a structure, the alternating voltage as shown in FIG. 5 which varies according to the polarity inversion signal POL is supplied to the data line of the liquid crystal display element.

[0017]

In such a conventional liquid crystal drive circuit, the selection of the gradation level in the L decoder and the H decoder is performed by the transistor.

As a result, when the number of gradations is increased to improve the image quality, the number of bits n of the incoming image data increases and the number of gradation potentials set by the gradation potential setting section also increases. There is a problem that the number of transistors forming the decoder and the H decoder is significantly increased, the size of the liquid crystal drive circuit is increased, and the manufacturing cost is increased.

Further, the liquid crystal display element is generally driven by a plurality of integrated liquid crystal drive circuits, and in order to reduce the manufacturing cost, the number of pins of the integrated circuit device of each liquid crystal drive circuit is large. There is a tendency to reduce the number of integrated circuit devices by pinning. For this reason, when the number of pins is increased, the number of outputs increases, so that the number of elements (transistors) of the conventional liquid crystal drive circuit also increases, which causes a problem that the size of the integrated circuit device increases and the manufacturing cost also increases.

The present invention has been made in view of the above circumstances, and provides a liquid crystal drive circuit capable of preventing an increase in size and manufacturing cost as much as possible even if the image quality is increased and the number of pins is increased. The purpose is to

[0021]

A first mode of a liquid crystal drive circuit according to the present invention is a grayscale potential generating means for generating a potential of 2 ⁿ grayscale level on each of a negative side and a positive side with respect to a predetermined potential. And a potential of one grayscale level corresponding to the incoming n-bit image data is selected from the negative ²ⁿ grayscale levels generated by the grayscale potential generation means and is output. A decoder and a second gradation level generating means for selecting and outputting one gradation level potential corresponding to incoming n-bit image data from the positive side 2 ⁿ gradation levels generated by the decoder. And the polarity inversion signal is at the first level, the n-bit first image data transmitted via the first data bus is sent to the first decoder and the second data is transmitted. N-bit second picture transmitted over the bus When the data is sent to the second decoder and the polarity inversion signal is at the second level, the first image data is sent to the second decoder and the second image data is sent to the second decoder. No. 1 decoder switch circuit, first and second output terminals for outputting the potential corresponding to the image data to the outside, and the polarity inversion signal at the first level. Sends the output of the first decoder to the first output terminal and the output of the second decoder to the second output terminal, and when the polarity inversion signal is at the second level, The output of the first decoder is sent to the second output terminal and the output of the second decoder is sent to the first output terminal.
And a second change-over switch circuit for sending to the output terminal of the.

A second aspect of the liquid crystal drive circuit according to the present invention is the liquid crystal drive circuit according to the first aspect, wherein the liquid crystal drive circuit is provided between the first data bus and the first changeover switch circuit. The first transmitted via a data bus of
Second image data sampled and held by the first register, and the second data bus provided between the second data bus and the first changeover switch circuit and transmitted via the second data bus. And a second register for sampling and holding the image data of 1.

A third aspect of the liquid crystal drive circuit according to the present invention is the liquid crystal drive circuit according to the first aspect, wherein the liquid crystal drive circuit is provided between the first changeover switch circuit and the first decoder. Is provided between the first register for sampling and holding the output of the changeover switch circuit and the first changeover switch circuit and the second decoder, and samples the output of the first changeover switch circuit. , And a second register for holding the same.

A fourth aspect of the liquid crystal drive circuit according to the present invention is the liquid crystal drive circuit according to the first aspect, wherein the liquid crystal drive circuit is provided between the first data bus and the first changeover switch circuit. A first sampling register for sampling the image data, a second sampling register provided between the second data bus and the first changeover switch circuit for sampling the second image data, A first load register provided between the first changeover switch circuit and the first decoder, for holding an output of the first changeover switch circuit, the first changeover switch circuit, and the second load register. And a second load register which is provided between the decoder and the second changeover switch circuit and holds the output of the second changeover switch circuit.

A fifth aspect of the liquid crystal drive circuit according to the present invention is the liquid crystal drive circuit according to any one of the first to fourth aspects, wherein the liquid crystal drive circuit is provided between the second changeover switch circuit and the first output terminal. Is provided on the first and amplifies the input signal
And an amplifier that is provided between the second changeover switch circuit and the second output terminal and amplifies an input signal.

A sixth aspect of the liquid crystal drive circuit according to the present invention is the liquid crystal drive circuit according to any one of the first to fourth aspects, wherein the liquid crystal drive circuit is provided between the first decoder and the second changeover switch circuit. First provided for amplifying input signal
And a second amplifier that is provided between the second decoder and the second changeover switch circuit and that amplifies an input signal.

A liquid crystal drive circuit according to a seventh aspect of the present invention is the liquid crystal drive circuit according to any one of the first to fourth aspects, wherein the first output terminal is an odd-numbered liquid crystal display element to be driven. Connected to one of the signal lines,
The second output terminal is connected to one of two signal lines adjacent to the one signal line of the even-numbered signal lines of the liquid crystal display element.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment of Liquid Crystal Driving Circuit According to the Present Invention
FIG. 1 shows the configuration of the embodiment. In the liquid crystal drive circuit of this embodiment, when the number of data lines (signal lines) of the liquid crystal display element driven by the liquid crystal drive circuit is 2 m, m changeover switch circuits 3 ₁ , ..., 3 _m , The 2m sampling registers 4 ₁ , ..., 4 _2m , the 2m load registers 6 ₁ , ..., 6 _2m, and the D / A converter 7
, M change-over switch circuits 8 ₁ , ..., 8 _m, and an output circuit 9. In FIG. 1, 2i-1
Only the portion connected to the 2nd (even number) data line is shown.

The D / A converter 7, m-number of L decoder 7a _1, ..., and 7a _m, m-number of H decoder 7b _1, ...,
7b _m and a gradation potential setting section 7c. The output circuit 9 has 2m operational amplifiers 9 ₁ , ..., 9 _2m .

The data bus 2 for transmitting the image data taken in by the liquid crystal drive circuit of this embodiment supplies n-bit image data to the odd-numbered data lines of the liquid crystal display element driven by this liquid crystal drive circuit. a data bus 2 ₁ for, and a data bus 2 ₂ Metropolitan for supplying image data of n bits in even-numbered data line.

Changeover switch circuit 3 _i (i = 1, ..., M)
When the level of the polarity inversion signal POL synchronized with the horizontal blanking period supplied from the outside is "H", the data bus 2 ₁ and the sampling register 4 _2i-1 are connected, and the data bus 2 ₂ and the sampling register are connected. When the register 4 _2i is connected and the level of the signal POL is “L”, the connection is switched to connect the data bus 2 ₁ and the sampling register 4 _2i, and the data bus 2 ₂ and the sampling register 4 _2i-1 are connected. Connecting.

Sampling register 4 _i (i = 1, ...,
2m) takes in the image data sent via the changeover switch circuit based on a command from a data control unit (not shown). Load register 6 _i (i = 1, ..., 2 m)
Latches the image data held in the sampling register 4 _i in response to the LOAD signal supplied from the outside.

Load register 6 _2i-1 (i = 1, ..., m)
The image data latched by the L / D converter 7a _i in the D / A converter 7 is supplied to the load register 6 _2i (i
= 1, ..., M), the image data latched is supplied to the H decoder 7b _i in the D / A converter 7.

The gradation potential setting section 7c divides the reference voltage by, for example, resistance division or capacitance division, so that 2 ⁿ (minus side) and 2 ⁿ (minus side) with respect to the potential V _com applied to the common electrode of the liquid crystal display element. (n is the number of bits of image data)
Set the gradation level potential.

The L decoder 7a _i (i = 1, ..., M) is
One gradation corresponding to the n-bit image data latched by the load register 6 _2i-1 among the 2 ⁿ gradation levels on the negative side with respect to the potential V _com set by the gradation potential setting unit 7c. Select the level and output. Further, the H decoder 7b _i (i = 1, ..., M) includes the gradation potential setting unit 7
Of the 2 ⁿ gradation potential levels on the plus side with respect to the potential V _com set by c, one gradation level corresponding to the n-bit image data latched in the load register 6 _2i is selected and output. To do.

Changeover switch circuit 8 _i (i = 1, ..., M)
Is L when the level of the polarity inversion signal POL is "H".
The output terminal of the decoder 7a _i is connected to the positive input terminal of the operational amplifier 9 _2i-1 and the output terminal of the H decoder 7b _i is connected to the positive input terminal of the operational amplifier 9 _{2i to obtain} the signal POL.
Is "L", the connection is switched to connect the output terminal of the L decoder 7a _i and the positive input terminal of the operational amplifier 9 _2i , and the output terminal of the H decoder 7b _i and the operational amplifier 9 _2i-1. Connect to the positive input terminal of. The negative input terminal of each operational amplifier 9 _i (i = 1, ..., 2 m) is connected to its own output terminal.

Then, the operational amplifier 9 _2i-1 (i = 1, ...,
m) amplifies the image data received via the changeover switch circuit 8 _i, and supplies it to the 2i-1th data line of the liquid crystal display element via the output terminal OUT _2i-1 of the liquid crystal drive circuit. Further, the operational amplifier 9 _2i (i = 1, ..., M) amplifies the image data received via the changeover switch 8 _i and outputs the 2i-th pixel of the liquid crystal display element via the output terminal OUT _2i of the liquid crystal drive circuit. Supply to the data line.

In the liquid crystal drive circuit of the present embodiment having such a configuration, when the level of the polarity inversion signal POL is "H", the liquid crystal display element sent via the data bus 2 _i The image signal to be supplied to the 2i−1th data line is sent to the L decoder 7a _i through the changeover switch circuit 3 _i , the sampling register 4 _2i−1 , and the load register 6 _2i−1, and is converted into the above image signal. According to the potential V
The potential of the gradation level on the side of Mymas is selected from _com .
Then, the selected potential is sent to the operational amplifier 9 _2i-1 via the changeover switch circuit 8 _i , amplified and supplied to the 2i-1th data line of the liquid crystal display element. At this time, the image signal sent via the data bus 2 ₂ for supplying to the 2i-th data line of the liquid crystal display element passes through the changeover switch circuit 3 _i , the sampling register 4 _2i , and the load register 6 _2i. It is sent to the H decoder 7b _i , and the potential of the gradation level on the plus side of the potential V _com is selected according to the image signal. Then, the selected potential is sent to the operational amplifier 9 _2i via the changeover switch circuit 8 _i ,
It is amplified and supplied to the 2i-th data line of the liquid crystal display element.

On the other hand, if the level of the polarity inversion signal POL is "L" via the data bus 2 ₁ sent, the image signals to be supplied to the 2i-1-th data lines, the selector switch It is sent to the operational amplifier 9 _2i-1 via the circuit 3 _i , the sampling register 4 _2i , the load register 6 _2i , the H decoder 7b _i , and the changeover switch circuit 8 _i , amplified, and supplied to the 2i-1th data line. It Further, at this time, the image signal to be supplied to the 2i-th data line sent via the data bus 2 ₂ is the changeover switch circuit 3 _i , the sampling register 4 _2i-1 , the load register 6 _2i-1 , L decoder 7a _i , changeover switch circuit 8 _i
Is sent to the operational amplifier 9 _2i via the signal line A, amplified, and supplied to the 2i-th data line.

Therefore, when the level of the polarity inversion signal POL is "H", the potential V is applied to the 2i-1th data line.
A potential corresponding to the image signal on the minus side with respect to _{com is applied} , and a potential according to the image signal on the plus side with respect to the potential V _com is applied to the 2i-th data line. When the level of the polarity inversion signal POL is “L”, the 2i−1th data line is given a potential on the positive side of the potential V _com according to the image signal, and the 2i−1th data line is supplied. _Will be given a negative potential corresponding to the image signal with respect to the potential V _com .

As described above, the liquid crystal drive circuit of this embodiment can output the positive and negative potentials and can drive the liquid crystal display element.

Further, in the liquid crystal drive circuit of the present embodiment, the number of decoders and the number of operational amplifiers in the D / A converter 7 can be halved as compared with the conventional liquid crystal drive circuit. In general, since the number of transistors constituting a decoder for 256 gradations (n = 8) per gradation is 32, an integrated circuit device having 384 outputs (m = 192) has a larger number of transistors than the conventional case. This is a reduction of 1.5 million elements. In the liquid crystal drive circuit of this embodiment, 2m changeover switch circuits are used as compared with the conventional case, but the number of transistors used in this changeover switch circuit is extremely larger than that of the decoder. Few. Therefore, the increase in the number of elements due to the increase in the number of changeover switch circuits can be ignored as compared with the decrease in the number of elements due to the decrease in the number of decoders.

As a result, even if the image quality is increased and the number of pins is increased, the increase in the number of elements can be made extremely small as compared with the conventional case, and the increase in size and manufacturing cost can be prevented as much as possible.

Next, FIG. 2 shows the configuration of a second embodiment of the liquid crystal drive circuit according to the present invention. The liquid crystal drive circuit according to this embodiment is similar to the liquid crystal drive circuit according to the first embodiment shown in FIG. 1 _except that sampling registers 4 _2i−1 , 4 _2i (i =
1, ..., M), the changeover switch circuit 3 _i provided before the D / A converter 7 and the changeover switch circuit 8 _i provided after the D / A converter 7 are respectively connected to the load registers 6 _2i-1 ,
It is provided in the _subsequent stage of 6 _{2i and in} the subsequent stage of the output circuit 9.

In the liquid crystal drive circuit of the second embodiment, when the level of the polarity inversion signal POL is "H", the image signal sent via the data bus 2 ₁ is
Sampling register 4 _2i-1 , load register 6 _2i-1 ,
The output terminal OUT via the changeover switch circuit 3 _i , the L decoder 7a _i , the operational amplifier 9 _2i-1 , and the changeover switch circuit 8 _i.
Sent from _2i-1 . At this time, the image signal sent via the data bus 2 ₂ is sent to the sampling register 4 _2i ,
It is sent from the output terminal OUT _2i via the load register 6 _2i , the changeover switch circuit 3 _i , the H decoder 7b _i , the operational amplifier 9 _2i and the changeover switch circuit 8 _i .

When the level of the polarity inversion signal POL is "L", the image signal sent via the data bus 2 ₁ includes the sampling register 4 _2i-1 , load register 6 _2i-1 , and changeover switch circuit. 3 _i , H decoder 7b
It is sent to the output terminal OUT _2i-1 via _i , the operational amplifier 9 _2i , and the changeover switch circuit 8 _i . At this time, data bus 2
_The image signal sent through ₂ is output through a sampling register 4 _2i , a load register 6 _2i , a changeover switch circuit 3 _i , an L decoder 7a _i , an operational amplifier 9 _2i-1 , and a changeover switch circuit 8 _i. It is sent from OUT _2i .

As described above, it goes without saying that the liquid crystal drive circuit of this embodiment also has the same effects as the liquid crystal drive circuit of the first embodiment.

In the second embodiment, the changeover switch circuit 3 _i (i = 1, ..., M) is loaded in the load register 6.
It is needless to say that may be provided between the _2i-1, sampling register 4 _2i-1 instead of providing the 6 _2i subsequent, 4 _2i and load register 6 _2i-1, 6 _2i. At this time, the change-over switch circuit 8 _i is similar to the output circuit 9 in the first embodiment.
It is possible to provide it in the preceding stage.

Further, in the second embodiment, the changeover switch circuit 3 _i may be provided in the preceding stage of the sampling registers 4 _2i-1 and 4 _{2i as in} the _first embodiment.

The liquid crystal drive circuit of the above-described embodiment can be used for the liquid crystal display element for dot inversion display shown in FIG. 6 and V line inversion display (pixels in the same column are applied with the same polarity voltage and are adjacent to each other). It can also be used for a liquid crystal display device of a display in which voltages of different polarities are applied to pixel columns).

[0051]

As described above, according to the present invention, it is possible to prevent an increase in size and manufacturing cost as much as possible even if the image quality is increased and the number of pins is increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of a liquid crystal drive circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a second embodiment of a liquid crystal drive circuit according to the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional liquid crystal drive circuit.

FIG. 4 is a circuit diagram showing a configuration of a liquid crystal display element.

FIG. 5 is a waveform diagram of a voltage applied to electrodes of a liquid crystal display element.

FIG. 6 is an explanatory diagram illustrating dot inversion display.

[Explanation of symbols]

2 ₁ , 2 ₂ Data bus 3 _i (i = 1, ... m) Changeover switch circuit 4 _i (i = 1, ... 2 m) Sampling register 6 _i (i = 1, ... 2 m) Load register 7 D / A converter 7a _i (i = 1, ... m) L decoder 7b _i (i = 1, ... m) H decoder 7c Grayscale potential setting unit 8 _i (i = 1, ... m) Changeover switch circuit 9 Output circuit 9 _i (i = 1, ... 2 m) Operational amplifiers 22 ₁ , 22 ₂ devices 24 _i (i = 1, ... 2 m) Sampling register 26 _i (i = 1, ... 2 m) Load register 27 D / A converter 27 a _i (i = 1, ... 2 m) 2m) L decoder 27b _i (i = 1, ... 2m) H decoder 27c Gray scale potential setting section 29 Output circuit 29a _i (i = 1, ... 2m) Operational amplifier 29b _i (i = 1, ... 2m) Operational amplifier 61 _{i (i = 1, ... 3} ) data line 62 _{i (i} = , ... 3) common electrode 67 gate line 63 TFT 65 pixel electrode 66 auxiliary capacitor _{OUT i (i = 1, ...} 2m) output terminal POL polarity inversion signal LOAD load signal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI G09G 3/20 641 G09G 3/20 641C (58) Fields investigated (Int.Cl. ⁷ , DB name) G09G 3/36 G02F 1 / 133 505 G09G 3/20

Claims (8)

(57) [Claims] 1. A gradation voltage generating means for generating a respective 2 ⁿ gray-scale-level potential to the negative side and the positive side with respect to a predetermined potential, 2 ⁿ of the negative-side generated by the gradation voltage generating means Of the gradation levels, a first decoder for selecting and outputting one gradation level potential corresponding to the incoming n-bit image data, and a positive side 2 generated by the gradation potential generating means. Of the ⁿ gradation levels, a second decoder that selects and outputs one gradation level potential corresponding to the incoming n-bit image data, and if the polarity inversion signal is the first level, The n-bit first image data transmitted via the first data bus is sent to the first decoder, and the n-bit second image data transmitted via the second data bus is transmitted. The polarity inversion signal is sent to the second decoder. In the case of the second level, a first changeover switch circuit that sends the first image data to the second decoder and sends the second image data to the first decoder; First and second output terminals for outputting a potential corresponding to the data to the outside, and when the polarity inversion signal is at the first level, the output of the first decoder is output to the first output terminal. In addition to sending, the output of the second decoder is sent to the second output terminal, and when the polarity inversion signal is at the second level, the output of the first decoder is sent to the second output terminal. And a second change-over switch circuit for sending the output of the second decoder to the first output terminal. 2. A first image data which is provided between the first data bus and the first changeover switch circuit and which samples and holds the first image data transmitted through the first data bus. A first register, and a second image data that is provided between the second data bus and the first changeover switch circuit, and samples and holds the second image data transmitted via the second data bus. 2. The liquid crystal drive circuit according to claim 1, further comprising: 2 registers. 3. A first register which is provided between the first changeover switch circuit and the first decoder and which samples and holds the output of the first changeover switch circuit, and the first register. The second register provided between the changeover switch circuit and the second decoder, for sampling and holding the output of the first changeover switch circuit, and a second register. LCD drive circuit. 4. The first register comprises a first sampling register and a first load register, and the second register comprises a second sampling register and a second load register. Claim 2
Alternatively, the liquid crystal drive circuit described in 3. 5. A first sampling register provided between the first data bus and the first changeover switch circuit for sampling the first image data, the second data bus and the first sampling register. A second sampling register provided between the first changeover switch circuit and the first decoder, the second sampling register being provided between the first changeover switch circuit and the first decoder and sampling the second image data; A first load register that holds the output of the second changeover switch circuit; and a second load register that is provided between the first changeover switch circuit and the second decoder and that holds the output of the second changeover switch circuit. 2. The liquid crystal drive circuit according to claim 1, further comprising: 6. A first amplifier provided between the second changeover switch circuit and the first output terminal for amplifying an input signal, the second changeover switch circuit and the second amplifier. 6. A liquid crystal drive circuit according to claim 1, further comprising a second amplifier provided between the output terminal and the output terminal for amplifying an input signal. 7. A first amplifier provided between the first decoder and the second change-over switch circuit, for amplifying an input signal, the second decoder and the second change-over switch. 6. A liquid crystal drive circuit according to claim 1, further comprising a second amplifier provided between the circuit and the circuit for amplifying an input signal. 8. The first output terminal is connected to one of the odd-numbered signal lines of the liquid crystal display element to be driven, and the second output terminal is connected to the even-numbered signal line of the liquid crystal display element. 8. The liquid crystal drive circuit according to claim 1, which is connected to one of two signal lines adjacent to the one signal line among the signal lines.