JP3361314B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device such as a thin film transistor and a thin film diode used for a switching element, an integrated circuit, a liquid crystal display element and the like.

[0002]

2. Description of the Related Art Thin film semiconductor devices, such as thin film transistors and thin film diodes, have been attracting attention as devices that can be formed on an insulating substrate such as a drive circuit of a liquid crystal display device and an amplifier circuit of an image sensor. Even in the monolithic technology of forming an element on the top surface, it has been attempted to use a thin film transistor for the purpose of increasing the degree of integration of the element and to realize a three-dimensional circuit. The thin film semiconductor used at this time is a polycrystalline material such as polysilicon, an amorphous material such as amorphous silicon, or an intermediate position between them, and has characteristics of polycrystalline and amorphous. A semi-amorphous semiconductor such as semi-amorphous silicon that combines the above is used.

However, the mobility of carriers of these thin film semiconductors is a fraction to several 1 as compared with that of single crystals.
The operating speed of the thin film semiconductor device using these materials was remarkably low because it was remarkably small, which was 1/0. For example, amorphous silicon has an electron mobility of 1 cm ² / Vs or less, and general polysilicon has an electron mobility of 10 to 30 cm ² / Vs. Also,
Even with a special manufacturing method such as laser annealing, the limit is 200 cm ² / Vs, which is significantly smaller than the electron mobility of single crystal silicon of 1350 cm ² / Vs. Therefore, thin-film semiconductor devices are used for relatively low-frequency applications and single-crystal semiconductor auxiliary applications
For example, it was only used as a load resistance element in a static RAM.

The reason why the carrier mobility of the thin film semiconductor is low is considered to be that carrier scattering is likely to occur due to short crystal periodicity in an amorphous material, and thus the mean free path of carriers is short. It is also considered that, in the polycrystalline material, the concentration of the foreign element becomes high at the crystal grain boundaries, and a barrier is generated at the crystal grain boundaries, so that carriers are randomly scattered at the crystal grain boundaries. Therefore, attempts have been made to increase the mobility by decreasing the number of grain boundaries per unit length by increasing the size of each crystal. The semi-amorphous material has a large part with a long periodicity like a polycrystalline material as a whole, and since there is no clear grain boundary,
Carrier scattering at grain boundaries is suppressed, and relatively large carrier mobility is exhibited. However, it is difficult to obtain a semi-amorphous material having a crystal with a large grain size (a region in which long-range order is maintained). Further, although it is easy to obtain polysilicon having a large grain size, if the size and grain size of the element are about the same, variation in the characteristics of the element becomes large,
Not practical.

[0005]

The problem to be solved by the present invention is to improve the carrier mobility of a thin film semiconductor and to provide a semiconductor material suitable for use in a thin film semiconductor device.

[0006]

DISCLOSURE OF THE INVENTION The present inventors have been studying the cause of obtaining a material having a large mobility by laser annealing. That is, although the size of each crystal is the same, that is, about several to 10 μm,
In the case of thermal annealing in an ordinary electric furnace, the electron mobility obtained was 30 cm ² / Vs, whereas that of laser annealing was 200 cm ² / Vs. One of the causes of this is that in thermal annealing, annealing takes a sufficiently long time, so many foreign elements are precipitated at the grain boundaries, whereas in laser annealing, in particular laser annealing using pulse laser, It was considered that the barrier formation at the grain boundary was incomplete because there was no time to move to the grain boundary.

In addition, it is considered that the stress generated during laser irradiation is preserved as it is in the laser annealing, and it has some influence on the grain boundaries. That is, it is considered that the laser annealing makes the junctions of the grain boundaries close to each other and reduces the width of the barriers at the grain boundaries.

Then, in order to prove the hypothesis, FIG.
An experiment was performed as shown in. That is, a film of an insulating material that shrinks by heat on the semiconductor substrate 101, for example, a film of a material of phosphorus glass, boron glass, phosphorus-boron glass, AN glass, quartz glass,
A thin film semiconductor material film, for example, a polysilicon film, an amorphous silicon film, or a semi-amorphous silicon film was further formed by a plasma CVD method or a sputtering method. It should be noted here that thermal contraction is different from thermal expansion. The latter is reversible in thermal cycling, whereas the former is not reversible in thermal cycling. That is, it is an irreversible phenomenon. Therefore, in the above laminating step, it is important to maintain a sufficiently low temperature at which the heat-shrinkable coating does not shrink.

Then, the semiconductor film and the insulating film were patterned to obtain the state shown in FIG. 1 (B). Then, these were heated at an appropriate temperature to shrink the insulating film, and thus the semiconductor film thereon. This temperature is determined by the underlying insulating material, but in the case of quartz, the optimum temperature is about 600 ° C., and the amorphous silicon film is crystallized at this temperature. This state was maintained for 24 hours, for example.

Thereafter, for the purpose of neutralizing crystal disorder due to annealing, thermal annealing was performed in a hydrogen stream at 200 to 400 ° C., and hydrogen added to the polysilicon formed by the annealing. A device having a MOS structure was manufactured using this semiconductor, and the electron mobility was measured. As a result, a mobility of 40 to 60 cm ² / Vs was obtained. This value was as large as 30 to 100% as compared with the case where the underlayer was formed on a material that did not cause heat shrinkage.

Although this experiment itself is not a direct proof that high mobility can be obtained by laser annealing, it is possible to apply stress to the upper semiconductor film and improve the mobility by using a special material for the underlayer. It was discovered by chance that this was possible. Based on this experiment, the inventors of the present invention continued their research and arrived at the following invention.

The material used as the substrate is either a semiconductor or glass
It may be an insulator such as a material. Also, seemingly contradictory
However, the heat-shrinkable insulating film that will be formed in a later step is sufficient.
When thick, the effect of the substrate can be ignored. But
In such a case, no matter what the substrate is,
I do not care. And heat-shrinkable insulation on these substrates
Materials such as phosphorus glass, boron glass, phosphorus boro
Glass, AN glass, quartz glass
By the optical CVD method, plasma CVD method, or sputtering method.
Is deposited. In that case, first form a silicon oxide film
After that, phosphorus or boron is added by an ion implantation method or the like.
10¹⁴-10¹⁸cm^-2, Preferably 10 ¹⁶~ 5 x 10
¹⁷cm^-2You may use what was inject | poured with the density of. these
When hydrogen is contained in the glass material of
In that case, it was found that the heat shrinkage was relatively large. Also,
The thickness of these insulating layers is 50 to 1000 nm.
Was suitable. This thickness is the thickness of the semiconductor coating deposited on top
It is determined by the size of the device. But Naga
If it is extremely thin, it will peel off from the substrate during heat shrinkage.
Do not shrink or shrink due to the influence of the substrate being too large.
I am disappointed. A thickness of at least 50 nm is required
It

After that, a film of a semiconductor material such as amorphous silicon, polysilicon, or semi-amorphous silicon is formed thereon to a thickness of 10 to 500 nm.
These semiconductor coatings may or may not contain hydrogen. Further, for example, after forming the amorphous silicon coating film at a low temperature, the coating film may be converted into polysilicon by laser annealing. This is because laser annealing heats only the vicinity of the surface of the semiconductor film and has no thermal effect on most of the insulating film. Especially, when visible light is used as the laser light, silicon etc. Laser light is absorbed in the semiconductor layer, whereas the insulating layer is transparent to visible light, so that the thermal action is extremely small. In any case, it is necessary to form the semiconductor film at a temperature at which the film of the underlying insulating layer does not shrink thermally.

Then, the semiconductor film and the insulating film are patterned. The patterning may be performed by completely removing the insulating film as shown in FIG. 2A or to a certain depth as shown in FIG. 2B. In either case, the patterning may be performed by patterning. It was found that the selection of the width L of the region to be separated and the depth T from the interface between the semiconductor film and the insulating film to the bottom of the groove formed is important.
We have L / T <1000, preferably L / T <
It has been found necessary to be 100. This is because when L is significantly larger than the thickness of the insulating layer that thermally contracts, the thermal contraction proceeds in the vertical direction instead of in the horizontal direction. In that case, the semiconductor film formed above is hardly affected.

Then, the insulating coating is shrunk by a heating process. In the case of silicon oxide, 600 to 1000 ° C. is suitable as the temperature at this time, but the semiconductor film is crystallized at the same time in this step. Especially when annealed at a high temperature, many crystal nuclei are generated and the size of the crystal becomes small. To avoid that, first 500-700
C., preferably 550 to 600.degree. C. for 12 to 70 hours, for example, 580.degree. C. for 36 hours to crystallize a silicon-based material such as amorphous silicon, and then 700 to 1000.degree. C., preferably 750. ~
12 to 70 hours at 800 ° C, for example 24 at 780 ° C
The insulating layer may be contracted by annealing for a time.
In addition, a non-oxidizing atmosphere such as argon or a reducing atmosphere such as hydrogen was suitable as the atmosphere for these thermal annealing.
When annealed in a vacuum of 0 ^-2 torr or less, remarkable shrinkage occurred especially when a material containing a large amount of hydrogen was used for the insulating film. It is considered that this is because hydrogen in the insulating film became water and went out. If the temperature of this annealing is raised, thermal contraction will occur more remarkably, but if the temperature is too high, the insulating material will melt or become glassy and show fluidity, which is not suitable. Especially when phosphorus glass, boron glass, or phosphorus glass is used, the vitrification temperature is low, so care must be taken.

FIG. 3 illustrates another method for achieving the present invention. First, a heat-shrinkable insulating film is formed on an insulator or a semiconductor substrate and is patterned to obtain FIG. 3 (A). Further, a semiconductor film is formed on it to obtain FIG. 3 (B). Then, the insulating film is thermally shrunk by thermal annealing. In this case, unlike the case shown in FIGS. 1 and 2, the semiconductor film is not cut, and the semiconductor film is in direct contact with the substrate. Therefore, when a part of the semiconductor film is used as wiring, Alternatively, it is effective when it is necessary to make contact between a substrate such as a semiconductor substrate and a semiconductor film.

FIG. 4 shows a manufacturing method including both steps for obtaining the present invention shown in FIGS. 2 and 3.
First, an insulating material 402 having heat shrinkability is formed on a substrate 401.
A and B are selectively formed and a semiconductor film 40 is formed thereon.
3 is formed. Then, the coating films 403 and 402A, B are formed by using a known patterning technique such as dry etching.
Is etched to obtain FIG. 4 (B). After that, the insulating coatings 402a to 402d are contracted by thermal annealing, and the semiconductor coatings 403a to 403d on the insulating coatings 403a to 403d are stressed, thereby exhibiting high mobility.

FIG. 4C shows an example of an element manufactured by this method. This is a complementary MOS (CMOS)
An element called a thin film transistor is used to form p-type impurity regions 412a to 412c on a single crystal semiconductor substrate 411, and a semiconductor gate electrode 413 is formed.
a and b are provided. Semiconductor gate contains phosphorus
It is common to use type semiconductors. Then, heat-shrinking insulating coatings 414a and 414b are formed thereon, and a semiconductor coating having an n-type semiconductor region is further formed thereon. n
Of the type semiconductor regions, 415b and 415c are in contact with the n-type semiconductor region provided on the substrate. Like this 412b
And 415b, or the interface between 412c and 413c is PN
Although they are junctions, when both are sufficiently doped and are degenerate semiconductors, there is almost no rectifying action. Semiconductor gates 416a and 416b are provided on the semiconductor region. Further, the interlayer insulating films 417a to 417e are formed, and after the drilling step, the metal electrode is formed of a material such as aluminum, aluminum-silicon alloy, tungsten, molybdenum, or an alloy thereof with silicon.

Thus, contacting the thin film semiconductor region with the semiconductor substrate facilitates electrode formation. Figure 4 (d)
Shows a circuit diagram of an element on the left side of the element of FIG. In the case of having such a multi-layer structure, a deep hole must be formed in order to form an electrode, and the area of the hole is shown in FIG. 4 in order to make a reliable contact through the deep hole.
It is necessary to make the area sufficiently large like 418a and 418 of (C). This is because when the hole is deep, the electrode material often adheres to the side surface of the hole when the coating film for the electrode is formed, and the hole is often blocked without forming the coating film to the inside of the hole. is there. In this case, contact cannot be surely made. However, for example, the electrode of 418b has relatively shallow holes, so that the area of the electrode forming portion can be reduced.

In a multi-layered semiconductor device, it is not desirable to form a contact hole up to the semiconductor substrate and make contact with the wiring of the uppermost layer or a layer near it. Therefore, also in the case of FIG.
Instead of providing a and f, the impurity regions 412a and 412 are
By designing so as to also serve as a wiring as it is, contact to the impurity region becomes unnecessary, and the area of the element can be made sufficiently smaller than that shown in FIG.

[0021]

[Example] [Example 1] Resistivity of 10³Ωcm p-type single
Utilizing conventional integrated circuit manufacturing technology on crystalline silicon substrate 501
Then, an n-channel MOSFET as shown in FIG.
Was produced. That is, 502a-c are so-called LO.
Formed by COS technology or other similar technology
Element isolation region consisting of a thick oxide film
503a and b have a thickness of 10
nm formed on the gate insulating films 504a and 504a,
A gate electrode with a thickness of 200 nm.^{twenty one}cm
^-3It is heavily doped n-type silicon. These gates
The electrodes are L-shaped as shown in FIG. 5 (B '). It
505a-d are field insulators and gates.
Self-aligned (self-aligned) using the electrode as a mask
The impurity region formed as a
And arsenic 3 × 10 ²⁰cm^-31 x 10²⁰c
m^-3Contains. Furthermore, as shown in FIG.
Impurity regions 505a and 505d are formed on the semiconductor substrate.
It is also electrically connected to other elements and power supply. Ge
The width of the electrode was 1 μm. Also, Source Dray
The length of the impurity region in the channel direction is about 5 μm,
The width was 3 μm.

Then, a silicon oxide film was deposited to a thickness of 500 nm by the glow discharge plasma CVD method. The manufacturing method at this time will be briefly described. Monosilane gas (SiH ₄ ) and hydrogen gas were used as raw material gases, and high frequency (1
The monosilane was decomposed by discharging (3.56 MHz). The pressure in the chamber during the reaction was 0.1 torr. The substrate temperature was room temperature or liquid nitrogen was used for cooling. Various measurements revealed that the amount of hydrogen contained in the silicon oxide film thus obtained was about 30 atomic%. Then, the silicon oxide film is etched by a known dry etching technique to form the silicon oxide region 5
06a and b were formed. As the raw material gas, disilane gas (Si ₂ H ₆ ) can be used in addition to monosilane.

Then, a thickness of 200 is obtained by the sputtering method.
nm amorphous silicon film 507 was formed thereon.
The substrate temperature is room temperature, and the sputtering target has a purity of 99.9.
It was a silicon target of 9999% or more. The atmosphere during sputtering was 100% argon and 0.2 torr. The power used for sputtering was a high frequency 200 W of 13.56 MHz. Thus, FIGS. 5B and 5B were obtained.

Then, the silicon coating 507 and the silicon oxide coatings 506a and 506b were selectively removed by a known etching technique. A top view of the element obtained by this etching is shown in FIG. The portion where the silicon film is in contact with the underlying substrate or the gate electrode to form a contact is the hatched portion in the figure. At this time, 200 nm of the silicon oxide film was left as it was. Thereafter, the substrate, ^10-5
It is heated to 600 degrees C in a vacuum of torr and the state is set to 7
Hold for 0 hours. Further, in that state, the temperature was raised to 800 ° C. over 2 hours, and the state was maintained for 3 hours. This step causes crystallization of amorphous silicon and thermal contraction of the insulating film.

Then, the surface of the silicon coating 507 was exposed to a dry high temperature oxygen atmosphere to form a thermal oxide film having a thickness of about 10 nm. This oxide film is used later as a gate insulating film. Of this oxide film, 507b in FIG.
Those formed on and d are removed to expose the underlying silicon film. Further, a polycrystal silicon film was formed thereon by a thermal decomposition method of silane. About 10 ²⁰ to 10 ²¹ cm ⁻³ of phosphorus was added to polycrystalline silicon to make it good conductivity. Then, the gate electrode 5 is selectively removed.
08a and b were formed. This gate electrode is 507b
And d contact silicon coatings 507b and d,
Therefore, it is in contact with the gate electrodes 503a and 503 existing below.

Further, boroso ions were implanted by 10 ¹⁴ to 10 ¹⁵ cm ^-2 by the ion implantation method. Then, it was annealed at 1000 ° C. for 30 minutes in vacuum to recrystallize the amorphous region generated by the ion implantation to obtain p-type impurity regions 509a to 509d. Further, phosphorus / boron glass was formed on the surface, and the surface was flattened by using a reflow technique to obtain an interlayer insulating film 510. Then, the electrode forming holes were provided to form the aluminum electrodes 511a to 511d. Through the above steps, a CMOS using a thin film transistor having a multilayer structure was manufactured as shown in FIG. The hole mobility of the thin film transistor (P-channel type) thus obtained was 50 to 100 cm ² / Vs, and the characteristic was improved about twice as much as the conventional one.

[Embodiment 2] An n-channel MOSFET as shown in FIG. 5A is formed on a p-type single crystal silicon substrate 501 having a resistivity of 10 Ωcm by utilizing a conventional integrated circuit manufacturing technique.
Was produced. The size of the details of the device was the same as in Example 1. Then, a silicon oxide film was deposited to a thickness of 500 nm by the glow discharge plasma CVD method. The manufacturing method at this time was almost the same as in the case of Example 1, but 1000 ppm to 20% of phosphine (P
H ₃₎ were mixed. Therefore, the obtained film contained phosphorus. The amount of hydrogen contained in the silicon oxide film was 30 atom% as in Example 1. The silicon oxide film containing phosphorus was etched by a known dry etching technique to form silicon oxide regions 506a and 506b. Then, a 200 nm-thick amorphous silicon film 507 was formed thereon by a sputtering method. The film forming conditions were the same as in Example 1. Thus, FIGS. 5B and 5B were obtained.

Then, the silicon coating 507 and the silicon oxide coatings 506a and 506b were selectively removed by a known etching technique. A top view of the element obtained by this etching is shown in FIG. The portion where the silicon coating is in contact with the underlying substrate or gate electrode is the hatched portion in the figure. At this time, 20 nm of the silicon oxide film was left as it was. After that, the substrate is placed in a vacuum of 10 ⁻⁶ torr and the excimer laser light (KrF laser, wavelength 24
8 nm, pulse width 30 nsec: 200 mJ / pulse,
50 shots). Through this step, the amorphous silicon film was crystallized. After that, it was held at 700 ° C. for 12 hours also in vacuum. Through this step, the insulating film causes thermal contraction. Further, hydrogen passivation was performed by holding the substrate at 200 to 600 ° C. for 3 hours in a hydrogen atmosphere to improve the electrical characteristics of silicon.

Then, the surface of the silicon coating 507 was exposed to a dry, high temperature oxygen atmosphere to form a thermal oxide film having a thickness of about 10 nm. This oxide film is used later as a gate insulating film. Of this oxide film, 507b in FIG.
Those formed on and d are removed to expose the underlying silicon film. Further, a polycrystalline silicon film having a thickness of 300 nm was formed thereon by a thermal decomposition method of silane. About 10 ²⁰ to 10 ²¹ cm ⁻³ of phosphorus was added to polycrystalline silicon to make it good conductivity. Then, this was selectively removed to form gate electrodes 508a and 508b. This gate electrode has a silicon coating 507b at 507b and 507d.
And the gate electrode 503 underneath, and thus underneath
It comes into contact with a and b.

Further, boroso ions were implanted by 10 ¹⁴ to 10 ¹⁵ cm ^-2 by the ion implantation method. Then, it was annealed at 1000 ° C. for 30 minutes in vacuum to recrystallize the amorphous region generated by the ion implantation to obtain p-type impurity regions 509a to 509d. Further, phosphorus / boron glass was formed on the surface, and the surface was flattened by using a reflow technique to obtain an interlayer insulating film 510. Then, the electrode forming holes were provided to form the aluminum electrodes 511a to 511d. Through the above steps, a CMOS using a thin film transistor having a multilayer structure as shown in FIG. 6B was manufactured. The thin film transistor (P
Channel type) has a hole mobility of 150 to ²⁰⁰ cm ² /
It was Vs, and it was seen that the characteristics were more than doubled as compared with the conventional one.

[Embodiment 3] An n-channel MOSFET as shown in FIG. 5A is formed on a p-type single crystal silicon substrate 501 having a resistivity of 10 Ωcm by utilizing a conventional integrated circuit manufacturing technique.
Was produced. The size of the details of the device was the same as in Example 1. Then, a silicon oxide film was deposited to a thickness of 500 nm by the glow discharge plasma CVD method. The manufacturing method at this time was almost the same as that in Example 1, but 1000 ppm to 20% of phosphine was mixed in the raw material gas. Therefore, the obtained film contained phosphorus. The amount of hydrogen contained in the silicon oxide film was 30 atom% as in Example 1. The silicon oxide film containing phosphorus was etched by a known dry etching technique to form silicon oxide regions 506a and 506b. Then, a 200 nm-thick amorphous silicon film 507 was formed thereon by a sputtering method. The film forming conditions were the same as in Example 1. Thus, FIGS. 5B and 5B were obtained.

Then, the silicon coating 507 and the silicon oxide coatings 506a and 506b were selectively removed by a known etching technique. A top view of the element obtained by this etching is shown in FIG. The portion where the silicon coating is in contact with the underlying substrate or gate electrode is the hatched portion in the figure. At this time, 20 nm of the silicon oxide film was left as it was. After that, the substrate is placed in a vacuum of 10 ⁻⁶ torr and the excimer laser light (KrF laser, wavelength 24
8 nm, pulse width 30 nsec, 100 mJ / pulse,
50 shots). By this step, the amorphous silicon coating became semi-amorphous. The semi-amorphous state was determined by Raman spectroscopy. After that, it was held in vacuum at 600 ° C. for 72 hours. By this process, the insulating film caused heat shrinkage. Further, the substrate is placed at 200 to 400 ° C., for example 300
Hydrogen passivation was carried out by holding in a hydrogen atmosphere, for example, a mixed gas of hydrogen 20% and argon 80% (1 atm) for 30 minutes at a temperature of C to improve the electrical characteristics of the semi-amorphous silicon.

After that, a silicon oxide film having a thickness of about 100 nm was formed on the silicon film 507 by the glow discharge method. This oxide film is used later as a gate insulating film. Of this oxide film, the one formed on 507b and 507d of FIG. 6A 'is removed to expose the underlying silicon film. Further, a polycrystalline silicon film having a thickness of 300 nm was formed thereon by a thermal decomposition method of silane. About 10 ²⁰ to 10 ²¹ cm ⁻³ of phosphorus was added to polycrystalline silicon to make it good conductivity. Then, the gate electrode 5 is selectively removed.
08a and b were formed. This gate electrode is 507b
And d contact silicon coatings 507b and d,
Therefore, it is in contact with the gate electrodes 503a and 503 existing below.

Further, boroso ions were implanted by 10 ¹⁴ to 10 ¹⁵ cm ^-2 by the ion implantation method. Then, it was annealed in vacuum at 600 ° C. for 30 hours to recrystallize the amorphous regions generated by the ion implantation to obtain p-type impurity regions 509a to 509d. Further, phosphorus / boron glass was formed on the surface, and the surface was flattened by using a reflow technique to obtain an interlayer insulating film 510. And
Aluminum holes 511a to 511d were formed by forming electrode forming holes. Through the above steps, a CMOS using a thin film transistor as shown in FIG. 6B was manufactured. Thin film transistor (P-channel type) thus obtained
Has a hole mobility of 130 to 150 cm ² / Vs,
The characteristics were improved more than twice as compared with the conventional one.
Also, the variation in mobility among the devices was small.

[0035]

According to the present invention, it becomes possible to improve the carrier mobility of a thin film semiconductor. The degree of the improvement was about 20 to 100%, but in some cases, the improvement was three times or more. In this example, the electron mobility was not particularly mentioned, but the mobility was improved by manufacturing through the same steps. In the present embodiment, silicon was mainly used as the semiconductor material for explanation, but the same phenomenon was confirmed whether germanium or a compound semiconductor such as a silicon germanium alloy was used.

Although only the semiconductor substrate is used as the substrate in this embodiment, an insulating substrate may be used, as described in the text. In this embodiment, only the first layer transistor on the semiconductor substrate and the second layer thin film transistor on the semiconductor substrate are shown. However, for example, the first layer transistor on the semiconductor substrate In the present invention, a first thin film transistor is formed, and this is used as a transistor of a second layer, a heat shrinkable material is formed on the thin film transistor and the like as a substrate, and a second thin film transistor is formed thereon. It is also possible to take a three-layer structure of a third-layer transistor, and further, a first thin film transistor and a second thin film transistor are formed on the insulating substrate to form a two-layer structure on the insulating substrate. It is also possible to construct structural elements. The former is for the purpose of increasing the integration density in semiconductor integrated circuits,
In addition, the latter can be adopted, for example, in a liquid crystal display element for the purpose of reducing the semiconductor element region and increasing the translucent region.

[Brief description of drawings]

FIG. 1 shows an example of a method for producing a thin film semiconductor material of the present invention.

FIG. 2 shows an example of a method for producing a thin film semiconductor material of the present invention.

FIG. 3 shows an example of a method for producing a thin film semiconductor material of the present invention.

FIG. 4 shows an example of a method for producing a thin film semiconductor material of the present invention and an example of an element using the semiconductor material of the present invention.

FIG. 5 shows an example of a method for producing a thin film semiconductor material of the present invention.

FIG. 6 shows an example of a method for manufacturing a thin film semiconductor material of the present invention.

[Explanation of symbols]

101 ... substrate 102 ... Insulating coating having heat shrinkability 103 ... Semiconductor coating

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Claims (2)

(57) [Claims] 1. A phosphorous or boron compound is formed on a substrate by using a gas phase reaction.
An insulating coating film containing hydrogen and 10 to 30 atomic% of hydrogen is formed, the insulating coating film is formed in an island shape, and a semiconductor film is formed on the insulating coating film. A method for manufacturing a semiconductor device, comprising heating the insulating coating film at a temperature of ℃ to 1000 ℃ to shrink the insulating film. 2. Phosphorus or boron is formed on a substrate by using a gas phase reaction.
An insulating coating film containing hydrogen and 10 to 30 atomic% hydrogen is formed, a groove is formed in the insulating coating film, a semiconductor film is formed on the insulating coating film, and the temperature is 600 ° C. in vacuum. A method for manufacturing a semiconductor device, which comprises heating at ˜1000 ° C. to shrink the insulating film.