JP3353570B2 - Flat semiconductor element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a high withstand voltage and a large current capacity, such as a power transistor or a thyristor enclosed in a flat package of a double-sided cooling type.

[0002]

2. Description of the Related Art Gate turn-off thyristors (GTO thyristors) have been used as high-withstand-voltage, large-current-capacity semiconductor elements (hereinafter referred to as power semiconductor elements) for power conversion of vehicles and industrial inverters and converters. Thyristors, bipolar transistors, insulated gate bipolar transistors (IGBTs) and the like are used.
In order to maintain a high withstand voltage, a power semiconductor element is usually housed in a sealed flat package having ceramics as an insulator and having copper electrodes on upper and lower sides. Normally, in a power thyristor, the element element is round,
The outer shape of the package containing the element is also round. On the other hand, in the IGBT, a rectangular package in which a plurality of rectangular chips are housed in the same package is used for increasing the capacity. In these devices, the outer shape of the package has become larger as the breakdown voltage and the capacity of the semiconductor device have been increased.

FIG. 2 is a sectional view of a conventional semiconductor package 10. As shown in FIG. However, in order to make the structure of the package easier to understand, the state before the final assembly is shown. The lower copper electrode 8 of the power semiconductor device package 10 is made of Kovar (Fe-29% Ni-17) having a thermal expansion coefficient similar to that of ceramics.
% Co) or a lower drawing plate 7 having a drawing structure of an Fe-42% Ni alloy or the like, and silver brazing is applied to one end face of the insulating ring 6 made of ceramics. Ceramic insulation ring 6
A welding plate 5 such as Kovar is silver-brazed at the other end.

The other upper copper electrode 1 is brazed to a welding plate 3 made of silver or the like by Kovar or the like via a copper upper drawing plate 2 having a drawing structure. Package 10
After the semiconductor element 9 is accommodated therein, the welding plate 5 and the welding plate 3 are joined by welding, and the element 9 is sealed in the package 10. In order to increase the adhesion between the upper and lower copper electrodes and the element 9, the upper diaphragm plate 2 and the lower diaphragm plate 7 are flexible.

[0005]

However, the diameter of the semiconductor element has been rapidly increased in order to increase the withstand voltage and the current capacity of the power semiconductor element. Accordingly, when the outer shape of the package becomes large, even if the flexible lower diaphragm plate 7 is interposed between the insulating ring 6 of ceramics and the lower copper electrode 8, the insulating ring 6 of ceramics and The distortion generated due to the difference in thermal expansion coefficient could not be completely absorbed, and the lower copper electrode 8 was deformed. For example, in the case of the lower copper electrode 8 having a diameter of 130 mm, about 150 μm
Warpage. Therefore, the contact between the upper and lower copper electrodes 1 and 8 and the semiconductor element 9 is poor, and the cooling is insufficient, which may cause a problem in reliability.

On the other hand, the diameter of the insulating ring 6 must be reduced in order to reduce the size of the package, and the diameter of the copper electrode 8 must be increased in order to improve the heat dissipation from the semiconductor element. There is a demand that the distance between the insulating ring 6 and the copper electrode 8 should be rather reduced. Therefore, it has become difficult to obtain a sufficient effect by a method of reducing distortion caused by a difference in thermal expansion coefficient by a diaphragm plate brazed between a ceramic and a copper electrode.

[0007] Therefore, an attempt was made to braze a copper drawn plate which can easily process the drawn structure and is adaptable to shrinkage due to a difference in thermal expansion coefficient because the material is soft. However, there is a large gap between the copper plate (22 × 10 ^-6 ° C. ^-1 ) and the ceramics (alumina: 7 × 10 ^-6 ° C. ^-1 ) in terms of the coefficient of thermal expansion. When the brazing was performed on the insulating ring 6, the surface of the copper diaphragm plate was cracked or pulled, resulting in poor airtightness.

In view of the above problems, an object of the present invention is to provide a flat semiconductor device which does not give a strain to a brazed copper electrode and has good airtightness even in a large flat package. To provide.

[0009]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention relates to a flat semiconductor device in which a diaphragm plate at the peripheral edge of a copper electrode is brazed to an insulating ring of ceramics. However, it is assumed that the thermal expansion coefficient is larger than that of ceramics, and the metal plate is smaller than copper, and is integrally brazed to the end face of the insulating ring.

The metal plate has a coefficient of thermal expansion of 8 × 10 ^{−6 to} 20 × 10 ⁻⁶ ° C. ⁻¹ , especially F
E-42% Ni alloy, Kovar, or iron is preferred.
In particular, it is preferable that the insulating ring is a square ring. The following effects are obtained by taking the above measures.

That is, by using a copper diaphragm plate, the copper electrode and the diaphragm plate have the same thermal expansion coefficient.
In addition, if the copper diaphragm plate has a larger thermal expansion coefficient than that of ceramics and is brazed to the end face of the insulating ring with a metal plate smaller than copper interposed therebetween, the insulation between the copper diaphragm plate and ceramics can be reduced. In the distortion caused by the difference in the thermal expansion coefficient from the ring, the contraction of the copper aperture plate is reduced by the intervening metal plate. Further, the copper drawing plate is rich in flexibility and hardly transmits distortion.

As the metal plate, the thermal expansion coefficient of any of the Fe-42% Ni alloy, Kovar, and iron is larger than that of ceramic and smaller than that of copper. In particular, when the insulating ring is a square ring, a portion having a large inhomogeneous distortion is generated, but the effect of suppressing the distortion is great.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention uses a copper diaphragm plate made of the same material as a copper electrode in joining a ceramic insulating ring of a semiconductor package and a diaphragm plate. In between, a metal plate having a thermal expansion coefficient between that of ceramics and that of copper is brazed across a metal plate. As such a metal plate, F
An e-42% Ni alloy, Kovar, iron, or the like can be used.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
The annular insulating ring 6 is made of alumina ceramic having a purity of 90% to 96%, and has an outer diameter of 150 mm and a height of 28 mm. On one end face (the lower side in the figure) of the insulating ring 6, Fe-4
A copper lower diaphragm plate 17 on the periphery of the lower copper electrode 18 is brazed across the annular metal plate 20 of 2% Ni alloy, and a welding plate 15 of Fe-42% Ni alloy is formed on the other end surface. After all it is brazed. A copper upper drawing plate 12 is brazed to the periphery of the upper copper electrode 11, and a welding plate 13 made of an Fe-42% Ni alloy is brazed to the periphery. The thyristor element 19 is mounted on the lower copper electrode 18, the upper copper electrode 11 is positioned so as to be in contact with the upper electrode of the element, and the outer circumferences of the welding plates 13 and 15 are welded. Reference numeral 14 denotes a positioning guide of the tetrafluoroethylene resin for positioning the element 19. Here, the upper part and the lower part are tentatively attached for distinction, and do not indicate a vertical relation at the time of assembly or use. A disc such as Mo may be interposed between the element 19 and the upper electrode. Although the gate electrode and the gate terminal of the thyristor are connected by an appropriate method, the structure is omitted.

A manufacturing method for obtaining the structure shown in FIG. 1 will be described below. First, Mo-Mn powder paste is applied to both end faces of an annular insulating ring 6 made of alumina ceramic having a purity of 90% to 96% by screen printing, and the pastes are placed in a humidified hydrogen atmosphere.
After baking at 400 to 1550 ° C., nickel plating is performed on the surface to form a strong metal layer on both end surfaces of the insulating ring 6.

In a jig for brazing graphite, Fe
A welding plate 15 made of a -42% Ni alloy is placed, and an insulating ring 6 that has been subjected to the above-described conductive treatment is placed with a silver solder therebetween. Further, on the end face of the insulating ring 6, a Fe-42% Ni
The lower plate 17 is placed on the annular metal plate 20 made of the alloy and the silver solder again, and the lower copper electrode 18 having a diameter of 130 mm and a height of 10 mm is placed between the brazing portions with a silver brazing piece interposed therebetween. (That is, brazing is performed upside down in FIG. 1, but this is not an absolutely necessary condition.) As silver brazing, for example, JIS BAg-8 can be used.
The brazing jig is placed in a hydrogen atmosphere at 800 to 850.
Hold at 10 ° C. for 10 minutes to perform brazing. The melting point of the silver braze BAg-8 is 783 ° C. The brazing atmosphere may be a vacuum.

Further, the upper copper electrode 11, the upper drawing plate 12, and the welding plate 13 of the Fe-42% Ni alloy are brazed using silver brazing. The thyristor element 19 was placed on the lower copper electrode 18 to which the insulating ring 6 was brazed, and the outer peripheries of the welding plates 13 and 15 were welded by covering the upper electrode brazed with a welding plate. The inside of the package is gas-replaced from a replacement pipe (not shown), and finally the replacement pipe is closed and sealed.

By brazing the insulating ring 6 via the Fe-42% Ni alloy metal plate 20 using the copper lower diaphragm plate 17 as described above, the conventional brazing plate of the Fe-Ni alloy has been used. There is no big warp like when attached,
The amount of warpage of the lower copper electrode 18 was 20 μm or less. As a result, after brazing, the conventional processing for smoothing the surface of the copper electrode is no longer necessary.

This is because the lower copper electrode 18 and the lower diaphragm 17
Between the lower diaphragm plate 17 and the insulating ring 16, the distortion caused by the difference in thermal expansion coefficient between the lower diaphragm plate 17 and the insulating ring 16 is caused by the intermediate Fe-42% Ni alloy metal plate. 20 and the copper lower diaphragm plate 17 is rich in ductility, so that distortion due to the difference in thermal expansion coefficient between the lower diaphragm plate 17 and the insulating ring 16 is not transmitted to the lower copper electrode 18. It is thought that.

In addition, no cracking or pulling occurred when a copper drawing plate was directly brazed to a ceramic insulating ring, and no problem of poor airtightness occurred. Also in this case, since the metal plate 20 having a thermal expansion coefficient intermediate between that of ceramics and copper is interposed between the insulating ring 16 of ceramics and the lower drawing plate 17 of copper, distortion due to the difference in shrinkage is reduced, and It is considered that no pulling or pulling occurs.

Therefore, according to the above method, the insulating ring 16
And the lower copper electrode 18 can be minimized. Table 1 shows the coefficients of thermal expansion of the Fe-42% Ni alloy, Kovar, iron, and copper and alumina ceramics for comparison, at 20 to 800 ° C.

[0022]

[Table 1] Example 2 In the same manner as in Example 1, a square insulating ring made of a square alumina ceramic having an outer shape of 120 × 90 mm and a height of 16 mm, on which a strong metal layer was formed, and a Kovar square annular metal plate 3
0, further, brazing with a copper lower drawing plate having a drawing structure, brazing the lower drawing plate with a lower copper electrode having an outer shape of 100 × 70 mm and a height of 6 mm, and the other end surface of the square insulating ring. Brazing with a Kovar weld plate was performed simultaneously.

Further, the upper copper electrode, the upper diaphragm plate, and the welded plate of Kovar were brazed using silver brazing. An IGBT chip is placed on the lower copper electrode 18 to which the insulating ring has been brazed, and the outer periphery of the weld plate is welded over the upper electrode to which the weld plate has been brazed. Thereafter, the inside of the package was gas-replaced from a replacement pipe (not shown), and finally the replacement pipe was closed and sealed.

Also in the IGBT package described above, the warpage of the lower copper electrode was so small that it did not matter. Conventionally, in the case of a rectangular ceramic package, cracks or pulls were noticeably formed at the corners of the lower drawing plate.
However, in the method of the present embodiment, there was no crack, pulling or the like of the lower diaphragm plate, and there was no poor airtightness. As the metal material sandwiched between the ceramics and the metal member to be brazed, iron having a thermal expansion coefficient of 16 × 10 ⁻⁶ ° C. ^-1 is also effective, in addition to the Fe-42% Ni alloy and Kovar. there were.

According to the above-mentioned method, a highly reliable flat semiconductor device which is large, does not give a distortion to the copper electrode, has good airtightness, and is highly reliable.

[0026]

As described above, according to the present invention, a copper drawing plate is used, and a metal having a coefficient of thermal expansion between copper and ceramic is placed between the drawing plate and the insulating ring of ceramic. By forming a flat package brazed with a plate interposed therebetween, distortion due to a difference in thermal expansion coefficient between the copper electrode and the copper diaphragm plate does not occur. In addition, distortion due to a difference in thermal expansion coefficient between the copper diaphragm plate and the insulating ring is reduced by the intermediate metal plate.
Further, the copper diaphragm is highly ductile and absorbs distortion due to the difference in thermal expansion coefficient between the copper diaphragm and the insulating ring, and does not transmit to the copper electrode.

As a result, the following effects can be obtained. The warpage of the copper electrode is reduced, the uniform pressurization of the copper electrode and the semiconductor element becomes possible, and the heat radiation performance is improved, and the reliability is improved. The secondary electrode surface processing becomes unnecessary. Since there is no cracking or pulling of the aperture plate, the airtightness of the package is improved. A copper electrode structure larger than the inner diameter of the insulating ring can be obtained.

That is, through these effects, the present invention contributes to further enlargement and high reliability of the power semiconductor device.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a flat semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a conventional flat semiconductor package.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 11 Upper copper electrode 2, 12 Upper drawing plate 3, 13 Upper welding plate 4, 14 Positioning guide 5, 15 Lower welding plate 6, 16 Insulating ring 7, 17 Lower drawing plate 8, 18 Lower copper electrode 9, 19 Semiconductor Element 10 Flat package 20 Metal plate

Claims (4)

(57) [Claims] 1. A flat semiconductor device enclosed in a flat package in which a diaphragm plate at the peripheral edge of a copper electrode is brazed to an insulating ring of ceramics, wherein the diaphragm plate made of copper has a larger thermal expansion coefficient than that of ceramics. A flat semiconductor element, which is integrally brazed to an end face of an insulating ring with a metal plate smaller than an aperture plate to be brazed interposed therebetween. 2. The thermal expansion coefficient of a metal plate is 8 × 10 ^{-6 to} 20 ×.
The flat semiconductor device according to claim ¹ , wherein the temperature is 10 ^-6 ° C ^-1 . 3. The flat semiconductor device according to claim 1, wherein the metal plate is made of any one of a 42% Ni—Fe alloy, Kovar, and iron. 4. The flat semiconductor device according to claim 1, wherein the insulating ring is a square ring.