JP3351100B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as a semiconductor pressure sensor.

[0002]

2. Description of the Related Art In recent years, when a diaphragm is formed in a semiconductor pressure sensor, an electrochemical stop etching technique for automatically stopping the etching when the thickness of the diaphragm reaches a predetermined thickness has been used (for example, Japanese Unexamined Patent Publication No. JP-A-4-239185, JP-B-4-50736). This technique will be described in detail with reference to FIGS. FIG. 36 is a plan view of the silicon wafer 100 before the electrochemical etching is performed, and FIG.
It is A sectional drawing. An N-type epitaxial layer 102 is formed on a P-type silicon substrate 101 and includes a diaphragm forming region 103 and a peripheral circuit region 104. The N-type epitaxial layer 102 in the diaphragm formation region 103 includes four P-type impurity diffusion regions (piezoresistive layers) 105,
106, 107 and 108 are formed. The P-type impurity diffusion regions (piezoresistive layers) 105, 106, and 10
7, 108 are bridged as shown in FIG.
The voltage Vcc is applied to the first connection terminal a, the ground potential is applied to the second connection terminal b, and the third and fourth connection terminals c and d are output Vout via the amplifier OP1. ing. This amplifier OP1 is formed in the peripheral circuit region 104 in FIG. 37, and the amplifier OP1 is configured by elements such as an NPN transistor 109, and each element is separated by a PN junction. On the surface of the silicon wafer 100, an aluminum wiring 110 for ground potential for obtaining the ground potential at the PN junction and for obtaining the ground potential of the bridge in FIG. 38 is extended near the scribe line. Further, since it is necessary to supply a voltage from the outside for etching the P-type silicon substrate 101, the aluminum wiring 11 for etching is placed on the scribe line.
The aluminum wiring 111 extends from the aluminum wiring 111.
Reference numeral 12 extends to the N-type epitaxial layer 102 in the diaphragm formation region 103. Then, at the time of electrochemical etching, such a silicon wafer 100 is immersed in an etching solution, and aluminum wirings 111 and 112 are formed.
To remove the P-type silicon substrate 101 in the diaphragm formation region 103 to form a diaphragm.

[0003]

However, the aluminum wiring 1
Since the formation of the layers 10, 111, 112 was performed by forming an aluminum film on the entire surface of the silicon wafer 100 and performing photo-etching simultaneously using one mask, photo defects were generated when the aluminum wirings 110, 111, 112 were etched. If there is (for example, a defect due to a mask flaw or particle), the aluminum wiring 11 for the ground potential is often caused by an aluminum short-circuit due to the aluminum 113 shown in FIGS.
0 and the aluminum wiring 111 for etching are short-circuited. Then, at the time of electrochemical etching, the aluminum wiring 11 for ground potential is replaced with the aluminum wiring 11 for ground potential.
0, a leak current was generated on the P-type silicon substrate 101 side. Due to the generation of the leakage current, the potential of the P-type silicon substrate 101 rises, and the etching stops halfway, so that a desired diaphragm thickness cannot be obtained. That is, as shown in FIG. 39, when no short circuit occurs during electrochemical etching, the applied voltage Vcc drops sharply at the PN junction, and the PN junction has the minimum etching potential Vth. Etching stops. However, when a short circuit occurs, the P-type silicon substrate 10
1, and gradually decreases to the minimum etching potential Vth.
In the thickness direction of the P-type silicon substrate 101, and the etching stops at a portion corresponding to the etching minimum potential Vth, so that a desired diaphragm thickness cannot be obtained.

It is an object of the present invention to manufacture a semiconductor device which can prevent a leakage current from flowing from a conductor for electrochemical etching to a P-type silicon substrate and can reliably form a thin portion having a predetermined thickness. It is to provide a method.

[0005]

According to the first aspect of the present invention, an N-type silicon layer is formed on a P-type silicon substrate,
A semiconductor having a thin portion formed by removing the P-type silicon substrate and extending a metal wiring for substrate connection electrically connected to the P-type silicon substrate on a surface of the N-type silicon layer. A method of manufacturing a device, comprising: a first step of forming a metal wiring material on an entire surface of a silicon wafer having an N-type silicon layer formed on a P-type silicon substrate; and forming one mask on the metal wiring material. A second step of simultaneously performing photoetching while leaving the metal wiring for substrate connection and the metal wiring for electrochemical etching electrically connected to the N-type silicon layer by using the metal wiring for substrate connection and the metal wiring for electrochemical etching Forming a resist pattern with an opening between the third step and performing photoetching in the opening, and supplying a voltage to the metal wiring for electrochemical etching Electrochemically etching the P-type silicon substrate as its gist the method of manufacturing a semiconductor device and a fourth step of forming a thin portion by the.

According to a second aspect of the present invention, an N-type silicon layer is formed on a P-type silicon substrate, the thin-film portion formed by removing the P-type silicon substrate, and the N-type silicon layer is formed. A method for manufacturing a semiconductor device, comprising: a substrate connecting metal wiring electrically connected to the P-type silicon substrate on a surface of the semiconductor device, wherein the N-type silicon layer is formed on the P-type silicon substrate. A first step of forming the substrate connection metal wiring thereon; and a second step of forming a passivation film on the silicon wafer.
A third step of forming an electrochemical etching conductor electrically connected to the N-type silicon layer on the passivation film; and supplying a voltage to the electrochemical etching conductor to electrochemically convert the P-type silicon substrate. The gist is a method of manufacturing a semiconductor device including a fourth step of forming a thin portion by etching.

According to a third aspect of the present invention, in the second aspect, the second step is to form a passivation film so as to cover the entire surface of the metal wiring for substrate connection. A gist of the present invention is a method of manufacturing a semiconductor device including a process of exposing a pad portion of a metal wiring for substrate connection after electrochemical etching.

According to a fourth aspect of the present invention, in the second aspect of the present invention, the second step forms a passivation film so as to cover the entire surface of the metal wiring for substrate connection. A gist of the present invention is a method of manufacturing a semiconductor device including a process of opening a conductor for electrochemical etching and a passivation film in a pad portion of a metal wiring for substrate connection.

According to a fifth aspect of the present invention, in the second aspect of the present invention, the second step includes forming a passivation film so that a pad portion of the metal wiring for substrate connection is exposed. A gist of the present invention is a method of manufacturing a semiconductor device, in which the process includes a process of forming an insulating isolation opening around a conductor for electrochemical etching in a pad portion of a metal wiring for substrate connection.

[0010]

According to the first aspect of the present invention, a metal wiring material is formed on the entire surface of a silicon wafer having an N-type silicon layer formed on a P-type silicon substrate in a first step, and a metal wiring material is formed in a second step. In contrast, using a single mask, photo-etching is performed simultaneously while leaving the metal wiring for substrate connection and the metal wiring for electrochemical etching electrically connected to the N-type silicon layer. Then, after a resist pattern having an opening between the metal wiring for substrate connection and the metal wiring for electrochemical etching is formed in the third step, photoetching is performed in the opening. Therefore, the metal wiring for substrate connection and the metal wiring for electrochemical etching are not electrically connected. Thereafter, in the fourth step, a voltage is supplied to the metal wiring for electrochemical etching to electrochemically etch the P-type silicon substrate to form a thin portion. In this electrochemical etching, a short circuit between the metal wiring for substrate connection and the metal wiring for electrochemical etching is avoided, and no leak current is generated from the metal wiring for electrochemical etching to the P-type silicon substrate side.

According to a second aspect of the present invention, a metal wiring for substrate connection is formed on a silicon wafer having an N-type silicon layer formed on a P-type silicon substrate in a first step, and a silicon wiring is formed on a silicon wafer in a second step. Then, a passivation film is formed. In the third step, an electrochemical etching conductor electrically connected to the N-type silicon layer is formed on the passivation film. In the fourth step, a voltage is supplied to the electrochemical etching conductor to electrochemically etch the P-type silicon substrate. As a result, a thin portion is formed. In this electrochemical etching, since the conductor for electrochemical etching is formed on the passivation film, no leak current is generated from the conductor for electrochemical etching to the P-type silicon substrate side.

According to a third aspect of the present invention, in addition to the function of the second aspect, a passivation film is formed so as to cover the entire surface of the substrate-connecting metal wiring in the second step, and an electric power is formed in the fourth step. After the chemical etching, the pad portion of the metal wiring for substrate connection is exposed. Therefore, at the time of electrochemical etching, since the passivation film is formed so as to cover the entire surface of the metal wiring for substrate connection, there is no danger of contact between the electrode to be brought into contact with the conductor for electrochemical etching and the metal wiring for substrate connection. , The electrodes can be placed anywhere.

According to a fourth aspect of the present invention, in addition to the function of the second aspect, a passivation film is formed so as to cover the entire surface of the metal wiring for substrate connection in the second step, and the substrate is formed in the third step. An opening is formed in the conductor for electrochemical etching and the passivation film in the pad portion of the metal wiring for connection. Therefore, it is not necessary to remove the conductor for electrochemical etching and the passivation film in the pad portion of the metal wiring for substrate connection after electrochemical etching.

According to a fifth aspect of the present invention, in addition to the function of the second aspect, in the second step, a passivation film is formed so as to expose a pad portion of the metal wiring for substrate connection. In (2), an insulating isolation opening is formed around the electrochemical etching conductor in the pad portion of the substrate connecting metal wiring. Therefore, it is not necessary to remove the conductor for electrochemical etching and the passivation film in the pad portion of the metal wiring for substrate connection after electrochemical etching.

[0015]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

A method for manufacturing a semiconductor pressure sensor according to the present embodiment will be described with reference to FIGS. FIG. 1 is a plan view of the silicon wafer 1 before electrochemical etching is performed, and FIG.
Shows a BB cross section of FIG.

An N-type epitaxial layer 3 as an N-type silicon layer is formed on a P-type silicon substrate 2. A large number of chip forming regions 4 are formed on the silicon wafer 1. In each of the chip forming regions 4, a diaphragm forming region 5 is formed at a central portion thereof, and a peripheral circuit region 6 is formed at a peripheral portion thereof. Four P-type impurity diffusion regions (piezoresistive layers) 7, 8, and 4 are provided on the surface of the N-type epitaxial layer 3 in the diaphragm formation region 5.
9 and 10 are formed, and these four P-type impurity diffusion regions (piezoresistive layers) 7, 8, 9 and 10 are connected in full bridge as shown in FIG. In FIG. 3, the voltage Vcc is applied to the first connection terminal a of the bridge circuit, the ground potential is applied to the second connection terminal b, and the third and fourth connection terminals c and d are connected via the amplifier OP1. Output Vout.

In the peripheral circuit area 6 of FIG. 2, the amplifier O of FIG.
An NPN transistor 11 for forming P1 is formed. That is, a P-type base region 12 is formed in the N-type epitaxial layer 3, an N-type emitter region 13 is formed in the P-type base region 12, and an N-type collector region 14 is formed in the N-type epitaxial layer 3. Is formed. Further, an N ⁺ buried layer 15 is formed. A P-type region 16 is formed in the N-type epitaxial layer 3 around the NPN transistor 11, and the NPN transistor 11 is insulated and separated by a PN junction.

An N-type impurity region 17 for applying an etching voltage is formed in the N-type epitaxial layer 3 in the diaphragm forming region 5. An N-type impurity region 19 for applying an etching voltage extends in the N-type epitaxial layer 3 on the scribe line 18.

The surface of the N-type epitaxial layer 3 is covered with a silicon oxide film 20, and has a contact opening 21 for the P-type base region 12, a contact opening 22 for the N-type emitter region 13, and an N-type collector region. 14, N-type impurity region 1 for etching voltage application
7, a contact opening 25 to the P-type region 16, a contact opening 26 to the etching voltage application N-type impurity region 19, a P-type impurity diffusion region (piezoresistive layer) 7, Openings 27 for contacts to 8, 9, and 10 are formed.

Then, as shown in FIG. 4, an aluminum film 28 as a metal wiring material is formed on the entire surface of the silicon wafer 1 as shown in FIG. Further, the aluminum film 28 is etched using an aluminum wiring photomask (for positive) 29 shown in FIG. As a result, as shown in FIGS. 6 and 7, the peripheral circuit aluminum wiring 30, the peripheral circuit aluminum wiring (substrate connecting metal wiring) 31, the bridge circuit aluminum wiring 32, and the electrochemical etching aluminum wiring (electrochemical etching) Metal wiring) 33 and the aluminum wiring 34 for electrochemical etching remain. Here, the aluminum wiring 30 for the peripheral circuit corresponds to the transistor 11 in the peripheral circuit region 6.
The aluminum wiring 32 for the bridge circuit is a wiring for forming the bridge circuit of FIG. Further, the aluminum wiring 31 for the peripheral circuit is an aluminum wiring for the ground potential extending close to the scribe line in the chip forming region, and is electrically connected to the P-type region 16 and reduces the ground potential of the bridge circuit of FIG. It is for taking. Further, the aluminum wiring 33 for electrochemical etching is an aluminum wiring extending over the scribe line, and the aluminum wiring 34 for electrochemical etching is a wiring extending from the aluminum wiring 33 to the N-type impurity region 17 for applying an etching voltage.

Further, a short material removing mask (for positive) 35 shown in FIG. 8 is prepared. The short material removing mask (positive) 35 has an opening between the peripheral circuit aluminum wiring 31 and the electrochemical etching aluminum wiring 33. Using the short material removing mask 35, the resist 36 is patterned as shown in FIG. In this resist pattern, an opening 37 is formed between the peripheral circuit aluminum wiring 31 and the electrochemical etching aluminum wiring 33.

Then, photo-etching is performed using the resist pattern. By this photo-etching, the aluminum wiring 31 for the peripheral circuit and the aluminum wiring 33 for the electrochemical etching are formed.
And are completely separated. That is, in FIG. 7, the aluminum wiring 31 for the peripheral circuit and the aluminum wiring 3 for the electrochemical etching are used.
Even if the short-forming aluminum 38 exists between the first and third aluminum alloys 3 (even if the short-forming aluminum 38 exists in FIG. 10), the short-forming aluminum 38 is removed.

Thereafter, as shown in FIG. 11, a passivation film 39 is formed on the entire surface of the silicon wafer 1. As the passivation film 39, a silicon nitride film, a silicon oxide film, or a laminate of a silicon nitride film and a silicon oxide film is used. Further, in FIG. 7, the aluminum pad 40 for applying the voltage Vcc, the aluminum pad 41 for the ground potential, and the aluminum pad 42 for the output in FIG. 3 are formed, and as shown in FIG. An opening 43 is formed by etching the passivation film 39. At the same time, the passivation film 39 in the pad portion (not shown) of the aluminum wiring 33 for electrochemical etching on the silicon wafer 1 is etched.

Then, as shown in FIG. 13, electrochemical etching is performed. That is, N in the silicon wafer 1
A mask material 44 is formed on a surface where the type epitaxial layer 3 is not formed, in a region where a diaphragm is not formed. Further, the platinum electrode 45 is interposed between the silicon wafer 1 and fixed to a ceramic supporting substrate 46. The surface of the silicon wafer 1 where the etching is not performed (the surface on which the N-type epitaxial layer 3 is formed) is protected by the wax 47. The platinum electrode 45 is electrically connected to the aluminum wiring 33 for electrochemical etching. Container 4
8 is filled with a KOH aqueous solution (33 wt%, 82 ° C.) 49. The silicon wafer 1 described above is immersed in a KOH aqueous solution 49 in a container 48, and a platinum electrode 50 is arranged so as to face the silicon wafer 1. And
A constant voltage power supply (2 volt) 51 is connected between the platinum electrode 45 and the platinum electrode 50 of the silicon
A constant voltage is applied between 5, 50. Then, the P-type silicon substrate 2 is electrochemically etched, and the etching is stopped near the junction with the N-type epitaxial layer 3.
As a result, as shown in FIG. 14, a diaphragm (thin portion) 52 is formed in the diaphragm formation region 5.

Then, the silicon wafer 1 is diced on a scribe line and cut into chips. As described above, in the present embodiment, the N-type epitaxial layer 3 is formed on the P-type silicon substrate 2, and the diaphragm 52 is formed by removing the P-type silicon substrate 2. A method of manufacturing a semiconductor pressure sensor in which an aluminum wiring 31 for a peripheral circuit electrically connected to a P-type silicon substrate 2 on the surface is provided, wherein the N-type epitaxial layer 3 is formed on the P-type silicon substrate 2.
Aluminum film 28 is formed on the entire surface of silicon wafer 1 on which
Is formed (first step), and the aluminum wiring 31 for the peripheral circuit and the aluminum wiring 33 for electrochemical etching electrically connected to the N-type epitaxial layer 3 are left on the aluminum film 28 using one mask 29. At the same time (second step). Then, after forming a resist pattern in which an opening is formed between the aluminum wiring 31 for the peripheral circuit and the aluminum wiring 33 for electrochemical etching, photo-etching is performed in the opening 37 (third step). Therefore, the aluminum wiring for peripheral circuit 31 and the aluminum wiring for electrochemical etching 33 are not electrically connected. Further, by supplying a voltage to the aluminum wiring 33 for electrochemical etching, P
The mold 52 was electrochemically etched to form the diaphragm 52 (fourth step). In this electrochemical etching, a short circuit between the aluminum wiring for peripheral circuit 31 and the aluminum wiring for electrochemical etching 33 is avoided, and the aluminum wiring for electrochemical etching 33 and the aluminum wiring for peripheral circuit 31 pass through the P-type silicon substrate 2 side. No leakage current to As a result, the diaphragm 52 having a predetermined thickness is reliably formed.

That is, in the conventional wafer process, a passivation film is deposited after an aluminum wiring is formed by photo-etching an aluminum wiring material, and the passivation film in the bonding pad portion is removed.
If it is found that the peripheral circuit aluminum wiring 31 and the electrochemical etching aluminum wiring 33 are short-circuited after depositing the passivation film, the wafer cannot be used. In addition, if a short circuit is found before the passivation film is deposited, if the photo-etching step of the aluminum wiring material is performed again, the width of the aluminum wiring may be reduced and the aluminum wiring may be disconnected. Furthermore, if a short circuit is found before the passivation film is deposited, short circuit may occur again even if the aluminum is entirely removed, an aluminum wiring material is formed on the entire surface, and the aluminum wiring is photo-etched. On the other hand, since the aluminum wiring material was photo-etched as in the present embodiment, a resist pattern having an opening between the peripheral circuit aluminum wiring 31 and the electrochemical etching aluminum wiring 33 was formed, and aluminum etching was performed. There is no possibility that the aluminum wiring 31 for the peripheral circuit and the aluminum wiring 33 for electrochemical etching are short-circuited, and stable electrochemical etching can be performed. (Second Embodiment) Next, a second embodiment will be described focusing on differences from the first embodiment.

A method of manufacturing the semiconductor pressure sensor according to the present embodiment will be described with reference to FIGS. FIG. 15 is a plan view of the silicon wafer 1 before the electrochemical etching is performed.
16 shows a cross section taken along the line CC of FIG. 15, and FIG. 17 shows a cross section taken along the line DD of FIG.

An N-type epitaxial layer 3 is formed on a P-type silicon substrate 2. In each chip forming region 4 of the silicon wafer 1, a diaphragm forming region 5 is formed at a central portion thereof, and a peripheral circuit region 6 is formed at a peripheral portion thereof. Four P-type impurity diffusion regions (piezoresistive layers) 7, 8, 9, and 10 are formed on the surface of the N-type epitaxial layer 3 in the diaphragm formation region 5, and these four P-type impurity diffusion regions 7, 8, and 10 are formed. 9,10
Are connected in full bridge as shown in FIG. Further, the peripheral circuit area 6 has N for configuring the amplifier OP1 of FIG.
A PN transistor 11 is formed. That is, a P-type base region 12 is formed in the N-type epitaxial layer 3 and an N-type emitter region 13 is formed in the P-type base region 12.
Is formed, and an N-type collector region 14 is formed in the N-type epitaxial layer 3. Further, an N ⁺ buried layer 15 is formed. This NPN transistor 11
N-type epitaxial layer 3 around P-type region 1
6 are formed, and an NPN transistor 11 is formed by a PN junction.
Are insulated and separated.

In the N-type epitaxial layer 3 in the diaphragm forming region 5, an N-type impurity region 17 for applying an etching voltage is formed. The surface of N-type epitaxial layer 3 is covered with silicon oxide film 20. P-type base region 12, N-type emitter region 13, N-type collector region 1
4 is electrically connected by an aluminum wiring 30 for peripheral circuits. The P-type region 16 is electrically connected to a peripheral circuit aluminum wiring 31 serving as a substrate connection metal wiring, and the aluminum wiring 31 extends as shown in FIG. The P-type impurity diffusion regions 7, 8, 9, 10 are electrically connected by an aluminum wiring 32 for a bridge circuit. Further, an aluminum wiring 53 for electrochemical etching is formed in the N-type impurity region 17 for applying an etching voltage, and the aluminum wiring 53 for electrochemical etching extends outside the diaphragm forming region 5 to form an aluminum pad 54. In FIG. 15, aluminum pad 55 for applying voltage Vcc, aluminum pad 56 for ground potential, and aluminum pad 57 for output in FIG.
Are formed. Aluminum pad 56 for ground potential
Is for connecting to the aluminum wiring 31 for the peripheral circuit and for taking the ground potential of the bridge circuit of FIG.

Then, a passivation film 58 is formed on the entire surface of the silicon wafer 1 as shown in FIGS. As the passivation film 58, a silicon nitride film, a silicon oxide film, or a laminate of a silicon nitride film and a silicon oxide film is used.

Then, as shown in FIG. 20, the passivation film 58 on the aluminum pad 54 is etched to form an opening 59. Subsequently, as shown in FIG.
An aluminum film (electrochemical etching conductor) 60 is formed on the entire surface of the silicon wafer 1.

Next, electrochemical etching is performed as shown in FIG. That is, on the surface of the silicon wafer 1 where the N-type epitaxial layer 3 is not provided, the mask material 44 is formed in a region where the diaphragm is not formed. Further, the platinum electrode 45 is interposed between the silicon wafer 1 and fixed to a ceramic supporting substrate 46. The surface of the silicon wafer 1 where the etching is not performed (the surface on which the N-type epitaxial layer 3 is formed) is wax 4
Protect with 7. The platinum electrode 45 is electrically connected to the aluminum film 60. The container 48 contains a KOH aqueous solution (33
wt%, 82 ° C.) 49 is satisfied. The silicon wafer 1 described above is immersed in a KOH aqueous solution 49 in a container 48, and a platinum electrode 50 is arranged so as to face the silicon wafer 1. A constant voltage power supply (2 volts) is applied between the platinum electrode 45 and the platinum electrode 50 of the silicon wafer 1.
51 is connected to apply a constant voltage between the electrodes 45 and 50. Then, the P-type silicon substrate 2 is electrochemically etched, and the etching is stopped near the junction with the N-type epitaxial layer 3. As a result, as shown in FIG. 23, a diaphragm (thin portion) 61 is formed in the diaphragm formation region 5.

Subsequently, as shown in FIG. 24, the aluminum film 60 is removed over the entire surface. Thereafter, as shown in FIG. 25, the opening 62 is formed by etching the passivation film 58 on the aluminum pads 55, 56, 57.

Then, the silicon wafer 1 is diced on a scribe line and cut into chips. As described above, in the present embodiment, the N-type epitaxial layer 3 is formed on the P-type silicon substrate 2, and the diaphragm 61 is formed by removing the P-type silicon substrate 2. A method of manufacturing a semiconductor pressure sensor in which an aluminum wiring 31 for a peripheral circuit electrically connected to a P-type silicon substrate 2 on the surface is provided, wherein the N-type epitaxial layer 3 is formed on the P-type silicon substrate 2.
Is formed on silicon wafer 1 on which is formed (first step), passivation film 58 is formed on silicon wafer 1 (second step), and N-type epitaxial layer is formed on passivation film 58. An aluminum film 60 electrically connected to the third film 3 is formed (third step).
By applying a voltage to 0, the P-type silicon substrate 2 was electrochemically etched to form a diaphragm 61 (fourth step). At the time of this electrochemical etching, since the aluminum film 60 is formed on the passivation film 58,
No leak current is generated from the aluminum film 60 to the P-type silicon substrate 2 side. As a result, the diaphragm 61 having a predetermined thickness is reliably formed.

In the second step, a passivation film 58 is formed so as to cover the entire surface of the peripheral circuit aluminum wiring 31, and in the fourth step, after electrochemical etching, the aluminum pad 56 of the peripheral circuit aluminum wiring 31 is exposed. did. Therefore, at the time of the electrochemical etching, the passivation film 58 is formed so as to cover the entire surface of the aluminum wiring 31 for the peripheral circuit.
Is formed, there is no danger that the platinum electrode 45 to be brought into contact with the aluminum film 60 and the aluminum wiring 31 for the peripheral circuit will come into contact with each other, and the platinum electrode 45 can be arranged at an arbitrary place, thus improving workability.

Further, at the time of electrochemical etching, FIG.
As shown in FIG. 6, when an etching wiring pattern 114 is formed on the outer periphery of the wafer 1 and the etching wiring pattern 114 is connected to the etching platinum electrode 115 to perform electrochemical etching, scratches due to handling, etc. Accordingly, the wiring pattern 114 for etching and the P-type silicon substrate 2 are short-circuited by the conductor 116. On the other hand, by forming the aluminum film 60 on the passivation film 58 and performing the electrochemical etching as in the present embodiment, the leakage between the etching wiring and the P-type silicon substrate at the outer periphery of the wafer 1 is performed. Can be prevented.

Conventionally, it is necessary to dispose an etching wiring material on the scribe line or on the outer periphery of the wafer in order to perform electrochemical etching, or to make contact impurities (etching in FIG. 11) on the scribe line or on the outer periphery of the wafer. Although it is necessary to appropriately dispose the voltage application N-type impurity region 19), in the present embodiment, it is not necessary to devise such a device on the scribe line or the outer peripheral portion of the wafer.

The conductor for electrochemical etching disposed on the passivation film 58 is not limited to the aluminum film 60,
Other conductor materials may be used. (Third Embodiment) Next, a third embodiment will be described focusing on differences from the second embodiment.

A method of manufacturing the semiconductor pressure sensor according to the present embodiment will be described with reference to FIGS. The opening 63 is formed by etching the passivation film 58 on the aluminum pad 54 from the state shown in FIGS. 18 and 19 in the second embodiment, as shown in FIG. Subsequently, as shown in FIG. 28, an aluminum film (electrochemical etching conductor) 64 is formed on the entire surface of the silicon wafer 1.

Then, as shown in FIG. 29, an opening 65 is formed by etching the aluminum film 64 above the aluminum pads 55, 56, 57. At the same time, the aluminum film 64 in the diaphragm formation region is removed. Further, as shown in FIG. 30, the opening 66 is formed by etching the passivation film 58 on the aluminum pads 55, 56, 57.

Next, electrochemical etching is performed as shown in FIG. Then, the silicon wafer 1 is diced on a scribe line and cut into chips.

As a result, the semiconductor pressure sensor shown in FIG. 31 is manufactured. In this semiconductor pressure sensor, a passivation film 58 is formed on the upper surface of the silicon wafer 1, and an aluminum film 64 is formed thereon.

As described above, in the present embodiment, in the passivation film forming step (the second step in the second embodiment), the passivation film 58 is formed so as to cover the entire surface of the aluminum wiring 31 for the peripheral circuit. In the conductor forming step (third step in the second embodiment), the aluminum film 64 and the passivation film 58 in the aluminum pad 56 for ground potential (pad of the metal wiring for substrate connection) were opened. Therefore, it is not necessary to remove the aluminum film 64 and the passivation film 58 in the pad portion for the ground potential after the electrochemical etching as compared with the second embodiment. (Fourth Embodiment) Next, a fourth embodiment will be described focusing on differences from the second embodiment.

A method of manufacturing the semiconductor pressure sensor according to the present embodiment will be described with reference to FIGS. As shown in FIG. 32, the openings 67 and 68 are formed by etching the passivation film 58 on the aluminum pads 54, 55, 56 and 57 from the state shown in FIGS. Subsequently, as shown in FIG. 33, an aluminum film (electrochemical etching conductor) 69 is formed on the entire surface of the silicon wafer 1.

Then, as shown in FIG. 34, the periphery of the aluminum film 69 on the aluminum pads 55, 56, 57 is etched to form a groove 70 as an insulating isolation opening in a ring shape over the entire circumference. At the same time, the aluminum film 69 in the diaphragm formation region is removed.

Next, electrochemical etching is performed as shown in FIG. Then, the silicon wafer 1 is diced on a scribe line and cut into chips.

As a result, the semiconductor pressure sensor shown in FIG. 35 is manufactured. In this semiconductor pressure sensor, a passivation film 58 is formed on the upper surface of the silicon wafer 1, and an aluminum film 69 is formed thereon.

As described above, in this embodiment, in the passivation film forming step (the second step in the second embodiment), the passivation film is exposed such that the ground potential aluminum pad 56 (pad of the metal wiring for substrate connection) is exposed. 58, and a ground potential aluminum pad 5 is formed in the step of forming a conductor for electrochemical etching (the third step in the second embodiment).
A groove 70 was formed around the aluminum film 69 in the portion 6 (pad of the metal wiring for substrate connection). Therefore, it is not necessary to remove the aluminum film 69 and the passivation film 58 in the pad portion for the ground potential after the electrochemical etching as compared with the second embodiment.

The present invention is not limited to the above embodiments. For example, in the above embodiments, the case where the diaphragm of the semiconductor pressure sensor is formed has been described.
It can be used when a thin portion (beam portion) of a semiconductor acceleration sensor is formed.

The etching solution is not limited to a KOH aqueous solution, but may be a tetramethylammonium hydroxide aqueous solution (T
MAH: (CH ₃ ) ₄ NOH), another alkali anisotropic etching solution such as ethylenediamine, or an isotropic etching solution such as hydrofluoric acid.

[0052]

As described above in detail, according to the first aspect of the present invention, it is possible to prevent the occurrence of a leak current from the metal wiring for electrochemical etching to the P-type silicon substrate side and to surely achieve the predetermined thickness. It has an excellent effect of forming a thin portion.

According to the second aspect of the present invention, it is possible to prevent a leakage current from flowing from the conductor for electrochemical etching to the P-type silicon substrate side and to reliably form a thin portion having a predetermined thickness.

According to the invention described in claim 3, according to claim 2
In addition to the effects of the invention described in (1), an electrode to be brought into contact with the conductor for electrochemical etching can be arranged at an arbitrary position. Claim 4
According to the invention described in (1), in addition to the effect of the invention described in claim 2, the step of removing the conductor for electrochemical etching and the passivation film after the electrochemical etching can be omitted.

According to the invention described in claim 5, according to claim 2,
In addition to the effects of the invention described in (1), the step of removing the conductor for electrochemical etching and the passivation film after the electrochemical etching can be eliminated.

[Brief description of the drawings]

FIG. 1 is a plan view of a silicon wafer when manufacturing a semiconductor pressure sensor according to a first embodiment.

FIG. 2 is a sectional view taken along line BB of FIG.

FIG. 3 is an electric circuit diagram of the semiconductor pressure sensor.

FIG. 4 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the first embodiment.

FIG. 5 is a plan view showing a photomask.

FIG. 6 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the first embodiment.

FIG. 7 is a plan view for explaining a manufacturing process of the semiconductor pressure sensor according to the first embodiment.

FIG. 8 is a plan view showing a short material removing mask.

FIG. 9 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the first embodiment.

FIG. 10 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the first embodiment.

FIG. 11 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the first embodiment.

FIG. 12 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the first embodiment.

FIG. 13 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the first embodiment.

FIG. 14 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the first embodiment.

FIG. 15 is a plan view of a silicon wafer when manufacturing the semiconductor pressure sensor of the second embodiment.

16 is a sectional view taken along the line CC of FIG.

FIG. 17 is a sectional view taken along the line CC of FIG. 15;

FIG. 18 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the second embodiment.

FIG. 19 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the second embodiment.

FIG. 20 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the second embodiment.

FIG. 21 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the second embodiment.

FIG. 22 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the second embodiment.

FIG. 23 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the second embodiment.

FIG. 24 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the second embodiment.

FIG. 25 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the second embodiment.

FIG. 26 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the second embodiment.

FIG. 27 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the third embodiment.

FIG. 28 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the third embodiment.

FIG. 29 is a cross-sectional view for explaining a manufacturing step of the semiconductor pressure sensor according to the third embodiment.

FIG. 30 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the third embodiment.

FIG. 31 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the third embodiment.

FIG. 32 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the fourth embodiment.

FIG. 33 is a cross-sectional view for explaining a manufacturing step of the semiconductor pressure sensor according to the fourth embodiment.

FIG. 34 is a cross-sectional view for explaining a manufacturing step of the semiconductor pressure sensor according to the fourth embodiment.

FIG. 35 is a cross-sectional view for explaining a manufacturing step of the semiconductor pressure sensor according to the fourth embodiment.

FIG. 36 is a plan view of a silicon wafer for explaining a conventional technique.

FIG. 37 is a sectional view taken along line AA of FIG. 34.

FIG. 38 is an electric circuit diagram of the semiconductor pressure sensor.

FIG. 39 is an explanatory diagram for explaining a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon wafer, 2 ... P type silicon substrate, 3 ... N type epitaxial layer, 28 ... Aluminum film, 31 ... Aluminum wiring for peripheral circuits, 33 ... Aluminum wiring for electrochemical etching,
36: resist, 37: opening, 52: diaphragm,
56 ... aluminum pad, 58 ... passivation film, 60
... Aluminum film, 61 ... Diaphragm, 64 ... Aluminum film, 6
5 ... opening, 66 ... opening, 69 ... opening

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-5582 (JP, A) JP-A-6-104245 (JP, A) JP-A-3-74882 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 21/306-21/308

Claims (5)

(57) [Claims] An N-type silicon layer is formed on a P-type silicon substrate. The N-type silicon layer has a thin portion formed by removing the P-type silicon substrate, and the P-type silicon layer is formed on a surface of the N-type silicon layer. A method for manufacturing a semiconductor device in which a metal wiring for substrate connection electrically connected to a substrate is extended, wherein a metal wiring material is provided on the entire surface of a silicon wafer having an N-type silicon layer formed on a P-type silicon substrate. A first step of forming a metal wiring material, and using a single mask for the metal wiring material, simultaneously leaving the metal wiring for substrate connection and the metal wiring for electrochemical etching electrically connected to the N-type silicon layer. A second step of etching, and forming a resist pattern in which an opening is formed between the metal wiring for substrate connection and the metal wiring for electrochemical etching, and then performing photoetching in the opening. Manufacturing a semiconductor device, comprising: performing a third step; and applying a voltage to a metal wiring for electrochemical etching to electrochemically etch the P-type silicon substrate to form a thin portion. Method. 2. An N-type silicon layer is formed on a P-type silicon substrate. The N-type silicon layer has a thin portion formed by removing the P-type silicon substrate, and the P-type silicon layer is formed on a surface of the N-type silicon layer. A method of manufacturing a semiconductor device in which a metal wiring for substrate connection electrically connected to a substrate is extended, wherein the metal for substrate connection is formed on a silicon wafer having an N-type silicon layer formed on a P-type silicon substrate. First to form wiring
A second step of forming a passivation film on the silicon wafer; a third step of forming a conductor for electrochemical etching electrically connected to the N-type silicon layer on the passivation film; And a fourth step of electrochemically etching the P-type silicon substrate to form a thin portion by supplying a voltage to the conductor. 3. The step of forming a passivation film so as to cover the entire surface of the metal wiring for substrate connection, and the step of forming the pad portion of the metal wiring for substrate connection after electrochemical etching. 3. The method of manufacturing a semiconductor device according to claim 2, comprising a process of exposing the semiconductor device. 4. The step of forming a passivation film so as to cover the entire surface of the metal wiring for substrate connection, and the step of forming a third electrode for electrochemical etching at a pad portion of the metal wiring for substrate connection. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising a process of opening a conductor and a passivation film. 5. The step of forming a passivation film such that a pad portion of the metal wiring for substrate connection is exposed, and the step of electrochemically forming the pad portion of the metal wiring for substrate connection in the third step. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising a process of forming an insulating isolation opening around the etching conductor.