JP3343794B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

2. Description of the Related Art There is known a configuration in which a thin film transistor (generally called a TFT) is used for a liquid crystal display device or an image sensor. In particular, a configuration in which a thin film transistor is arranged in each pixel of an active matrix type liquid crystal display device and switching of the pixel is known.

When a thin film transistor is arranged in each pixel of an active matrix type liquid crystal display device, it is necessary that the OFF current of the thin film transistor be as small as possible.
This is because when the thin film transistor is in the OFF operation, it is necessary to hold the electric charge in the pixel for a predetermined time.

As a means for reducing the OFF current of a thin film transistor, there is a method of employing an offset gate structure or an LDD (lightly doped drain) structure. These are intended to reduce the value of the OFF current by relaxing a high electric field applied between the channel formation region and the drain region.

[Procedure leading to the invention] The present inventors have manufactured a thin film transistor whose manufacturing process is shown in FIGS. 2 and 3 as a thin film transistor having a small OFF current value. This thin film transistor has an offset gate region and a low impurity concentration (lightly doped) region (L
(Which functions as a DD area).

[0005] Hereinafter, a manufacturing process of the thin film transistor will be described with reference to FIGS. 2 and 3. First, a glass substrate 101 is prepared, and a silicon oxide film 102 is formed as a base film on the surface of the glass substrate 101 to a thickness of 3000 ° by a sputtering method. Next, an amorphous silicon film is formed to a thickness of 1000 ° by a plasma CVD method or a low pressure thermal CVD method. Further, heat treatment or laser light irradiation is performed to crystallize the amorphous silicon film to obtain a crystalline silicon film. The active layer 103 is obtained by patterning this crystalline silicon film. (Fig. 2 (A))

Then, a silicon oxide film 104 functioning as a gate insulating film is formed to a thickness of 1000 ° by a plasma CVD method or a sputtering method. Further, a film containing aluminum as a main component is formed to a thickness of 5000 ° by a vapor deposition method. Then, a dense oxide layer (dense anodic oxide layer) is formed with a thickness of about 100 ° on the surface of the film containing aluminum as a main component. This dense oxide layer (dense anodic acid
Formation of oxide layer) is achieved by performing the anodic oxidation of aluminum as an anode in ethylene glycol solution containing of 3-10% tartaric acid.

By performing patterning, a shape as shown in FIG. 2B is obtained. In FIG. 2B, 105 is a patterned film containing aluminum as a main component, and 106 is a dense oxide layer (a dense anodic oxide layer) formed on the surface thereof .

Next, the anodic oxidation step is performed again using the patterned film 105 mainly composed of aluminum as an anode, thereby forming a porous oxide layer 107 as shown in FIG. 2C. This porous oxide layer 107
Is about 5000 °. This anodizing step is performed by using a 3 to 20% aqueous solution of nitric acid or citric acid as an electrolytic solution. This anodic oxidation step is performed with the dense oxide layer 106 (dense anodic oxide
) From the side of the aluminum film in the horizontal direction.

Next, a dense oxide layer 106 (dense anodic acid)
Anodization is again performed in the ethylene glycol solution containing 3 to 10% tartaric acid using the remaining aluminum film 100 as an anode. In this step, a dense anodic oxide layer 108 is formed to a thickness of about 2000 °. The region 109 containing aluminum as a main component remaining after this step becomes a gate electrode. Then, the gate electrode 109 and the surrounding dense oxide layer 108 ( compact
Dense anodic oxide layer) and the exposed silicon oxide film 10 using the porous oxide layer 107 on the side surface as a mask.
4 is etched. (FIG. 2 (D))

Then, the anodic oxide (porous anodic oxide layer 107) is etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. Thus, the state shown in FIG.

Next, source regions 110 and drain regions 111 are formed by implanting N-type impurity ions. In this step, regions indicated by 112 and 116 are formed as low impurity concentration regions (N ⁻ type).
The regions indicated by 112 and 116 are formed by partially reducing ions to be implanted due to the remaining silicon oxide film 104. In this step, the dense oxide layer 108 (dense anodic oxide layer) serves as a barrier, and offset gate regions 113 and 115 are formed.

Further, TEOS (tetraethoxysilane)
A silicon oxide film 117 serving as an interlayer insulating film is formed to a thickness of 7000.degree. When a silicon oxide film forming an interlayer insulating film or the like is formed, a plasma CVD method using TEOS as a raw material is often used. This is mainly because there are significant steps such as good step coverage (step coverage) and a high film forming rate at a low temperature.

However, a silicon oxide film formed using TEOS as a raw material has the following disadvantages. (1) Since a large amount of OH groups are present in the film, electrons are trapped in the film. (2) The film contains a large amount of water, which lowers the reliability of the device. Such a problem exists.

The problem (1) causes an operation failure in an N-channel thin film transistor, particularly, a thin film transistor having a structure as shown in FIG. FIG. 4 is an enlarged view of the vicinity of the source region 110 and the low impurity concentration region 112 of the thin film transistor shown in FIG. Silicon oxide film 11 manufactured using TEOS
7 traps many electrons because it contains a large amount of OH groups. In particular, the electrons trapped in the vicinity indicated by 301 induce holes (positive charges) on the surfaces of the source region 110 and the low impurity concentration region 112, and cause light P
Type (P ^- type). As a result, an N-channel thin film transistor using electrons as carriers to be moved between the source and the drain does not operate normally.

As described above, the problem (1) has been a cause of hindering the normal operation of the N-channel thin film transistor. Further, this problem is not limited to TEOS, but becomes apparent when an insulating film having a film quality that easily traps electrons is used in the film.

The problem (2) is the presence of moisture in the device, which causes a reduction in the reliability of the device.

[0017]

SUMMARY OF THE INVENTION An object of the invention disclosed in this specification is to solve at least one of the following items.・ To provide a thin film transistor which is not affected (or hardly affected) by electrons trapped in the interlayer insulating film. -To provide a thin film transistor which is not (or hardly) affected by moisture in an interlayer insulating film. -Stabilize the operation of the thin film transistor by positively utilizing the charge existing in the interlayer insulating film.

[0018]

SUMMARY OF THE INVENTION One of the inventions disclosed in the present specification is an N-type region having a low impurity concentration disposed between a source and / or drain region having an N-type and a channel forming region. An N-type lightly doped region), a gate insulating film is formed on the low impurity concentration N-type region, and an insulating film for trapping positive charges is formed on the gate insulating film. It is characterized by being.

FIG. 1 shows a specific example having the above configuration. In the configuration shown in FIG. 1, an N-type source region 110, the source region 110 and the channel forming region 1 are formed.
14 and an N-type region 112 having a low impurity concentration (N ⁻ type). A gate insulating film 104 is formed on the low impurity concentration N-type region denoted by reference numeral 112. Then, a low impurity concentration N
Above the mold region 112, a silicon nitride film 100 having a property of trapping positive charges is formed.

Source / drain region 1 in the above configuration
The impurity concentration at 10/111 is a typical source /
What is necessary is just to make it the same as the impurity concentration in a drain region.
Further, the impurity concentration in the low impurity concentration region depends on the source /
The concentration may be two to three digits less than the impurity concentration in the drain regions 110/111 . For example, the impurity concentration in the low impurity concentration region is set to 1 × 10
And ^{17 ~2} × 10 ¹⁸ cm ^-3 or so, the impurity concentration in the source / drain region 110/111 may be set to ^{1 × 10 20 ~2 × 10 21} cm -3 about a region of high impurity concentration. As the gate insulating film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a stacked body thereof can be used.

The construction of another invention, a pair of intrinsic region disposed in contact with the channel forming region, and the N-type region of the pair of low impurity concentration which is arranged in contact with the pair of intrinsic region, the A pair of high-impurity-concentration N-type regions disposed in contact with the pair of low-impurity-concentration N-type regions; and a gate on the channel formation region and the pair of low-impurity-concentration N-type regions. An insulating film is provided, and a silicon nitride film is provided on the gate insulating film and the pair of high impurity concentration N-type regions.

FIG. 6C shows a specific example having the above configuration.
Shown in In the structure shown in FIG. 6C, a pair of intrinsic regions 11 arranged in contact with the channel formation region 114 are provided.
3 and 115 and this pair of intrinsic regions 113 and 11
5 and a pair of low impurity concentration N-type regions 1
12 and 116. A pair of intrinsic regions 11
Areas 3 and 115 function as offset gate areas. Also, a pair of low-concentration N-type regions 112 and 1
Reference numeral 16 denotes a region which constitutes an LDD (lightly doped drain).

A pair of low-concentration N-type regions 112 and 1
16 and a pair of high-concentration N-type regions 110 and 11
1 is arranged. This pair of high-concentration N-type regions 11
0 and 111 are the source region 110 and the drain region 1
It is an area that functions as 11 .

A gate insulating film 104 is formed on the pair of low-concentration N-type regions 112 and 116.
On the pair of high-concentration N-type regions 110 and 111,
A silicon nitride film 100 is formed.

According to another aspect of the invention, a step of forming an insulating film on an active layer made of a semiconductor, a step of implanting impurity ions into the active layer through the insulating film, The method includes a step of forming a silicon nitride film and a step of performing heat treatment .

According to another aspect of the present invention, a step of implanting impurity ions into an active layer in which a region to be a source / drain region is exposed, a step of forming a silicon nitride film covering the exposed region, Performing a heat treatment.

As a specific example of the above configuration, a step shown in FIG. 6 can be mentioned. In the step shown in FIG. 6, first, in the step shown in FIG. 6A , impurity ions are implanted in a state where the source region 110 and the drain region 111 are exposed, and thereafter, the exposed source / drain regions 110/1 are exposed.
11 shows a step of forming a silicon nitride film 100 covering the silicon nitride film 11 and further performing a heat treatment.

According to another aspect of the present invention, a step of implanting impurity ions into an active layer in which a region to be a source / drain region is exposed, a step of forming a silicon nitride film covering the exposed region, Performing a heat treatment,
In the step of implanting impurity ions, an insulating film remains on a region of the active layer which is to be a low impurity concentration region.

A specific example of the above-mentioned configuration in which “the insulating film remains in the region of the active layer that is to be a low impurity concentration region in the step of implanting impurity ions” is as follows.
It is shown in FIG. In the step shown in FIG.
In the step of implanting impurity ions, the insulating film 10 is formed on the active layer regions 112 and 116 to be low impurity concentration regions.
4 can be mentioned.

[0030]

As shown in FIG. 6, between the channel forming region 114 and the source / drain regions 110/111,
By providing low impurity concentration regions 112 and 116 and offset gate regions 113 and 115, a low OF
A thin film transistor having F current characteristics can be obtained.

A silicon nitride film having the property of trapping positive charges on the exposed N-type source / drain regions shown by 110 and 111 and above the N-type low impurity regions shown by 112 and 116 By forming
Negative charges can be induced on the surfaces of the source / drain regions 110/111 and the low impurity concentration regions, and the operation of the N-channel thin film transistor can be performed normally.

As a passivation film or an interlayer insulating film on the surface, a silicon oxide film (for example, T
Even when the silicon oxide film 117 made of EOS is formed, the silicon nitride film 100 is provided so as not to be affected or hardly affected by the electrons trapped in the silicon oxide film 117. Can be.

Further, a silicon oxide film 11 made of TEOS as a passivation film or an interlayer insulating film on the surface.
Even when 7 was formed, by providing the silicon nitride film 100 may be a silicon nitride film 100 serves as a barrier, preventing the water contained in the silicon oxide film 117 adversely affect the active layer .

Furthermore, after the formation of the silicon nitride film 100, by heat treatment, hydrogen ions are diffused from in the silicon nitride film 100, the silicon oxide film 104 and the source region 110 damaged during impurity ion implantation And drain region 1
11 can be annealed for defects.

[0035]

[Example 1] FIGS. 5 and 6 show a manufacturing process of this example. First, FIG.
As shown in FIG. 1A, a silicon oxide film 102 is formed as a base film on a glass substrate 101 to a thickness of 3000 ° by a sputtering method or a plasma CVD method. Next, the amorphous silicon film is
A film is formed to a thickness of 00 ° by a plasma CVD method or a low pressure thermal CVD method. Then, a crystalline silicon film is obtained by heating or irradiation with a laser beam. Then, by patterning, an active layer 103 of the thin film transistor is formed. Note that an amorphous silicon film may be used as it is instead of the crystalline silicon film. (FIG. 5 (A))

Next, a silicon oxide film 104 is formed as an interlayer insulating film to a thickness of 1000 ° by a plasma CVD method, a low pressure thermal CVD method or a sputtering method. And 0.18%
Of scandium-containing aluminum is formed to a thickness of 5000 ° by electron beam evaporation. Further, by performing anodization using the aluminum film as an anode in an ethylene glycol solution containing 5% tartaric acid, an extremely thin oxide layer (shown by 106) of about 100 ° is formed on the surface of the aluminum film. Form.

Next, by performing patterning, the film containing aluminum as a main component is patterned into a shape shown by 105. On the surface of the patterned film 105 mainly containing aluminum, the dense oxide layer 106 (dense anodic oxidation ) formed in the previous step is formed.
Material layer) is formed. (FIG. 5 (B))

Next, in a 10% citric acid solution, anodization is performed using the aluminum film 105 as an anode to form a porous oxide layer 107. This porous oxide layer is grown over a length of 6000 °. By controlling the growth distance of the porous oxide layer, the length of the low impurity concentration region formed in the subsequent impurity ion process is determined. (FIG. 5 (C))

Next, the dense oxide layer 106 (dense anodic acid)
Oxide layer) was removed, subjected to anodic oxidation in again for 5% ethylene glycol solution tartrate is included to form a dense oxide layer 108 (dense anodic oxide layer). The region 109 containing aluminum as a main component remaining after the formation of the dense oxide layer is a region functioning as a gate electrode. The silicon oxide film 10 exposed using the gate electrode 109, the surrounding dense oxide layer 108 (dense anodic oxide layer) and the porous oxide layer 104 as a mask.
4 is etched. (FIG. 5 (D))

Next, as shown in FIG. 6A, ions of phosphorus, which is an impurity imparting N-type, are added to 5 × 10 ^{14 to} 5 × 10 ^15.
The source region 1 is implanted at a dose of cm ^−2.
10 and the drain region 111 are formed. In this step, at the same time, the low impurity concentration region (lightly doped region) 1
12 and 116 are formed. This low impurity concentration region 1
The reason why the layers 12 and 116 are formed is that the implanted ions are shielded by the silicon oxide film 104 that is partially left. In the step of implanting impurity ions, offset gate regions 113 and 115 into which impurity ions are not implanted.
Are formed. (FIG. 6 (A))

After the impurity ions are implanted, heat treatment, laser light irradiation, or strong light irradiation is performed.
The region where the impurity ions have been implanted is activated.

Next, a silicon nitride film 100 is formed by a plasma CVD method using silane and ammonia, or silane and N ₂ O, or silane, ammonia and N ₂ O. The silicon nitride film 100 has a thickness of 500 to 2000 Å,
A film is formed to a thickness of 000 mm. The method for forming the silicon nitride film may be a method using dichlorosilane and ammonia. Alternatively, a low pressure thermal CVD method or a photo CVD method may be used.

After the formation of the silicon nitride film, at a temperature of 350.degree.
By performing heat treatment for a long time, annealing is performed on the surfaces of the silicon oxide film 104, the source region 110, and the drain region 111 damaged by the previous impurity ion implantation. In this step, hydrogen is diffused from the silicon nitride film 100,
Silicon oxide film 104, source region 110, and drain region 1
Defects existing on the surface of No. 11 are annealed.

The silicon oxide film 117 is formed to a thickness of at least 5,000 mm or more by a plasma CVD method using TEOS as a source gas, so that an interlayer insulating layer formed by laminating the silicon nitride film 100 and the silicon oxide film 117 is formed. To form

[Embodiment 2] This embodiment shows an example of a liquid crystal display device integrated on a substrate using a thin film transistor manufactured by using the invention disclosed in this specification. FIG. 7 shows a schematic configuration of this embodiment. The configuration shown in FIG. 7 is reduced in size by fixing a semiconductor chip mounted on a main board of a normal computer to at least one substrate of a liquid crystal display having a configuration in which a liquid crystal is sandwiched between a pair of substrates. This is an example of reducing the weight and thickness.

FIG. 7 will be described below. The substrate 15 is also a substrate of a liquid crystal display, and the TFT 1 is provided thereon.
1, an active matrix circuit 14 in which a number of pixels each having a pixel electrode 12 and an auxiliary capacitor 13 are formed, and an X decoder / driver, a Y decoder / driver, and an XY branch circuit for driving the active matrix circuit 14 are formed by TFTs. . Needless to say, the invention disclosed in this specification can be used as a TFT.

Then, another chip is mounted on the substrate 15. These chips are connected to circuits on the substrate 15 by means such as a wire bonding method and a COG (chip-on-glass) method. In FIG. 7, the correction memory, the memory, the CPU, and the input port are:
The chip is attached in this manner, and various other chips may be attached.

In FIG. 7, an input port is a circuit that reads a signal input from the outside and converts the signal into an image signal. The correction memory is a memory unique to a panel for correcting an input signal or the like in accordance with the characteristics of the active matrix panel. In particular, this correction memory has information unique to each pixel as a non-volatile memory,
This is for individual correction. That is, if a pixel of the electro-optical device has a point defect, a signal corrected in accordance therewith is sent to pixels around the point to cover the point defect and make the defect inconspicuous. Alternatively, when a pixel is darker than the surrounding pixels, a larger signal is sent to the pixel so as to have the same brightness as the surrounding pixels. Since the pixel defect information is different for each panel, the information stored in the correction memory is different for each panel.

The functions of the CPU and the memory are the same as those of an ordinary computer. In particular, the memory has an image memory corresponding to each pixel as a RAM. These chips are all CMOS type.

Further, at least a part of a required integrated circuit may be constituted by the thin film transistor disclosed in this specification. As described above, even a CPU and a memory are formed on a liquid crystal display substrate, and configuring an electronic device such as a simple personal computer with one substrate reduces the size of a liquid crystal display system and expands its application range. Very useful for.

[Embodiment 3] This embodiment is an example of a thin film transistor having an offset gate structure disposed in each pixel portion of an active matrix type liquid crystal display device. FIG. 8 shows a manufacturing process of the thin film transistor of this embodiment.

First, an underlying silicon oxide film 802 is formed on a glass substrate 801 to a thickness of 3000 ° by a sputtering method.
Next, the amorphous silicon film is subjected to plasma CVD or reduced pressure CV.
A film is formed to a thickness of 500 ° by Method D. Next, the amorphous silicon film is crystallized by heating or irradiation with laser light to obtain a crystalline silicon film. Further, by patterning, an active layer 803 of the thin film transistor is obtained. (FIG. 8
(A))

After obtaining the active layer 803 of the thin film transistor shown in FIG. 8A, a silicon oxide film 804 functioning as a gate insulating film is formed to a thickness of 1000 ° by a plasma CVD method or a sputtering method. 0.18w of scandium
A gate electrode 805 is formed by forming a film containing aluminum containing t% as a main component to a thickness of 6000 ° by an electron beam evaporation method and performing patterning.

After the gate electrode 805 is formed, anodic oxidation is performed in an ethylene glycol solution containing 5% tartaric acid using the aluminum-based gate electrode 805 as an anode to form a dense oxide layer 806. I do. The thickness of this oxide layer 806 is about 2000 °.

Then, phosphorus which is an impurity imparting N-type is doped by an ion implantation method or a plasma doping method. At this time, the regions 807 and 811 are implanted with an impurity imparting an N-type conductivity and become source / drain regions. The regions 808 and 809 correspond to the oxide layer 806.
Are used as a mask, ions of impurities are not implanted, and are formed as offset gate regions. 809 is determined as a channel formation region. In this step, a large number of defects are generated in the silicon oxide film 804 due to the impact of the implanted ions.

After the implantation of the impurity ions, heating, irradiation with laser light, or irradiation with strong light is performed.
Activate the source / drain regions. Then, the silicon nitride film 812 is formed by plasma C using silane and ammonia.
It is formed to a thickness of 1000 ° by the VD method.

Then, at 300 to 500 ° C., here 450
The heat treatment is performed for one hour in an inert atmosphere at ° C. By this heat treatment, hydrogen diffuses from the silicon nitride film into the silicon oxide film 804, and the defects in the silicon oxide film 804 generated in the impurity ion implantation step are annealed.

Then, a silicon oxide film 813 is formed to a thickness of 5000 ° by a plasma CVD method using TEOS. Further, an ITO electrode 814 constituting a pixel electrode is formed, and a source electrode 816 and a drain electrode 817 are formed through a hole forming step, thereby completing a thin film transistor.

[0059]

According to the present invention, an insulating film (for example, a silicon nitride film) having a property of trapping a positive charge is formed in contact with or adjacent to an active layer having an N type or an N type having a low impurity concentration. A thin film transistor which is not affected (or hardly affected) by electrons trapped in the interlayer insulating film can be realized. -It is possible to realize a thin film transistor which is not affected (or hardly affected) by moisture in the interlayer insulating film. A thin film transistor in which the operation of the thin film transistor is stabilized by positively utilizing the charge existing in the interlayer insulating film can be realized.

Further, the defects of the insulating film on the active layer generated in the step of implanting impurity ions can be annealed by performing a heat treatment after the formation of the silicon nitride film. As a result, it is possible to suppress deterioration of device characteristics due to defects existing in the insulating film formed on the active layer.

[Brief description of the drawings]

FIG. 1 is an enlarged view of a part of a thin film transistor .

FIG. 2 is a diagram showing a conventional manufacturing process of a thin film transistor.

FIG. 3 is a view showing a manufacturing process of a conventional thin film transistor.

FIG. 4 is an enlarged view of a part of a conventional thin film transistor.

FIG. 5 illustrates a manufacturing process of a thin film transistor.

FIG. 6 illustrates a manufacturing process of a thin film transistor.

FIG. 7 shows an outline of a system of a liquid crystal cover device.

FIG. 8 illustrates a manufacturing process of a thin film transistor.

[Explanation of symbols]

 Reference Signs List 102 silicon oxide film (base film) 103 active layer 104 silicon oxide film (gate insulating film) 105 film containing aluminum as a main component 106 dense anodic oxide layer 107 porous anodic oxide layer 108 dense anodic oxide layer 109 Gate electrode 110 Source region 111 Drain region 112 Low impurity concentration region 113 Offset gate region 114 Channel formation region 115 Offset gate region 116 Low concentration impurity region 117 Interlayer insulating film (silicon oxide film) 118 Source electrode 119 Drain electrode 100 Silicon nitride film

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 29/786 H01L 21/336

Claims (1)

(57) [Claims] A pair of intrinsic regions arranged in contact with the channel forming region; a pair of low impurity concentration N-type regions arranged in contact with the pair of intrinsic regions; and a pair of low impurity concentration regions A pair of high-impurity-concentration N-type regions disposed in contact with the N-type region.
A semiconductor device, comprising: a gate insulating film provided on a mold region; and a silicon nitride film provided on the gate insulating film and the pair of high impurity concentration N-type regions.