JP3341692B2 - Processor, electronic device equipped with the processor, program inspection method, and program inspection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor, an electronic device equipped with the processor, a program inspection method and a program inspection device, and more particularly, to a processor capable of inspecting a program in a mounted state, and an electronic device equipped with the processor. The present invention relates to an apparatus, a program inspection method for inspecting a program executed by a processor mounted on an electronic apparatus, and a program inspection apparatus.

[0002]

2. Description of the Related Art A program installed in a processor mounted on an electronic device such as a facsimile machine or a communication device rarely normally operates normally from the beginning. Therefore, usually, for example, problems (bugs and the like) of the program are removed by the following method. (1) In place of the ROM that is mounted on the electronic device and in which the above-described program is written, a memory (ROM emulator) to which an inspection program and various data are written at the time of the inspection is attached to the substrate of the electronic device.
M is inserted into the socket to be inserted, and ROM
Connect the debug control terminal to the emulator via the probe. Then, after causing the processor mounted on the electronic device to execute the inspection program written in the ROM emulator, the program is obtained at the time of execution of the program.
Based on various data written in the emulator, the debug control terminal is operated to eliminate problems (bugs, etc.) in the program. (2) A ROM emulator is connected in parallel with the ROM of (1), access from the processor is switched by a changeover switch, and a debug control terminal is connected to the ROM emulator via a probe. Then, at the time of inspection, the changeover switch is switched to the ROM emulator side to cause the processor to execute the inspection program written in the ROM emulator. Operate the debug control terminal to eliminate problems (bugs, etc.) in the program. In either case of the above methods (1) and (2), the same memory space as that of the ROM is allocated to the ROM emulator.

Here, FIG. 11 is a block diagram showing an example of the electrical configuration of a conventional program inspection apparatus according to the above-mentioned method (2). The program inspection apparatus of this example includes a processor 1, a display 2, a dip switch 3, an external bus 4, a changeover switch 5, a ROM 6, a ROM emulator 7, a probe 8, a debug control terminal 9, ,
And a RAM 10, and a processor 1,
Display 2, DIP switch 3, External bus 4, ROM
The RAM 6 and the RAM 10 constitute an electronic device to be inspected.

The processor 1 includes a CPU core (central processing unit) 11, an internal bus 12, a display driver 13, an input / output port 14, and a bus control unit (B
CU) 15. CPU core 11
Has a register ₁₆ 1 to 16 _5, the internal bus 12, B
R via the CU 15, the external bus 4 and the switch 5
OM6 or reads each instruction of the program from the ROM emulator 7, and registers ₁₆ 1 to 16 _5, using the RAM10 accessed via the internal bus 12, BCU15 the external bus 4, sequentially executes each instruction read And controls each part of the electronic device. CPU core 1
1 is supplied with an interrupt signal INT from outside. The display driver 13 drives the display 2 based on display data supplied from the CPU core 11 via the internal bus 12. The input / output port 14 supplies the data set by the dip switch 3 to the CPU core 11 via the internal bus 12. The BCU 15 converts the address supplied from the CPU core 11 via the internal bus 12 into the ROM 6, the ROM emulator 7 or the RAM 10 via the external bus 4.
To the ROM 6, the ROM emulator 7 or the RAM 10, and supplies the instructions and data supplied via the external bus 4 to the CPU via the internal bus 12.
While being supplied to the core 11, the data supplied from the CPU core 11 via the internal bus 12 is written to a predetermined area of the RAM 10 or the ROM emulator 7 via the external bus 4.

The display 2 is composed of a liquid crystal display, a plasma display or the like, is driven by a display driver 13, and displays numbers, characters, and the like on a display screen. The DIP switch 3 includes four switches connected in parallel, and is used for various mode settings and data input. When each switch is turned on, an "L" level signal is output and when the switch is turned off. Output an "H" level signal.
The changeover switch 5 is switched by an operator of the program inspection apparatus, and connects the external bus 4 to the ROM 6 or the RO.
Connect to one of the M emulators 7. ROM
6, a program to be checked is stored in advance.
The ROM emulator 7 stores a test program in advance and has a storage area in which data as a test result is stored. Probe 8 is a ROM
The emulator 7 and the debug control terminal 9 are connected. The debug control terminal 9 transmits the inspection result data stored in a predetermined storage area of the ROM emulator 7 to the probe 8.
And analyze the problem of the program to be inspected. The RAM 10 stores various data when the CPU core 11 executes each instruction of the program. Here, FIG. 12 shows an example of a memory space of the ROM 6 and the RAM 10 constituting an external memory of the electronic device to be inspected. In this example, as shown in FIG. 12, an address “0000” (4-bit hexadecimal number, the same applies hereinafter)
To the address “1FFF” is a program area, which is allocated to the ROM 6 and has the address “1FF”.
The area from “F” to the address “3FFF” is a data area, which is allocated to the RAM 10. In addition, ROM
The emulator 7 is assigned the same memory space as the ROM 6.

Next, the operation of the above-described program inspection apparatus will be described. In this example, the changeover switch 5
Is switched to the ROM 6 side, and as a result of the CPU core 11 executing the program written in the ROM 6, in order to display “5” (decimal number) on the display 2, each switch of the DIP switch 3 is operated to “ An object of the present invention is to eliminate a bug in a program when "3" (decimal number) is displayed on the display 2 despite setting "0101" (4-bit binary number). It is assumed that there is no problem on hardware. Where RO
If there is no bug in the program written in M6,
It is assumed that the CPU core 11 executes processing (hereinafter, referred to as display processing) in the following order. First, when each switch of the DIP switch 3 is operated to set a number “0101”, the data “0101” of the number is stored in the CPU.
After the core 11 is written to once register 16 ₁ via the input and output ports 14 and the internal bus 12, internal bus 12, B
The data is written to the address "2111" (see FIG. 12) of the RAM 10 via the CU 15 and the external bus 4. Next, C
The PU core 11 stores the address “211” of the RAM 10.
After reading the data “0101” written in “1”, the data is transferred to the display driver 13 via the external bus 4, the BCU 15, and the internal bus 12, and based on the data “0101”, the display driver 13 To display the number “5” on the display 2.

In this display processing, the following four routes are usually considered as a route where a bug may occur. (A) The data “0” set in the DIP switch 3
101 ”is transferred into the CPU core 11 via the input / output port 14 and the internal bus 12. (B) The data “01” transferred inside the CPU core 11
01 "is written to the register 16 of the _internal CPU core 11. (C) the data written in the register 16 ₁ "010
"1" is written to the address "2111" of the RAM 10 via the internal bus 12, the BCU 15, and the external bus 4. (D) The data “0101” written to the address “2111” of the RAM 10 is transferred to the external bus 4 and the BCU 15
The data is transferred to the display driver 13 via the internal bus 12 and is displayed on the display 2. Therefore, in order to confirm which of the routes (a) to (d) has a bug, a program check is performed according to the following procedure.

First, in order to check whether a bug has occurred in the route (a), for example, the CPU core 11
To, and reads out the set dip switch 3 data from the input-output port 14 the process of writing to the register 16 of the _internal CPU core 11 (hereinafter, referred to as the old process a) Instead of executing the dip switches 3 after writing to the register 16 ₂ data input-output port is read from the 14 set in the process of writing in a predetermined storage area of the ROM emulator 7 reads the data written to the register 16 ₂ (hereinafter, new process a ), And operates the debug control terminal 9 to execute RO
The data “010” is stored in a predetermined storage area of the M emulator 7.
It is sufficient to confirm whether "1" is correctly written. Therefore, the operator may use the old process a created in the high-level language.
After the subroutine for the new process a is created by modifying the subroutine for the new process a, the subroutine for the machine language is compiled into a machine language. The program exchanged with the subroutine is written into the ROM emulator 7 as a test program, and a storage area for writing data to the ROM emulator 7 is secured. Next, the operator attaches such a ROM emulator 7 to the program inspection apparatus and then switches the changeover switch 5 to connect the ROM emulator 7 to the external bus 4. Then, the operator sets the CPU core 11
To execute the program written in the ROM emulator 7. In this case, after the instruction immediately before the subroutine for the old process a is executed, the interrupt signal INT is supplied to temporarily suspend the process, and then the process is set to branch to the subroutine for the new process a. Thereby, when the interrupt signal INT is supplied, the CPU core 11 temporarily suspends the processing, and then branches to a subroutine relating to the new processing a.
After writing to the register 16 ₂ reads the set from the input-output port 14 to the DIP switch 3 data,
Since the data is written into a predetermined storage area of the ROM emulator 7, the operator operates the debug control terminal 9 to
The data "0101" is stored in a predetermined storage area of the emulator 7.
Check if is written. And ROM
The data "0101" is stored in a predetermined storage area of the emulator 7.
Is written, since a bug has not occurred in the route (a), the process proceeds to a procedure for checking whether or not a bug has occurred in the next route (b). On the other hand, if the data “0101” is not written in the predetermined storage area of the ROM emulator 7, a bug has occurred in the route of (a), and the new process a created in the high-level language After modifying the subroutine, compile it into a machine language, and then execute the
The data is written into the M emulator 7 and the above processing is repeated.

Next, in order to confirm whether a bug has occurred in the route (b), for example, the CPU core 11
RA reads the data written in the register 16 ₁
Processing of writing to the M10 address address "2111" (hereinafter referred to as the old process b) Instead of executing the, ROM reads the data written in the register 16 ₁
A process of writing to a predetermined storage area of the emulator 7 (hereinafter referred to as a new process b) is executed, and the debug control terminal 9 is operated to correctly write the data “0101” to the predetermined storage area of the ROM emulator 7. What is necessary is just to confirm whether it is. Therefore, the operator modifies the subroutine for the old process b created in the high-level language to create a subroutine for the new process b, compiles the machine language, and stores the subroutine of the machine language in the program written in the ROM 6. Among them, a program exchanged with a subroutine irrelevant to the above display processing having the same code size is written in the ROM emulator 7 as a test program, and a storage area for writing data in the ROM emulator 7 is secured. Next, the operator attaches such a ROM emulator 7 to the program inspection apparatus and then switches the changeover switch 5 to connect the ROM emulator 7 to the external bus 4. Then, the operator causes the CPU core 11 to execute the program written in the ROM emulator 7. In this case, after the instruction immediately before the subroutine relating to the old process b is executed, the interrupt signal INT is supplied to temporarily suspend the process, and then the new process b
Set to branch to the subroutine for Thus, CPU core 11, an interrupt signal INT is supplied, after temporarily suspended process branches to the subroutine regarding the new process b, the ROM emulator 7 reads the data written in the register 16 ₁ Since the data is written in the predetermined storage area, the operator operates the debug control terminal 9 to check whether the data “0101” is written in the predetermined storage area of the ROM emulator 7. If the data "0101" is written in a predetermined storage area of the ROM emulator 7, no bug has occurred in the route (b), and a bug has occurred in the route (c). Move to the procedure to check whether On the other hand, if the data “0101” is not written in the predetermined storage area of the ROM emulator 7, a bug has occurred in the route (b), and the new process b created in the high-level language After the subroutine is corrected, it is compiled into a machine language, the subroutine of the machine language is written into the ROM emulator 7 again, and the above-described processing is repeated.

Next, in order to check whether a bug has occurred in the route (c), for example, the CPU core 11
Instead of executing a process of reading data written at the address “2111” of the RAM 10 and transferring the data to the display driver 13 (hereinafter, referred to as an old process c),
After writing to the register 16 ₂ reads the data written in the RAM10 address address "2111", ROM reads the data written to the register 16 ₂
A process of writing to a predetermined storage area of the emulator 7 (hereinafter referred to as a new process c) is executed, and the debug control terminal 9 is operated to correctly write the data “0101” to the predetermined storage area of the ROM emulator 7. What is necessary is just to confirm whether it is. Therefore, the operator modifies the subroutine for the old process c created in the high-level language to create a subroutine for the new process c, compiles it into machine language, and stores the machine language subroutine in the program written in the ROM 6. Of these, a program exchanged with a subroutine irrelevant to the display processing, having the same code size, is written into the ROM emulator 7 as a test program, and a storage area for writing data to the ROM emulator 7 is secured. Next, the operator attaches such a ROM emulator 7 to the program inspection apparatus and then switches the changeover switch 5 to connect the ROM emulator 7 to the external bus 4. Then, the operator causes the CPU core 11 to execute the program written in the ROM emulator 7. In this case, after the instruction immediately before the subroutine related to the old process c is executed, the interrupt signal INT is supplied to temporarily suspend the process, and then the new process c is executed.
Set to branch to the subroutine for Accordingly, when the interrupt signal INT is supplied, the CPU core 11 temporarily suspends the processing, branches to a subroutine relating to the new processing c, and executes the address “211” of the RAM 10.
The data written in “1” is read and the register 16 ₂
After writing, since writing in a predetermined storage area of the ROM emulator 7 reads the data written to the register 16 _2, the operator operates the debug control terminal 9, in a predetermined storage area of the ROM emulator 7 It is checked whether data “0101” has been written. If the data "0101" is written in a predetermined storage area of the ROM emulator 7, no bug has occurred in the route (c), and a bug has occurred in the route (d). Move to the procedure to check whether On the other hand, if the data "0101" is not written in the predetermined storage area of the ROM emulator 7, a bug has occurred in the route of (c), and the new process c created in the high-level language is involved. After the subroutine is corrected, it is compiled into a machine language, the subroutine of the machine language is written into the ROM emulator 7 again, and the above-described processing is repeated.

Next, in order to confirm whether a bug has occurred in the route (d), for example, the CPU core 11
A process of reading the data written in the address “2111” of the RAM 10 and transferring the data to the display driver 13, based on the data, causing the display driver 13 to drive the display 2 and display the numbers on the display 2 ( Instead of executing the old process d), data “0101” is written in a predetermined storage area of the ROM emulator 7 in advance, and the data written in the predetermined storage area of the ROM emulator 7 is read and displayed. The data is transferred to the driver 13, and based on the data, the display driver 13 drives the display 2 to execute a process of displaying a number on the display 2 (hereinafter referred to as a new process d). What is necessary is just to confirm whether the number "5" is displayed correctly. Then, the operator modifies the subroutine for the old process d created in the high-level language to create a subroutine for the new process d, compiles it into machine language, and stores the subroutine of the machine language in the program written in the ROM 6. Of the subroutines having the same code size and having no relation to the above-mentioned display processing, are written into the ROM emulator 7 as a test program.
The data “010” is stored in a predetermined storage area of the OM emulator 7.
Write "1". Next, the operator can use such R
After attaching the OM emulator 7 to the program inspection device, the changeover switch 5 is switched to set the ROM emulator 7
Is connected to the external bus 4. Then, the operator causes the CPU core 11 to execute the program written in the ROM emulator 7. In this case, after the instruction immediately before the subroutine related to the old process d is executed, the interrupt signal INT is supplied to temporarily suspend the process, and then the process is set to branch to the subroutine related to the new process d. Thereby, the CP
When the interrupt signal INT is supplied, the U core 11 temporarily suspends the processing, branches to a subroutine relating to the new processing d, and reads out the data “0101” written in a predetermined storage area of the ROM emulator 7. Display driver 1
3 and the display driver 13 based on the data.
Then, the operator drives the display 2 to display the number on the display 2, so that the operator checks whether or not the number “5” is correctly displayed on the display 2. If the number "5" is correctly displayed on the display 2, it can be confirmed that no bug has occurred in the route (d). On the other hand, if the number “5” is not correctly displayed on the display 2, a bug has occurred in the route of (d).
After correcting the subroutine relating to the new process d created in the high-level language, the subroutine is compiled into a machine language, the subroutine of the machine language is written into the ROM emulator 7 again, and the above process is repeated.

[0012]

By the way, in the above-mentioned conventional program inspection method, in any of the above-mentioned methods (1) and (2), the manufacturer of the electronic equipment is in the development stage of the electronic equipment. Although it is suitable for inspecting a program, since the ROM emulator and the debug control terminal must be connected via a probe, the electronic device is completed and the processor and the ROM are mounted on the case of the electronic device. In this case, remove the ROM and
There is a drawback that the program cannot be inspected because it cannot be replaced with an OM emulator. Therefore, for example, there has been a problem that, for example, an electronic device is sold, a complaint is received from a user, and a program cannot be inspected again with a processor or a ROM mounted on the electronic device in order to deal with the complaint.

In the above-described conventional program checking method, the same memory space as that of the ROM is allocated to the ROM emulator in any of the methods (1) and (2). When only one process such as the display process described above is inspected at the initial stage of program development, there is room in the memory space, so that a program for inspection can be allocated to an empty memory space. At the stage of completion, most of the memory space is filled, and as described above, in order to write the test program into the ROM emulator, it must be exchanged with another subroutine, which is troublesome. In some electronic devices, for example, a program is externally transferred and stored in a partial storage area of a RAM, such as a communication device. However, in the above-described conventional program inspection method, as described above, it is troublesome or difficult to inspect the program written in the ROM alone, so that the inspection of the program written in the RAM is more difficult. It is even more cumbersome and almost impossible.

Further, when a subroutine relating to a more complicated process is inspected instead of a subroutine relating to a simple process such as the above-mentioned display process, not only the size of the subroutine to be inspected but also the size of the subroutine for the inspection increases. However, in such a case, if the same memory space is allocated to the ROM emulator and the ROM, both the program immediately before the subroutine and the subroutine for inspection cannot be written to the ROM emulator. The method (1) makes it impossible to check the program itself. In the method (2), the program up to immediately before the subroutine is written in the ROM 6 and the subroutine for inspection is written in the ROM emulator 7, and at the time of inspection, the changeover switch 5 is first switched to the ROM 6 side, and the subroutine of the subroutine is written. After executing the program up to immediately before, the execution of the program is temporarily interrupted by an interrupt. Next, the changeover switch 5
May be switched to the ROM emulator 7 side, and then a subroutine for inspection may be executed.

Therefore, for example, as disclosed in Japanese Patent Application Laid-Open No. 63-4346, it is conceivable to secure a storage area in the memory space of the ROM only for debugging, It is useless to secure a storage area that is not used, and a large-capacity RO
M is required, and electronic equipment becomes expensive. Further, in order to save the trouble of switching the changeover switch 5, the changeover switch 5
It is conceivable to simply connect the ROM 6 and the ROM emulator 7 to the external bus 4 in parallel without providing
In recent years, the operating speed of the CPU core 11 has increased, and the operating clock has reached several hundred MHz.
When the OM 6 and the ROM emulator 7 are connected to the external bus 4 in parallel, unnecessary parasitic capacitance is added to the external bus 4, and electrical characteristics such as output delay, setup time, and hold time deteriorate. As a result, the waveform of the signal transferred by the external bus 4 may be distorted, the electronic device may not operate normally, and the program test may not be performed as expected. Further, if there is a hardware defect in the ROM 6, for example, a short circuit between adjacent pins,
There is a problem that the U core 11 cannot accurately read the program written in the ROM emulator 7, and the program itself cannot be inspected.

In the above-described conventional program inspection method, there are four routes where a bug may occur even in the inspection of a subroutine relating to a simple process such as the above display process. In order to confirm whether or not a bug has occurred, the procedure of creating a subroutine for inspection in a high-level language as described above, compiling it, writing a subroutine of a machine language into the ROM emulator 7, executing it, and modifying the subroutine is performed. Therefore, there is a problem that it takes an enormous amount of trouble and time in the inspection of the subroutine for more complicated processing.

By the way, most of the above description assumes that there is no problem on hardware.
There is a case where a normal operation cannot be performed due to a connection failure in the OM 6, the external bus 4 connecting the RAM 10 and the BCU 15, or the like. However, in the above-described conventional program inspection method, the ROM emulator is also connected to the BCU 15 together with the ROM 6 and the RAM 10, so that there is a drawback that the above-mentioned faulty connection cannot be found. In the above-described conventional program inspection method (1), the ROM 6 and the ROM
The emulator 7 is connected to the external bus 4 via the changeover switch 5.
Therefore, if the ROM 6 itself has a hardware defect and thus has any adverse effect on the external bus 4, even if the changeover switch 5 is switched, the external bus 4 still has the adverse effect. There are cases. In such a case, even if the program is inspected using the ROM emulator 7, the same problem occurs, and therefore, there is a problem that the cause cannot be determined.

The present invention has been made in view of the above circumstances, has a simple and inexpensive configuration, and can accurately inspect a program in a mounted state with a simple operation in a short time. Provided is a processor capable of checking a program supplied from the outside and further determining the cause of a hardware failure, an electronic device equipped with the processor, a program checking method, and a program checking device. It is an object.

[0019]

According to a first aspect of the present invention, there is provided a processor for storing a program to be executed by a central processing unit and information used when the program is executed. A first transfer control unit that controls the transfer of instructions and information to and from a first storage medium to which one memory space is allocated; and a first transfer control unit that is different from the first memory space of the first storage medium. A second memory space is allocated, and controls the transfer of instructions and information to and from a second storage medium in which a test program for checking the program and information used for checking the program are stored. 2 transfer control means, the first transfer control means, the second transfer control means, and an internal bus commonly connected to the central processing unit, wherein the second transfer control means , The second A first control unit for controlling each unit of the second transfer control unit when an address corresponding to a memory space is supplied from the internal bus; and a parallel address or information from the internal bus is serialized. And converting the serial address or information from the second storage medium into a parallel address or information and outputting the parallel address or information to the internal bus. I have.

According to a second aspect of the present invention, there is provided the processor according to the first aspect, wherein the number of signal lines connecting the second storage medium and the second transfer control means is equal to the first storage medium. And the number of signal lines connecting the first transfer control means and the first transfer control means.

According to a third aspect of the present invention, there is provided the processor according to the first or second aspect, wherein the second transfer control means reads out information stored in the first storage medium at the time of checking the program. It is characterized in that it is stored in the second storage medium.

According to a fourth aspect of the present invention, there is provided the processor according to any one of the first to third aspects, wherein the central processing unit comprises: a plurality of registers for temporarily storing information; Through the transfer control means of the first or the second
It reads each instruction from the storage medium constituting the program or the test program, the first accessed via the plurality of registers and said first transfer control means
Control means for sequentially executing the read instructions and a first vector address indicating a first branch destination to be branched when an interrupt occurs during normal use, using a storage medium of A second vector address register in which a first vector address register to be stored and a second vector address indicating a second branch destination to be branched when an interrupt occurs during a program check are stored in advance. And the value of the address of an instruction to be executed next by the second control means is stored, and the value is sequentially incremented each time an instruction is executed, or the first or second vector address is stored. Register first
Alternatively, a program counter to which a second vector address is supplied and a break address, which is an address of a branch source at which the operation of the program by the second control means is temporarily interrupted to generate an interrupt, are stored. A plurality of break address registers, each of which is specified in advance by an interrupt vector, which is an address address of a branch destination to be branched when an interrupt occurs at the time of program inspection; an output value of the program counter; A plurality of break addresses supplied from a plurality of break address registers are compared.
And a comparing means for supplying an interrupt signal to the second control means.

According to a fifth aspect of the present invention, there is provided the processor according to any one of the first to fourth aspects, wherein the second transfer control means transfers the data from the first control means and the central processing unit. A decoder for decoding the transferred address, an address buffer for temporarily holding the address transferred from the central processing unit, a data buffer for temporarily holding the information transferred from the central processing unit, and a data buffer for temporarily storing the information transferred from the central processing unit. The supplied address or the above data
A selector for selecting and outputting one of the information supplied from the buffer, and a reception buffer for temporarily holding serial information transferred from the second storage medium, converting the serial information to parallel information, and outputting the parallel information. A transmission buffer for temporarily storing a parallel address or information transferred from the selector and a command supplied from the first control unit, and then converting the serial address or information into a serial address or information and outputting the serial address or information; The first control means controls each section of the device when the address decoded by the decoder is an address corresponding to the second memory space.

The invention according to claim 6 relates to the processor according to any one of claims 1 to 5, wherein the central processing unit, the first transfer control means, and the second transfer control means Are formed in the same chip.

According to a seventh aspect of the present invention, there is provided the processor according to the sixth aspect, wherein at least one terminal for connecting the second storage medium and the second transfer control means is provided. It is characterized by:

According to an eighth aspect of the present invention, there is provided an electronic apparatus including the processor according to any one of the first to seventh aspects, wherein the electronic apparatus is connectable to the second storage medium.

According to a ninth aspect of the present invention, there is provided a program inspection method, wherein the second storage medium storing the inspection program is connected to the electronic device according to the eighth aspect, and the program or the inspection program is connected to the electronic device. The program is inspected based on information read from the first storage medium and a plurality of registers constituting the central processing unit and stored in the second storage medium. And

According to a tenth aspect of the present invention, there is provided a program inspection apparatus, wherein the electronic device according to the eighth aspect, the second storage medium storing the inspection program, and connected to the electronic device, And by executing the inspection program, based on the information read from the first storage medium or a plurality of registers constituting the central processing unit and stored in the second storage medium, And a program checking means for checking a program.

[0029]

According to the configuration of the present invention, a program can be inspected with a simple and inexpensive configuration. In addition, the program can be accurately inspected in the mounted state in a short time with a simple operation. In addition, it is possible to inspect a program supplied from the outside and to find out the cause of a hardware defect.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using an embodiment. FIG. 1 is a block diagram showing an electrical configuration of a program inspection apparatus according to one embodiment of the present invention. In this example, the program checking device includes a processor 21
, Display 22, dip switch 23, external bus 24, ROM 25, RAM 26, external bus 27
, A debug memory 28 and a debug control terminal 29
And a mode changeover switch 30. The processor 21, the display 22, the DIP switch 23, the external bus 24, the ROM 25 and the RAM 26 constitute an electronic device to be inspected. Has been implemented.

The processor 21 has a CPU core (central processing).
Device) 31, an internal bus 32, a display driver 33,
The input / output port 34 and the BCUs 35 and 36
Has been established. The CPU core 31 includes a register 37₁~ 3
7₅, Control circuit 38, and vector address register
39₁And 39₂, An address generation circuit 40, and a program
RAM counter (PC) 41 and break address
Register 42₁And 42₂And the comparator 43.
Has been established. Register 37₁~ 37₅There are various types of data
The data is temporarily stored. The control circuit 38 controls the internal bus 3
2, BCU 35 or 36, external bus 24 or external bus 2
From ROM 25 or debug memory 28 via
Each instruction constituting the program is read, and a register 37 is read.
₁~ 37₅And internal bus 32, BCU 35 and external bus
24 using the RAM 26 accessed through the
These instructions are sequentially executed to control each part of the electronic device.
Vector address register 39₁And 39₂In the
Interrupts in user mode and debug mode, respectively
The vector address "000" of the branch destination to be branched at the time of occurrence
0 ”and“ E000 ”are stored in advance,
Under control, the mode supplied by the mode switch 30 is controlled.
Mode switching signal S_MIs high, the vector
Dress register 39₁Vector address stored in
To the mode switching signal S_MIs low level is vector
・ Address register 39₂Vector add stored in
Are supplied to the address generation circuit 40, respectively. A
Under the control of the control circuit 38, the dress generation circuit 40
Address register 39₁Or 39₂Supplied by
The supplied vector address is supplied to the PC 41. To PC41
Is the address value of the instruction to be executed next by the control circuit 38
Is stored, and the value is sequentially counted every time each instruction is executed.
Or the value of the branch destination vector address is supplied.
Or be done. Break address register 42₁Passing
And 42 ₂The operation of the program by the control circuit 38
Minute to interrupt (break) and generate an interrupt
The break address, which is the address of the origin, is stored.
It is. Also, the break address register 42₁as well as
42₂Are assigned in debug mode.
Is the address of the branch destination to branch to when an interrupt occurs.
Vector B13 and B15 are specified in advance.
(See FIG. 3). The comparator 43 is supplied from the PC 41.
Output value of PC41 and break address register
TA 42₁Or 42₂Address supplied from
And when they match, the interrupt signal INT is controlled by the control circuit.
To the road 38.

The display driver 33 drives the display 22 based on display data supplied from the CPU core 31 via the internal bus 32. The input / output port 34 transmits the data set by the dip switch 23 to the internal bus 3.
2 to the CPU core 31. BCU35,
By supplying the address supplied from the CPU core 31 via the internal bus 32 to the ROM 25 or the RAM 26, the instructions and data read from the ROM 25 or the RAM 26 and supplied via the external bus 24 are transferred to the internal bus 32.
And writes the data supplied from the CPU core 31 via the internal bus 32 to a predetermined area of the RAM 26 via the external bus 24.

The BCU 36 serially supplies the address supplied from the CPU core 31 via the internal bus 32 to the debug memory 28 via the external bus 27, so that the BCU 36 reads the address from the debug memory 28 and reads the external bus 2
7 is supplied to the CPU core 31 via the internal bus 32 and the CPU
The data supplied from 1 through the internal bus 32 is serially supplied to the debug memory 28 via the external bus 27 and written into a predetermined area of the debug memory 28. B
The CU 36 is connected to the internal bus 32 by, for example, 32 signal lines, and is connected to the debug memory 28 by the external bus 27 formed by, for example, three signal lines. Therefore, the LSI configuring the processor 21
The chip is provided with three terminals for the external bus 27. And this LSI chip, ROM25, RAM
A connector receiver connected to the above-mentioned three dedicated terminals is mounted on a board on which the 26 and the like are mounted, a cover of the electronic device is removed, and a debug memory 28 is connected to one end of the connector receiver. A connector attached to the other end of the external bus 27 is inserted into the LSI chip, that is, the BCU 36 constituting the processor 21 and the debugger.
By connecting to the memory 28, a program inspection in a mounted state can be performed. Note that the connector receiver on the board need not be provided on the boards of all the electronic devices, but may be provided only on the boards of the electronic devices used for the program inspection.

FIG. 2 is a block diagram showing an example of the electrical configuration of the BCU 36. The BCU 36 in this example is
A decoder 51, an address buffer 52, and a data
It is roughly composed of a buffer 53, a control circuit 54, a selector 55, a reception buffer 56, and a transmission buffer 57. The decoder 51, under the control of the control circuit 54,
The address transferred from the CPU core 31 via the internal bus 32 is decoded and supplied to the control circuit 54. The address buffer 52 has a CPU under the control of the control circuit 54.
After temporarily holding the address transferred from the core 31 via the internal bus 32, the address is supplied to the selector 55. data·
The buffer 53 temporarily stores data transferred from the CPU core 31 via the internal bus 32 under the control of the control circuit 54, and then supplies the data to the selector 55. Control circuit 54
When the address decoded by the decoder 51 is the address assigned to the debug memory 28, the device controls each unit of the device. The selector 55 includes the control circuit 5
Under the control of (4), either the address supplied from the address buffer 52 or the data supplied from the data buffer 53 is selected and supplied to the transmission buffer 57. Under the control of the control circuit 54, the reception buffer 56 temporarily holds serial information transferred from the debug memory 28 via the external bus 27, converts the serial information into parallel information, and converts the serial information into parallel information via the internal bus 32. While being transferred to the core 31, a part is supplied to the control circuit 54. The transmission buffer 57 stores the parallel address or data transferred from the selector 55 and the control circuit 5 under the control of the control circuit 54.
4 is temporarily stored, converted into serial information, and supplied to the debug memory 28 via the external bus 27.

The display 22 shown in FIG. 1 is composed of a liquid crystal display, a plasma display, or the like, is driven by a display driver 33, and displays numbers and characters on a display screen. The dip switch 23 has four switches connected in parallel, and is used for setting various modes and inputting data. When each switch is turned on, an "L" level signal is output and turned off. In this case, an "H" level signal is output. The program to be inspected is stored in the ROM 25 in advance. The RAM 26 stores various data when the CPU core 31 executes each instruction of the program. In the debug memory 28, a program for inspection is stored in advance, and a storage area for storing data as an inspection result is provided. The debug control terminal 29 reads out the data as the inspection result stored in a predetermined storage area of the debug memory 28,
Analyze problems in the program to be checked. Note that the debug memory 28 and the debug control terminal 29 may be integrated instead of being connected by a probe as in the conventional case. Mode switching switch 30, the terminal T _a is connected to the power supply voltage V _{C C,} terminal T _b is grounded, the terminal T _c is connected to a mode switching signal input terminal of the LSI chip constituting the processor 21, terminal If the T _c is connected to the terminal T _a, while supplying the "H" level mode switching signal S _M of indicating the user mode to the processor 21,
When the terminal T _c is connected to the terminal T _b is the debug
"L" level mode switching signal S indicating the mode
_M is supplied to the processor 21. Here, the user mode is a mode set at the time of normal use, and is fixed to this mode when the electronic device is shipped to the market. In contrast, debug mode is
This mode is set during program inspection.

Next, FIG. 3 shows an example of the memory space of the ROM 26 and the RAM 25 constituting the external memory of the electronic device to be inspected and the debug memory 28. In this example, as shown in FIG.
From "0" (4-bit hexadecimal number, the same applies hereinafter) to an address "1FFF", a program area is provided.
5 and is a data area from address “1FFF” to address “DFFF”.
The area from address “E000” to address “FFFF” is a debug use area, and is allocated to the debug memory 28. That is, unlike the conventional case, the ROM 25 and the debug memory 28 are allocated different and independent memory spaces.

In the program area, from address address "0000" to address address "0002", interrupt vectors B01 to B03 used in the user mode are set.
Is stored, and a subroutine A is stored from the address “1010” to the address “101F”, and a subroutine B is stored from the address “1030” to the address “103F”. 4 and 5,
Examples of subroutine A and subroutine B are shown below. In this embodiment, when there is no bug in the program written in the ROM 25, the CPU core 31 executes processing (hereinafter, referred to as display processing) in the following order. First, when each switch of the dip switch 23 is operated to set a numeral “0101” (4-bit binary number), the CPU core 31 transmits the numerical data “0101” to the input / output port 34 and the internal bus 32. after writing to once register 37 ₁ via the internal bus 3
2. The data is written to the address "2111" (see FIG. 3) of the RAM 26 via the BCU 35 and the external bus 24. Next, the CPU core 31 reads the address “2
After reading the data “0101” written in “111”, the data is transferred to the display driver 33 via the external bus 24, the BCU 35, and the internal bus 32, and the data “0101” is read.
On the basis of “1”, the display driver 33 drives the display 22 to display the number “5” (decimal number) on the display 22.
Therefore, in the subroutine A shown in FIG. 4, the first line reads the data set in the DIP switch 23 from the address “_IO_ADR” of the input / output port 34 and writes the data in the register 37 ₁ (register A). the stands, second row address number of RAM26 reads data written in the register 37 ₁ "21
11 ". FIG.
In the subroutine B shown in FIG.
Reads out the data written in the 6 address number "2111" of representing instructions that write to the register 37 3 _(register C), the address of the display driver 33 second row reads data written to the register 37 ₃ It represents an instruction to transfer to the address “_TV_ADR”.

In the debug use area, the interrupt vectors B11 to B used in the debug mode are provided from the address "E000" to the address "E0004".
15 is stored, a subroutine C is stored from the address “E100” to the address “E110”, and the address “F010” is stored from the address “F000”.
Has a subroutine D stored therein, and an address "F02"
Subroutine E from address "0" to address "F030"
Is stored. In this embodiment, the interrupt vector B11
To B15, address addresses “E100”,
“1010”, “F1000”, “1030” and “F”
020 "is set. 6 to 8 show examples of the subroutine C, the subroutine D, and the subroutine E, respectively. In this embodiment, as a result of the CPU core 31 executing the display processing including the subroutine A and the subroutine B written in the ROM 25, the dip switch 23 is displayed on the display 22 to display "5" (decimal). Despite having set “0101” (4-bit binary number) by operating the switches of
It is an object of the present invention to remove a bug in a program when "3" (decimal number) is displayed on the screen. It is assumed that there is no problem on hardware. In the above-described display processing, the following three routes are usually considered as routes where a bug may occur. (A) the data set "0101" on the DIP switch 23 is transferred to the CPU core 31 via the input and output ports 34 and the internal bus 32, it is written into the register 37 _1. (B) the data written in the register 37 ₁ "010
"1" is written to the address "2111" of the RAM 26 via the internal bus 32, the BCU 35, and the external bus 24. (C) The data “0101” written at the address “2111” of the RAM 26 is transferred to the external bus 24 and the BCU 3
5 and transferred to the display driver 33 via the internal bus 32 and displayed on the display 22.

In order to confirm which of the routes (a) to (c) has a bug, in the subroutine C shown in FIG.
The break address register 42 ₁ (#
18) As the break address, the address "10
It represents a process of writing the 20 ', break second line in the break address register ₄₂ 2 (# 19)
The process of writing the address “1040” as the address is shown, and the third line shows the instruction to return from the subroutine C to the branch source. This subroutine C
Is a subroutine of preparation for interrupting processing of a subroutine D described later after the processing of the subroutine A and interrupting processing of a subroutine E described later after the processing of the subroutine B.
In the subroutine D shown in FIG. 7, the first line is a command to read data set in the dip switch 23 from the address “_IO_ADR” of the input / output port 34 and write the data to the register 37 ₂ (register B). the stands, second row represents an instruction that writes to the register 37 address number "F100" of ₂ written data by reading the debug memory 28, the data line 3 is written into the register 37 ₁ reading represents an instruction of writing into the address of the debug memory 28 "F101", the fourth line represents a command that writes read data written into the address "2111" in the RAM26 into register 37, _second line 5 reads data written in the register 37 ₂ debug a note Represents an instruction that writes to the 28 address address of "F102", the sixth row this subroutine D
From the branch source to the branch source. This subroutine D is a subroutine for confirming whether a bug has occurred in the routes (a) and (b). Further, in the subroutine E shown in FIG. 8, the first line is an address "_TV_ADR" of the display driver 33.
Data reads represents an instruction that writes to the register 37 _2, the second row represents an instruction that writes to the register 37 address number "F110" of ₂ written data by reading the debug memory 28, the third The line indicates an instruction for returning from the subroutine E to the branch source. This subroutine E is a subroutine for confirming whether or not a bug has occurred in the route (c). Subroutine C and D described above
The subroutine E is created in a high-level language, compiled into a machine language, and compiled in a debug memory 28 at a program development stage or at a stage where a complaint is received from a user after the electronic device is shipped to the market. Write to the address. Thus, according to this embodiment, the ROM 2
5 is different from the memory space of the debug memory 28, so that the subroutine for inspection can be freely created at once regardless of the stage.

Next, the operation of the above-configured program inspection apparatus and the operation of the operator will be described with reference to the flowchart shown in FIG. First, when the operator connects the terminal T _c of the mode selector switch 30 to the terminal T _a,
Mode was switched to debug mode (step SP
1) After that, when the power switch is turned on, the control circuit 38
Each part of the electronic device was reset and initialized (step S
After P2), the "H" to the mode switch signal S _M of the level is supplied, since recognizes that it has been switched to the debug mode, vector address register 39 previously stored vector address ₂ " E000 ”is supplied to the address generation circuit 40. Next, the control circuit 38
In the address generation circuit 40, the vector address "E
The value "E000" generated based on "000"
1 and the value of the interrupt vector B11 stored at the address "E000" of the debug memory 28,
In this case, the address “E100” is set to the external bus 27,
Reading is performed via the BCU 36 and the internal bus 32 (step SP3). Next, the control circuit 38 supplies the read value (address address “E100”) of the interrupt vector B11 to the PC 41 via the address generation circuit 40, and writes the value into the address address “E100” of the debug memory 28. In this case, the instruction of the first line of the subroutine C shown in FIG. 6 is read out via the external bus 27, the BCU 36, and the internal bus 32, and the execution of the subroutine C is started (step SP4). That is, the control circuit 38
41 while counting up the value,
The instruction written from the address “E100” to the address “E110” of the memory 28 is transferred to the external bus 2
7. Read out via the BCU 36 and the internal bus 32 and execute the subroutine C. First, the control circuit 38 after writing the address number "1020" in the break address registers 42 ₁ as a break address, writes the address number "1040" in the break address register 42 ₂ as a break address, the To return from the subroutine C, the address generation circuit 40
To the PC 41 via the address "E001" of the branch source
Supply.

During the above processing, the comparator 43 compares the output value of the PC 41 with the break address register 42.
And comparing the break address set in advance in the ₁ or 42 _2, if there is a match, an interrupt signal INT
Is supplied to the control circuit 38 (address trap). Therefore, the control circuit 38 determines whether or not there is an interrupt even during execution of the subroutine (step S
P5) If the interrupt signal INT is supplied, the currently executing subroutine is temporarily interrupted to execute the interrupt subroutine (step SP7), and then the execution of the subroutine interrupted by the interrupt is continued (P5). Step SP
6). In this case, since the subroutine C for setting the break address itself is being executed, the interrupt signal IN
T is not supplied to the control circuit 38. Next, the control circuit 38
Determines whether execution of all subroutines in the debug mode is completed based on the output value of the PC 41 (step SP8). The result of this determination is “YE
In the case of "S", the control circuit 38 ends the series of processing. On the other hand, if the decision result in the step SP8 is "NO", that is, if there is a subroutine not yet executed in the debug mode, the control circuit 38 returns to the step SP3. In this case, since only subroutine C has been executed, the result of the determination in step SP8 is "N
O ", and the control circuit 38 returns to step SP3.

Next, the control circuit 38 uses the value of the interrupt vector B12 stored at the address "E001" of the debug memory 28, in this case, the address "1010" as the external bus 27, the BCU 36 and the internal bus. 32 (step SP3). Next, the control circuit 38 reads the value of the read interrupt vector B12 (address address “101”).
0)) to the PC 41 via the address generation circuit 40, and the instruction written at the address "1010" of the ROM 25, in this case, the instruction on the first line of the subroutine A shown in FIG. 24, read out via the BCU 35 and the internal bus 32 and start execution of the subroutine A (step SP4). That is, the control circuit 38
While making PC 41 count up the value, ROM
25 address addresses "1010" to "1"
01F ”to the external bus 24, BC
The subroutine A is read out via the U35 and the internal bus 32 and executed. First, the control circuit 38, after writing to the register 37 ₁ via the internal bus 32 reads the set dip switch 23 data from address number "_IO_ADR" of the input and output ports 34, written in the register 37 ₁ Reads the data stored in the internal bus 3
2. The data is written to the address “2111” of the RAM 26 via the BCU 35 and the external bus 24.

The above processing is completed, the output value of the PC41 is "1020", break address set in advance in the break address register 42 ₁ "10
20 ”, the comparator 43 outputs the interrupt signal INT.
Is supplied to the control circuit 38. Therefore, the control circuit 38
Goes to step SP7 because the result of the determination in step SP5 is "YES".
Execute That is, first, the control circuit 38
Supplies address number "E002" in the debug memory 28 interrupt vector B13 that is designated in advance in the address register 42 ₁ is stored in the PC41 via the address generation circuit 40, the address of the debug memory 28 From the address "E002" to the value of the interrupt vector B13,
In this case, the address "F000" is set to the external bus 27,
Reading is performed via the BCU 36 and the internal bus 32. next,
The control circuit 38 supplies the read value of the interrupt vector B13 (address address “F000”) to the PC 41 via the address generation circuit 40 and the debug memory 28
, The instruction in the first line of the subroutine D shown in FIG. 7 is read out via the external bus 27, the BCU 36, and the internal bus 32, and the execution of the subroutine D is started. I do.

That is, the control circuit 38 causes the PC 41 to count up the value, and from the address address “F000” of the debug memory 28 to the address address “F01”.
0 ”to the external bus 27, BCU3
6 through the internal bus 32 and the subroutine D
Execute First, the control circuit 38 reads the data set in the dip switch 23 from the address “_IO_ADR” of the input / output port 34 and reads the data from the internal bus 32.
After writing to the register 37 ₂ via a register 37
₂ is read and the internal bus 32, B
Debug memory 2 via CU 36 and external bus 27
8 writes the address number "F100" in the debug via the internal bus 32, BCU36 the external bus 27 reads the data written in the register 37 ₁
The data is written to the address "F101" of the memory 28. Further, the control circuit 38 determines that the address “2
111 ”and read the data written to the external bus 2
4. Register 37 via BCU 35 and internal bus 32
After writing to _2, the internal bus 32 by reading the data written to the register 37 _2, BCU36 and address number of the external bus 27 through the debug memory 28 "F
In order to return to the subroutine D and to return from the subroutine D, the branch source address "E003" is supplied to the PC 41 via the address generation circuit 40. Thereby, the control circuit 38 continues the execution of the subroutine whose processing has been interrupted by the interruption (step SP6). Next, the control circuit 38 determines, for example, whether or not execution of all subroutines in the debug mode has been completed based on the output value of the PC 41 (step SP8). Therefore, the result of the determination in step SP8 is "NO", and the control circuit 38 returns to step SP3.

Next, the control circuit 38 stores the value of the interrupt vector B14 stored at the address "E003" of the debug memory 28, in this case, the address "1030" into the external bus 27, the BCU 36 and the internal bus. 32 (step SP3). Next, the control circuit 38 reads the value of the read interrupt vector B14 (address address “103”).
0 ") to the PC 41 via the address generation circuit 40, and the instruction written at the address" 1030 "of the ROM 25, in this case, the instruction on the first line of the subroutine B shown in FIG. 24, read out via the BCU 35 and the internal bus 32 and start execution of the subroutine A (step SP4). That is, the control circuit 38
While making PC 41 count up the value, ROM
25 address addresses “1030” to “1”
03F ”and the external bus 24, BC
Subroutine B is executed by reading through U35 and internal bus 32. First, the control circuit 38, after writing to the register 37 ₃ via the external bus 24, BCU35 and the internal bus 32 reads the data written into the address "2111" in the RAM 26, written into the register 37 ₃ Data Is read out and transferred to the address “_TV_ADR” of the display driver 33 via the internal bus 32.

The above processing is completed, the output value of the PC41 is "1040", break address set in advance in the break address register 42 ₂ "10
40 ”, the comparator 43 outputs the interrupt signal INT.
Is supplied to the control circuit 38. Therefore, the control circuit 38
Goes to step SP7 because the result of the determination in step SP5 is "YES".
Execute That is, first, the control circuit 38
Supplies address number "E004" in the debug memory 28 interrupt vector B15 that is designated in advance in the address register 42 ₂ is stored in the PC41 via the address generation circuit 40, the address of the debug memory 28 From the address "E004" to the value of the interrupt vector B15,
In this case, the address “F020” is set to the external bus 27,
Reading is performed via the BCU 36 and the internal bus 32. next,
The control circuit 38 supplies the read value of the interrupt vector B15 (address address “F020”) to the PC 41 via the address generation circuit 40 and the debug memory 28
, The instruction in the first line of the subroutine E shown in FIG. 8 is read out via the external bus 27, the BCU 36 and the internal bus 32, and the execution of the subroutine E is started. I do.

That is, the control circuit 38 causes the PC 41 to count up the value, and from the address “F020” of the debug memory 28 to the address “F03”.
0 ”to the external bus 27, BCU3
6 through the internal bus 32 and the subroutine E
Execute First, the control circuit 38 controls the display driver 33
After writing of the register 37 ₂ via the internal bus 32 reads the data of address number "_TV_ADR" debug via the internal bus 32, BCU36 the external bus 27 reads the data written to the register 37 ₂ In order to write to the address “F110” of the memory 28 and to return from the subroutine E, the branch source address “E005” is supplied to the PC 41 via the address generation circuit 40. Thereby, the control circuit 38
Continues the execution of the subroutine whose processing has been interrupted by the interruption (step SP6). Next, the control circuit 38
Determines, for example, whether the execution of all subroutines in the debug mode has been completed based on the output values of the PC 41 (step SP8). In this case, only the subroutines C, D and E have been executed. , Step S
The decision result in P8 is "NO", and the control circuit 38 returns to step SP3.

Next, the control circuit 38 causes the PC 41 to count up the value and, at the same time, sends the instruction written after the address “E005” of the debug memory 28 via the external bus 27, the BCU 36 and the internal bus 32. And read and execute other subroutines. Next, the control circuit 38 performs debugging /
It is determined whether or not the execution of all subroutines in the mode has been completed (step SP8). If the execution of all subroutines has been completed, the determination result of step SP8 is "YES", and the control circuit 38 Is completed. As a result, the operator can control the debug control terminal 29
By operating the address "F" of the debug memory 28.
100 "," F101 "," F102 "and" F11 "
It is checked whether data “0101” is written in “0” or not, and whether the number “5” is displayed on the display 22. Then, for example, the debug memory 28
If the data "0101" is not written in the address "F100", it is determined that a bug has occurred in the corresponding subroutine, and the correction is performed. Thereafter, the corrected subroutine is written into the debug memory 28, and the control circuit 38 executes the subroutine to check whether the subroutine operates normally.

Next, in the above configuration, the CPU core 31
There the operation when writing to the register ₃₇ 1 to 37 ₅ of the CPU core 31 via the external bus 27, BCU36 and the internal bus 32 reads information including data and instructions stored in the debug memory 28, FIG. 10
This will be described with reference to the timing chart shown in FIG. First, as the operation state CPUST the CPU core 31, as shown in FIG. 10 (13), a state _{ST 01} requesting access to the debug memory 28, a state _{ST 02} waiting for a response from BCU36 , there is a state _{ST 03} for reading the information from BCU36 to the internal bus 32. On the other hand, the operating state BCUST of the control circuit 54 of BCU36, as shown in FIG. 10 (14), a state _{ST 11} is preparing to access the external bus 27, the state _{ST 12} to send an instruction, information a state ST ₁₃ which prepares to receive and to a state ST ₁₄ receiving the information, the state ST are preparing for outputting information to the internal bus 32
_15, there is a state ST ₁₆ that the post-processing of the transmission and reception of information via the external bus 27.

First, when the CPU core 31 requests access to the debug memory 28, the CPU core 31 shown in FIG.
As shown in, its operating state CPUST state _{ST 01}
As shown in FIG. 10 (2), a memory access request signal ARQ indicating an access request to the debug memory 28 is raised, and the internal bus 32 is shown in FIGS. 10 (6) and (7). Thus, the address AD of the debug memory 28 and the information request command CM which are the targets of the access request are output. Next, when the CPU core 31 determines that the information is to be transferred between the BCU 36 and the debug memory 28 based on the address AD and the information request command CM, as shown in FIG. Then, a signal CMM indicating this is raised. Next, as shown in FIG. 10C, the CPU core 31
An information request signal IRQ indicating that the transfer of the information for which the access request has been made to the CU 36 is raised, and FIG.
As shown in, its operating state CPUST state _{ST 02}
But now I have just requested access and BCU3
6 is not ready to output information to the internal bus 32, and as shown in FIG. 10 (9), a signal indicating that the control circuit 54 is ready to output information to the internal bus 32. SBC has not been launched. Therefore, CP
The U core 31 raises the signal IRQ, and
As shown in (5), a preparation completion signal SBNG which indicates that the internal bus 32 is not ready to use for transferring information from the BCU 36 is raised. This allows
The internal bus 32 is used to transfer information from the BCU 35,
It is used for other than the transfer of information from U36.

On the other hand, the control circuit 54 controls the decoder 51 to decode and take in the address AD output to the internal bus 32 by the CPU core 31.
It is determined that the information is transferred between the BCU 36 and the debug memory 28, and the address AD is temporarily stored in the address buffer 52. Next, when the signal IRQ rises, the control circuit 54, as shown in FIG.
Its operating state BCUST state _{ST 11,} and the the external bus 27 controls the transmission buffer 57 sequentially outputs the command SE and CA to prepare access to the external bus 27 (see FIG. 10 (10)). When the access preparation is completed, the control circuit 54 sets the operation state BCUS
T state _{ST 12,} and the controls the address buffer 52 and the selector 55 supplies the address AD is temporarily stored in the address buffer 52 to the transmission buffer 57, the serial transfer of information shown in FIG. 10 (10) Is supplied to the transmission buffer 57,
The transmission buffer 57 is controlled and transmitted as a command CM to the debug memory 28 via the external bus 27 as shown in FIG.

Next, the transmission of the instruction SFI is completed, a serial response RCM (see FIG. 10 (11)) is received from the debug memory 28 via the external bus 27, and the reception buffer 56 converts the response into parallel. When to supply to the control circuit 54, control circuit 54, the instruction EX its operating state BCUST state _{ST 13,} and the the external bus 27 controls the transmission buffer 57, is prepared to receive the information, U
P, ID, SD and CD are sequentially output (FIG. 10 (1)
0)). When the preparation for receiving the information is completed, the control circuit 54 sets the operation state BCUST to the state S.
T _14, and the external bus and controls the transmission buffer 57 2
7, an instruction SFD for serially receiving information is output (see FIG. 10 (10)). Thus, the information I requested from the debug memory 28 via the external bus 27 is
Since the NF is transmitted serially (see FIG. 10 (11)), the control circuit 54 temporarily stores the serial information INF in the reception buffer 56. Next, when receiving information INF is completed, the control circuit 54 relates to preparation of outputting the operation state BCUST state _{ST 15,} and the the external bus 27 controls the transmission buffer 57, information on the internal bus 32 Outputs commands ED and UD (FIG. 10 (10)
reference). When the output of the instruction ED is completed, the control circuit 54 raises a preparation completion signal SBC indicating that preparation for outputting information to the internal bus 32 has been completed, as shown in FIG. Then, the information INF is transferred to the internal bus 3
When ready to output 2 is completed, the control circuit 54, the operation state BCUST is next state _{ST 16,} the external bus 27 controls the transmission buffer 57, the external bus 27
An instruction IDD for performing post-processing of information transmission / reception via the PC is output (see FIG. 10 (10)).

On the other hand, the CPU core 31 is arranged as shown in FIG.
As shown in, the operating state CPUST the state _{ST 03}
As shown in FIG. 10 (2), the memory access request signal ARQ is raised, and the internal bus 32 is subjected to an access request as shown in FIGS. 10 (6) and (7). Address AD of debug memory 28
And an information request command CM. Next, the CPU core 31 outputs the information request signal I as shown in FIG.
When RQ rises, the ready completion signal SBC rises as shown in FIG. 10 (9).
U36 determines that it is ready to use internal bus 32, and determines that it is ready to use internal bus 32 for the transfer of information from BCU 36, as shown in FIG. The signal SBOK shown rises. Thereby, the control circuit 54 converts the serial information INF temporarily stored in the reception buffer 56 into parallel, and
As shown in (6), the data is output to the internal bus 32.

Note that the CPU core 31 has its operating state C
PUST even in the period of the state _{ST 02} is, FIG. 10
As shown in (2), the memory access request signal ARQ
Are started several times, and the address AD of the debug memory 28 and the information request command CM, which are the targets of the access request, are sent to the internal bus 32 as shown in FIGS. Then, as shown in FIG. 10 (3), the information request signal IRQ rises each time, but as shown in FIG. 10 (9), the control circuit 54 does not raise the ready signal SBC. Therefore, as shown in FIG. 10 (5), the CPU core 31 prepares
Start NG. As a result, the internal bus 32
It is used for purposes other than transferring information from the BCU 36, such as transferring information from the U35.

As described above, according to the configuration of this example, the BCU 36 for controlling the transfer of information between the processor 21 and the debug memory 28 is provided by the ROM 25 and the RAM 25.
26 is provided separately from the BCU 35 connected via the external bus 24, and the debug memory 28 is configured to be connectable to the external bus 27 consisting of only three signal lines. The program can be inspected even when is installed. Therefore, for example, even when an electronic device is sold and a complaint is received from a user, it can be dealt with. Also, BCU
In the same manner as in the mounting state, RO
Since only M25 and RAM 26 are connected, C25
Even when the operating speed of the PU core 31 is high, the electrical characteristics do not deteriorate and the electronic device operates normally, so that the expected program inspection can be performed. Further, since the BCU 36 is provided separately from the BCU 35, there may be a hardware defect such as a short circuit between pins adjacent to the ROM 25 itself, or a connection defect in the external bus 24. However, since it does not affect the debug memory 28, the program inspection can be performed normally and the above-mentioned problem can be found.

According to the configuration of this example, the debug
Since the memory 28 and the ROM 25 are assigned separate and independent memory spaces, the size of the subroutine for inspection is not considered even in the stage of completion or production of a program in which all the memory spaces of the ROM 25 are filled. It can be created and used freely at one time without using it, and there is no need to use cumbersome processing such as replacing with other subroutines or switching a changeover switch, and it is not necessary to use a large-capacity ROM. , And can be configured at low cost. Further, even when a program transferred from the outside is stored in a part of the storage area of the RAM 26, the program can be copied to the debug memory 28 to be inspected.

Although the embodiments of the present invention have been described in detail with reference to the drawings, the specific configuration is not limited to the embodiments, and changes in design and the like can be made without departing from the gist of the present invention. However, the present invention is included in the present invention. For example, in the above-described embodiment, an example in which one internal bus 32 is provided has been described. However, the present invention is not limited to this, and a plurality of internal buses may be provided. In the above-described embodiment, the external bus 27 includes three signal lines, and the processor 21 is provided with three terminals for this purpose. However, the present invention is not limited to this. May be one, and therefore one terminal may be used. Further, in the embodiment described above, two break address registers 42
Although ₁ and 42 ₂ is an example that is provided, without being limited thereto, the break address register may be provided a plurality. Further, the present invention provides a cache memory and a direct memory access controller (D
The present invention can also be applied to a processor provided with a MAC (MAC) or the like, and can check a program even when a problem occurs in information transfer in a cache memory or a DMAC. In the above-described embodiment, the CPU core 31 plays a leading role even in the debug mode. Therefore, even when the information stored in the storage area of the RAM 26 is read, once the CPU core 31 only after written into the internal register 37 _{1-37 5,} it was not possible to write information to the debug memory 28. However, it is not limited to this,
In the debug mode, the control circuit 54 constituting the BCU 36 plays a leading role and uses the idle time of the operation of the CPU core 31 or requests the CPU core 31 to temporarily stop the operation. Alternatively, it may be configured to acquire the right to use 32 and directly read the information stored in the storage area of the RAM 26.

In the above-described embodiment, the ROM 25 and the debug memory 2 are used only in the debug mode.
8 can be accessed and the entire memory space can be used. However, the present invention is not limited to this, and even in the user mode, the CPU core 31 stores both the ROM 25 and the debug memory 28. It may be configured to be accessible. According to this configuration, R
It is possible to freely check the execution of the program, debug, and the like without worrying about the limitation of the memory space of the OM 25. Furthermore, in the above-described embodiment, an example has been described in which an inspection subroutine is created when a software or hardware problem occurs in the operation of an electronic device. However, the present invention is not limited to this. May be created in advance. For example, in general, electronic devices may be made into a series from a single-function type to a popular type and a multi-function type according to the use of the same model. In that case, instead of developing a program for each type separately, for example, for a popular type with basic functions, first develop a program, and based on that program, a function unnecessary for a single function type It is conceivable to develop a program from which the program has been deleted and a program to which a more advanced function is added in the multi-function type. Therefore, a subroutine for inspection created when developing a popular type program may be used when developing a single-function type or multi-function type program. In addition, a subroutine for inspection may be created in advance for a subroutine in which a problem is likely to occur, such as the timing of information transfer, due to restrictions on the functions and specifications of the hardware of the electronic device. In this way, the time for program development can be reduced.

[0059]

As described above, according to the configuration of the present invention, the processor stores the inspection program for inspecting the program to be executed by the central processing unit and the information used at the time of inspecting the program. Since the second transfer control means for controlling the transfer of information to and from the second storage medium is provided separately from the first transfer control means to which the first storage medium is connected, The program can be inspected with a simple and inexpensive configuration, and the program can be accurately inspected in a mounted state in a short time with a simple operation. Further, according to the configuration of the present invention, as in the mounting state, only the first storage medium is connected to the first transfer control means. Therefore, even if the operation speed of the central processing unit is high, The electrical characteristics are not degraded, and the electronic device on which the program is mounted operates normally, and the program can be inspected as expected. further,
Since the second transfer control means is provided separately from the first transfer control means, there is a problem in hardware of the first storage medium itself, and the connection between the first transfer control means and the first storage medium. Even if a connection failure occurs between them, it does not affect the second storage medium, so that the program inspection can be performed normally and the failure can be found. In addition, according to the configuration of the present invention, the number of signal lines connecting the second storage medium and the second transfer control means is changed to the number of signal lines connecting the first storage medium and the first transfer control means. Less than the number of lines. This makes it possible to reduce the number of terminals used at the time of program inspection without lowering the operation speed in the mounted state, thereby suppressing an increase in the chip area of the processor chip due to an increase in the number of terminals. Further, according to the configuration of the present invention, since the second storage medium and the first storage medium are assigned independent memory spaces, all the memory spaces of the first storage medium are filled. In the stage of program completion and product production, the inspection program can be freely created and used at once without worrying about its size, and can be replaced with subroutines that make up the program, and changeover switches can be used. There is no need to perform complicated processing such as switching, and it is not necessary to use a large-capacity storage medium. Furthermore, even in the case where a program transferred from the outside is stored in the RAM constituting the first storage medium, the program can be copied to the second storage medium to be inspected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a program inspection device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of an electrical configuration of a BCU constituting the device.

FIG. 3 is a diagram showing an example of a memory space of an external memory and a debug memory constituting the apparatus.

FIG. 4 is a diagram showing an example of a subroutine used in the device.

FIG. 5 is a diagram showing an example of a subroutine used in the same device.

FIG. 6 is a diagram showing an example of a subroutine used in the same device.

FIG. 7 is a diagram showing an example of a subroutine used in the device.

FIG. 8 is a diagram showing an example of a subroutine used in the device.

FIG. 9 is a flowchart illustrating an example of an operation of the apparatus and an operation of an operator.

FIG. 10 is a timing chart illustrating an example of the operation of the device.

FIG. 11 is a block diagram showing an example of an electrical configuration of a conventional program inspection device.

FIG. 12 is a diagram showing an example of a memory space of an external memory constituting the device.

[Explanation of symbols]

Reference Signs List 21 processor 25 ROM (first storage medium) 26 RAM (first storage medium) 28 debug memory (second storage medium) 29 debug control terminal (program inspection means) 31 CPU core (central processing unit) 35, 36 BCU (first, second transfer control means) ₃₇ 1-37 ₅ register 38 control circuit (second control means) ₃₉ 1, 39 ₂ vector address register 41 PC (program counter) ₄₂ 1, 42 ₂ break address register 43 comparator (comparing means) 51 decoder 52 address buffer 53 data buffer 54 control circuit (first control means) 55 selector 56 reception buffer 57 transmission buffer

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-8-255096 (JP, A) JP-A-5-100905 (JP, A) JP-A 8-185336 (JP, A) JP-A 9-95 319727 (JP, A) JP-A-63-4346 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 11/28-11/36

Claims (10)

(57) [Claims] A first program for storing a program to be executed by a central processing unit and information used when the program is executed.
A first transfer control means for controlling the transfer of instructions and information to and from a first storage medium to which the first memory space is assigned; and a second memory space different from the first memory space, A second transfer control unit that controls transfer of instructions and information to and from a second storage medium in which an inspection program for inspecting the program and information used at the time of inspecting the program are stored; A first transfer control unit; a second transfer control unit; and an internal bus commonly connected to the central processing unit, wherein the second transfer control unit is provided in the second memory space. A first control unit for controlling each unit of the second transfer control unit when a corresponding address is supplied from the internal bus, and converting a parallel address or information from the internal bus into a serial address or information; Processor converted and transferred to the second storage medium, converts the serial address or information from the second storage medium in a parallel address or information, and outputs to the internal bus. 2. The number of signal lines connecting the second storage medium and the second transfer control means is equal to the number of signal lines connecting the first storage medium and the first transfer control means. 2. The processor according to claim 1, wherein the number is less than the number. 3. The apparatus according to claim 1, wherein said second transfer control means reads out information stored in said first storage medium at the time of checking said program and stores it in said second storage medium. Or the processor according to 2. 4. The central processing unit includes: a plurality of registers in which information is temporarily stored; and the program or the program stored in the first or second storage medium via the first or second transfer control unit. Before reading each instruction constituting the inspection program and accessing via the plurality of registers or the first transfer control means.
Using the serial first storage medium, and second control means for sequentially executes each instruction read, the first vector address indicating the first branch destination to be branched to normal interrupt occurs during use Is stored in advance, and a second vector address in which a second vector address indicating a second branch destination to be branched when an interrupt occurs during a program check is stored in advance. An address register for storing an address value of an instruction to be executed next by the second control means, and for each execution of the instruction, the value is sequentially incremented or the first or second vector A program counter to which the first or second vector address is supplied from the address register, and an address of a branch source to temporarily interrupt the operation of the program by the second control means and generate an interrupt A plurality of break address registers, each of which stores a break address, which is an address of a destination address, and an interrupt vector, which is an address address of a branch destination to be branched when an interrupt occurs during a program check, An output value of the program counter is compared with a plurality of break addresses supplied from the plurality of break address registers, and when they match, an interrupt signal is supplied to the second control means. The processor according to any one of claims 1 to 3, further comprising a comparison unit that performs the comparison. 5. The second transfer control means, the first control means, a decoder for decoding an address transferred from the central processing unit, and a temporary storage of the address transferred from the central processing unit. An address buffer, a data buffer for temporarily storing information transferred from the central processing unit, and selecting one of an address supplied from the address buffer and information supplied from the data buffer. A selector to output, a reception buffer that temporarily holds serial information transferred from the second storage medium, converts the serial information to parallel information and outputs the parallel information, and a parallel address or information transferred from the selector. After temporarily holding the command supplied from the first control means, the command is converted into a serial address or information and output. A transmission buffer, wherein the first control means controls each unit of the device when an address decoded by the decoder is an address corresponding to the second memory space. A processor according to any one of claims 1 to 4. 6. The apparatus according to claim 1, wherein said central processing unit, said first transfer control means, and said second transfer control means are formed in the same chip. The processor according to claim 1. 7. The processor according to claim 6, further comprising at least one terminal for connecting said second storage medium and said second transfer control means. 8. An electronic device, comprising the processor according to claim 1 and being connectable to the second storage medium. 9. The first storage device by connecting the second storage medium storing the inspection program to the electronic device according to claim 8, and executing the program and the inspection program. A program inspection method for inspecting the program based on information read from a medium and a plurality of registers constituting the central processing unit and stored in the second storage medium. 10. The electronic device according to claim 8, wherein the inspection program is stored, the second storage medium connected to the electronic device, and the program and the inspection program are executed. Program inspection means for inspecting the program based on information read from a plurality of registers constituting the first storage medium or the central processing unit and stored in the second storage medium. A program inspection apparatus, comprising: