JP3239875B2 - Thin film transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, and more particularly to a high breakdown voltage thin film transistor used by applying a voltage to a sub-gate electrode provided on an offset region.

[0002]

2. Description of the Related Art In a high breakdown voltage thin film transistor according to the present invention, it is required to obtain a high on-current while maintaining a high breakdown voltage. For this purpose, electron
Device Letters June 1990, Vol.11, No.6, p.244,
Fig.1 (IEEE ELECTRON DEVICESLETTERS, Vol.11, No.6, J
As shown in UNE 1990), a configuration is known in which an offset region is provided between an active region and a drain region, and an electrode is provided so as to cover the offset region with an insulating film interposed therebetween.

Such a conventional high-breakdown-voltage N-type thin film transistor will be described with reference to FIG. As shown in FIG. 6, a base insulating film 111 is formed on an insulating substrate 101, and a patterned semiconductor layer 112 is formed on the base insulating film 111. The semiconductor layer 112 includes a source region 142, an active layer 131,
An offset region 132 not doped with an impurity and a drain region 141 are provided.

[0004] A first interlayer insulating film 151 is formed to cover the semiconductor layer 112, and a gate electrode 121 is formed on the active layer 131 with the first interlayer insulating film 151 interposed therebetween. Further, a second interlayer insulating film 152 is formed to cover the gate electrode 121. Offset area 132
A sub-gate electrode 122 is formed thereon with the first interlayer insulating film 151 and the second interlayer insulating film 152 interposed therebetween. The source region 142 is connected to the source electrode 144, and the drain region 141 is connected to the drain electrode 143 via contact holes.

Next, the operation of the high breakdown voltage thin film transistor having the above structure will be described. In an N-type transistor in which an N-type impurity is doped into the source region 142 and the drain region 141, carriers are induced in the offset region 132 by applying a positive voltage to the sub-gate electrode 122, so that the offset region 132 and the drain region 141 Can be alleviated near the boundary of. In the report example,
It is stated that the withstand voltage characteristics can be optimized when a voltage slightly larger than half the drain voltage is applied to the sub-gate electrode 122.

[0006]

However, when the thin film transistor is operated under the condition that the drain voltage is higher than 100 V, the offset region 13
In order to suppress the electric field concentration at the boundary between the gate electrode 2 and the drain region 141, it is necessary to increase the voltage applied to the gate electrode 122. If the sub-gate voltage is increased, the following problem occurs.

The first problem is that since the electric field strength near the active layer 131 and the offset region 132 increases, the maximum value of the sub-gate voltage is limited by the insulating film thickness under the sub-gate electrode 122. The second problem is that charges generated by impact ionization due to a high electric field near the boundary between the drain region 141 and the offset region 132 are injected into the insulating film between the offset region 132 and the sub-gate electrode 122, and this hot carrier effect This causes the sub-gate characteristics to fluctuate.

The present invention has been made in view of the above problems, and a main object of the present invention is to provide a high-breakdown-voltage thin-film transistor which can operate without a change in characteristics even when a drain voltage is set high. Is to provide.

[0009]

According to a first aspect of the present invention, a semiconductor layer including a source region, a drain region, and an active region is formed on a substrate. A non-doped offset region is disposed between at least one of the active region and the source region or between the active layer and the drain region, and a first interlayer is formed on the active region. A thin film transistor having a gate electrode formed via an insulating film, and a sub-gate electrode formed at a position corresponding to the offset region on a second interlayer insulating film formed to cover the gate electrode and the semiconductor layer; The distance between the sub-gate electrode and the offset region gradually increases from the end of the source region or the drain region toward the end of the active region. As it will be large, in which the sub-gate electrode is formed.

According to a second aspect of the present invention, in a second aspect, a semiconductor layer including a source region, a drain region, and an active region is formed on a substrate, and the semiconductor layer includes a region between the active region and the source region. Alternatively, at least one of the active layer and the drain region is provided with an offset region that is not doped with an impurity, and a gate electrode is formed on the active region via a first interlayer insulating film; In a thin film transistor in which a sub-gate electrode is formed at a position corresponding to the offset region on a second interlayer insulating film formed so as to cover a gate electrode and the semiconductor layer, the second interlayer insulating film on the offset region The insulating film
The sub-gate electrode is formed to be gradually thicker from the source region or the drain region toward the active layer, and the sub-gate electrode on the second interlayer insulating film is formed with a gentle inclination with respect to the substrate plane. .

According to a third aspect of the present invention, there is provided a method of manufacturing a thin film transistor. In the manufacturing method, a semiconductor layer is formed on a substrate via a base insulating film, a source region, a drain region, an active region, and an offset region are provided in the semiconductor layer, and a first interlayer insulating film is formed on the active region. After forming a gate electrode through the film, a second interlayer insulating film is formed so as to cover the gate electrode and the semiconductor layer, and a sub-gate electrode is formed on the second interlayer insulating film at a position corresponding to the offset region. And disposing a flattening agent having a predetermined viscosity at the time of forming the second interlayer insulating film, and heating and solidifying the second interlayer insulating film to form the thin film transistor. At least a step of gently filling the step is provided.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION In a preferred embodiment of the high breakdown voltage thin film transistor according to the present invention, an active region (31 in FIG. 1), a source region (42 in FIG. 1), A drain region (41 in FIG. 1) and an offset region (32 in FIG. 1) are provided so as to cover the first interlayer insulating film (51 in FIG. 1) deposited on the active region and the gate electrode on the active layer. After forming a second interlayer insulating film,
The level difference on the substrate is made gentle by a flattening film (53 in FIG. 1) formed by applying a flattening agent having a predetermined viscosity, and a sub-gate electrode is formed at a position corresponding to the offset region on the flattening film.

[0013]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

Embodiment 1 A high-breakdown-voltage thin-film transistor according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view illustrating the configuration of the high-breakdown-voltage thin-film transistor according to the first embodiment. Also, FIG.
FIG. 4 is a process cross-sectional view schematically illustrating a part of the manufacturing process of the high breakdown voltage thin film transistor.

First, the structure of the high-breakdown-voltage thin-film transistor of this embodiment will be described with reference to FIG. In this embodiment, an N-ch thin film transistor will be described. In the N-ch thin film transistor of this embodiment, an offset region 32 containing almost no impurities is provided between an active layer 31 and a drain region 41 in a semiconductor layer 12 made of polycrystalline silicon. The sub-gate electrode 22 is formed with the interlayer insulating film 51, the second interlayer insulating film 52, and the flattening film 53 interposed therebetween.

Here, the thickness of the insulating film between the offset region 32 and the sub-gate electrode 22 gradually increases from the drain region 41 toward the active layer 31. Is d1, the second
The thickness of the interlayer insulating film 52 is d2, the thickness of the planarizing film is d3,
The thickness of the gate electrode 21 is dg, and the offset region 32
Assuming that the insulating film thickness between the gate electrode 22 and the sub-gate electrode 22 is dd on the drain region 43 side and di on the active layer 31 side, dd = d
1 + d2 + d3, and di = d1 + d2 + d3 + dg.

Next, a method of manufacturing the thin film transistor having the above structure will be described with reference to FIG. First, FIG.
As shown in FIG. 1A, a semiconductor layer 12 made of polycrystalline silicon is formed on an insulating substrate 1 covered with a base insulating film 11. A part of the semiconductor layer 12 is doped with, for example, phosphorus to form a source region 42 and a drain region 41, and the active layer 31 containing almost no impurities and the offset are formed between the source region 42 and the drain region 41. A region 32 is formed.

Subsequently, the source region 42 and the drain region 4
1. A first interlayer insulating film 51 is formed to cover the active layer 31 and the offset region 32, and a gate electrode 21 is formed on the active layer 31 with the first interlayer insulating film 51 interposed therebetween. After this,
A second interlayer insulating film 52 is formed so as to cover the gate electrode 21.

Next, as shown in FIG. 2B, a flattening agent such as silica is applied by a coating method and then heated to form a flattening film 53. At this time, if a coating film having a viscosity equal to or less than a predetermined value is selected, when the gap between the steps is wide, the coating film accumulates in the step portion, and the flattening film 53 having a slope as shown in the figure can be formed. it can. In this embodiment, the coating method is used as the flattening method.
By using a method of flattening by thermal diffusion after depositing a G film or the like, a flattening film 53 having a similar inclination can be formed.

Next, as shown in FIG. 2C, the first interlayer insulating film 51 and the second
The sub-gate electrode 22 is formed with the interlayer insulating film 52 and the flattening film 53 interposed. The source region 42 is connected to the source electrode 44 via the contact hole, and the drain region 41 is connected to the drain electrode 43 via the contact hole, whereby the basic structure of the high breakdown voltage thin film transistor of the present embodiment is formed. .

Next, the operation of the high-breakdown-voltage thin-film transistor of this embodiment will be described with reference to FIG. The source electrode 44 of the N-type transistor is set to the ground potential, and the drain electrode 4
3, a power supply voltage VDD is applied, a sub-gate electrode 22 is applied with a positive voltage VSUB, and a gate electrode 21 is applied with a voltage between ground level and VG. Here, VG is VD
The voltage is lower than D. The switching of the N-type transistor is controlled by a voltage VG applied to the gate electrode 21. The offset region 32 sandwiched between the active layer 31 and the drain region 41 functions as a buffer region for reducing the electric field from the drain region 41.

In this embodiment, a flat film 53 is formed on the second interlayer insulating film 52, so that the film thickness between the offset region 33 and the sub-gate electrode 22 is smoothly changed between dd and di. When VSUB is applied to the sub-gate electrode 22, the offset region 3
2 is also applied to the offset region 32.
The carrier density induced in the offset region 32 is high at the boundary of the drain region 41 and is low near the boundary of the active layer 31. As a result, the carrier density also has a gentle gradient.

Accordingly, since the gradient of the electric field at the junction between the offset region 32 and the drain region 41 becomes gentle, the peak of the lateral electric field generated by applying the drain voltage can be reduced. An improvement in withstand voltage can be achieved. Further, generation of hot carriers generated by a high electric field at the end of the drain region 41 can be suppressed, and resistance to hot carriers can be improved.

The above-described carrier density distribution in the offset region 32 indicates that the first interlayer insulating film 51 and the second interlayer insulating film 52
In addition, when the dielectric constant of the flattening film 53 is constant, the thickness is determined by the thickness ratio of dd and di. Therefore, when the thickness dg of the gate electrode 21 is smaller than dd, the carrier concentration is substantially determined by dd. . Therefore, at least dg <1/2 ×
It is preferable that the structure satisfy the relationship of dd. Also,
When the dielectric constant of the planarizing film 53 is e1, and the dielectric constants of the first interlayer insulating film 51 and the second interlayer insulating film 52 are e2, e1 ×
The relationship dg <1/2 × e2 × dd may be satisfied.

Embodiment 2 Next, a high breakdown voltage thin film transistor according to a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a cross-sectional view illustrating the structure of the high breakdown voltage thin film transistor according to the second embodiment.

This embodiment is different from the first embodiment in that the first interlayer insulating film 51 is provided only below the gate electrode 21 in this embodiment. That is, in the present embodiment, after the first interlayer insulating film is formed so as to cover the semiconductor layer 12, the first interlayer insulating film 51 is also etched at the time of etching for forming the gate electrode 21. It is characterized in that the first interlayer insulating film 51 is removed.

The subsequent manufacturing method is the same as in the first embodiment described above. After forming the second interlayer insulating film 52 covering the gate electrode 21, application of a flattening agent having a predetermined viscosity and heating are performed. Then, a flattening film 53 is formed. And the first
Interlayer insulating film 51, second interlayer insulating film 52, and planarizing film 53
The sub gate electrode 22 is formed through the
Is a source electrode 44 through a contact hole, and the drain region 41 is a drain electrode 4 through a contact hole.
Connect to 3.

With such a structure, the insulating film thickness between the offset region 32 and the sub-gate electrode 22 is dd = d2 + d3 on the drain region 41 side, and di = d1 + d2 + d3 + dg on the active layer 31 side. Accordingly, the inclination angle of the planarizing film 53 can be made larger than that of the first embodiment.

Therefore, the carrier density induced in the offset region 32 can be high at the boundary of the drain region 41 and low near the boundary of the active layer 31, thereby improving the breakdown voltage and improving the resistance to hot carriers. Can be improved. Further, in the present embodiment, the thickness dg of the gate electrode required to obtain the same inclination angle of the flattening film 53 as in the first embodiment is reduced by d1, so that the thickness of the gate electrode 21 is reduced. Can be.

Embodiment 3 Next, a high breakdown voltage thin film transistor according to a third embodiment of the present invention will be described with reference to FIG. FIG. 4 is a process cross-sectional view schematically showing a manufacturing process of the high breakdown voltage thin film transistor according to the fourth embodiment. The difference between this embodiment and the first embodiment is that, in this embodiment, after forming the flattening film 53, a part of the interlayer insulating film is removed together with the flattening film.

First, as shown in FIG. 4A, a base insulating film 11 and a semiconductor layer 12 made of polycrystalline silicon are formed on an insulating substrate 1 in the same manner as in the first embodiment. A part of the layer 12 includes a source region 42 and a drain region 4.
The active layer 31 and the offset region 32 containing almost no impurities are formed between the source region 42 and the drain region 41. Subsequently, the first interlayer insulating film 51
Is formed, and the gate electrode 21 is formed on the active layer 31 with the first interlayer insulating film 51 interposed therebetween. Thereafter, a second interlayer insulating film 52 is formed to cover the gate electrode 21. At this time, in order to remove a part of the second interlayer film 52 in a later step, the second interlayer insulating film 52 is deposited thicker than in the first embodiment. I have. Then, a flattening film 53 is formed by applying and heating a predetermined viscosity flattening agent.

Next, as shown in FIG. 4B, in this embodiment, a part of the flattening film 53 and the second interlayer insulating film 52 is removed by using a technique called etch back. At this time, isotropic etching is performed under the condition that the etching rates of the flattening film 53 and the second interlayer insulating film 52 are substantially equal, so that the second interlayer insulating film 52 is etched in a form reflecting the shape of the flattening film 53. Is done.

Next, as shown in FIG. 4C, a sub-gate electrode 22, a source electrode 44 and a drain electrode 43 are formed. As a result, the second interlayer insulating film between the sub-gate electrode 22 and the offset region 32 can be inclined, so that the carrier density induced in the offset region 32 is high at the boundary of the drain region 41 and near the boundary of the active layer 31. Thus, the breakdown voltage can be improved, and the resistance to hot carriers can be improved.

In the first embodiment, the flattening film 53 is used as a part of the insulating film. However, if the MIS interface under the sub-gate electrode 22 contains impurities such as mobile ions, The characteristics of the sub-gate portion fluctuate, and the reliability decreases. For example, a flattening film 5 formed using silica
No. 3 has a problem that it contains more impurities than the insulating film formed by the vapor deposition method. On the other hand, in the present embodiment, the MIS under the sub-gate is removed by removing the planarizing film 53.
The quality of the interface can be improved, and the reliability of the thin film transistor can be improved.

Embodiment 4 Next, a high breakdown voltage thin film transistor according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 5 is a process sectional view schematically showing a part of the manufacturing process of the high breakdown voltage thin film transistor according to the fourth embodiment. The difference between this embodiment and the above-described second embodiment is that, in this embodiment, a flat interlayer 53 is formed on the gate electrode 21 and then a second interlayer insulating film 52 is deposited. .

The manufacturing method of this embodiment will be described.
First, a base insulating film 11 and a semiconductor layer 12 are formed on an insulating substrate 1 in the same manner as in the second embodiment.
2, a source region 42, a drain region 41, an active layer 31, and an offset region 32 are formed. Subsequently, after the formation of the first interlayer insulating film 51, the first interlayer insulating film 51 is also etched during the etching for forming the gate electrode 21, and the first interlayer insulating film 51 other than immediately below the gate electrode 21 is removed.

Subsequently, in the above-described first to third embodiments, the second interlayer insulating film 52 is formed. However, in this embodiment, as shown in FIG. Chemical film 5
Form 3 Thereafter, as shown in FIG.
An interlayer insulating film 52 is deposited, and a sub-gate electrode 22, a drain electrode 41, and a source electrode 42 are formed.

By forming in this manner, a gradient is formed in the insulating film thickness between the offset region 32 and the sub-gate electrode 22, and a gradient can be provided in the carrier concentration of the offset region 32. Therefore, offset region 3
2 can be high at the boundary of the drain region 41 and low near the boundary of the active layer 31, so that the withstand voltage can be improved and the resistance to hot carriers can be improved. Further, the shape in which the first interlayer insulating film 51 is left only below the gate electrode 21 has been described. However, similar to the first and third embodiments, the first interlayer insulating film 51 is formed entirely. Is also good.

In the first to fourth embodiments described above, an example in which the present invention is applied to an N-type transistor has been described. However, the present invention is not limited to the above-described embodiment, and may be applied to a P-type transistor. Can be similarly applied. Although the configuration in which the sub-gate electrode is provided only on the drain side is described, it is also possible to provide the sub-gate electrode on both the drain side and the source side.

[0040]

As described above, according to the structure of the present invention, the carrier density induced in the offset region can be gradually reduced from near the boundary between the drain region and the offset region toward the active layer. Therefore, there is an effect that the withstand voltage can be improved and deterioration due to hot carriers generated by a high electric field near the drain boundary can be suppressed.

The reason is that a flattening agent having a predetermined viscosity is applied to form a flattening film, and the leveling film of the gate electrode is filled with the flattening film to reduce the thickness of the insulating film between the offset region and the sub-gate electrode. From the vicinity of the boundary between the drain region and the offset region, it is possible to have a slope such that the thickness gradually increases toward the vicinity of the boundary between the active layer and the offset region, and the carrier density in the offset region is also high at the boundary of the drain region. This is because it can be gradually lowered.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a high-breakdown-voltage thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a process sectional view for explaining a part of the method of manufacturing the high breakdown voltage thin film transistor according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a structure of a high-breakdown-voltage thin-film transistor according to a second embodiment of the present invention.

FIG. 4 is a process sectional view for explaining a part of the method of manufacturing the high withstand voltage thin film transistor according to the third embodiment of the present invention.

FIG. 5 is a process cross-sectional view for explaining a part of the method of manufacturing the high withstand voltage thin film transistor according to the fourth embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating the structure of a conventional high-breakdown-voltage thin film transistor.

[Explanation of symbols]

 1, 101 Insulating substrate 11, 111 Base insulating film 12, 112 Semiconductor layer 21, 121 Gate electrode 22, 122 Sub-gate electrode 31, 131 Active layer 32, 132 Offset region 41, 141 Drain region 42, 142 Source region 43, 143 Drain electrode 44, 144 Source electrode 51, 151 First interlayer insulating film 52, 152 Second interlayer insulating film 53 Flattening film

Claims (14)

(57) [Claims] 1. A semiconductor layer including a source region, a drain region and an active region is formed on a substrate, and a semiconductor layer between the active region and the source region or between the active layer and the drain region is formed on the semiconductor layer. An offset region in which no impurity is doped is disposed in at least one of the regions, a gate electrode is formed on the active region via a first interlayer insulating film, and covers the gate electrode and the semiconductor layer. In a thin film transistor in which a sub-gate electrode is formed at a position corresponding to the offset region on the formed second interlayer insulating film, a distance between the sub-gate electrode and the offset region is
The thin-film transistor, wherein the sub-gate electrode is formed so as to gradually increase in size from the end of the source region or the drain region toward the end of the active region. 2. A semiconductor layer including a source region, a drain region and an active region is formed on a substrate, and a semiconductor layer between the active region and the source region or between the active layer and the drain region is formed on the semiconductor layer. An offset region in which no impurity is doped is disposed in at least one of the regions, a gate electrode is formed on the active region via a first interlayer insulating film, and covers the gate electrode and the semiconductor layer. A thin film transistor in which a sub-gate electrode is formed on a formed second interlayer insulating film at a position corresponding to the offset region, wherein the second interlayer insulating film on the offset region is the source region or the drain From the region toward the active layer, the sub-gate electrode on the second interlayer insulating film is gently A thin film transistor formed with an inclination. 3. The thin film transistor according to claim 1, wherein the second interlayer insulating film includes a flattening film that gently fills a step of the gate electrode. 4. The thin film transistor according to claim 3, wherein said flattening film is a film formed by applying, heating and solidifying a flattening agent having a predetermined viscosity. 5. The thin film transistor according to claim 3, wherein said flattening film is a film formed by depositing and thermally diffusing BPSG. 6. The thin film transistor according to claim 1, wherein the first interlayer insulating film is formed only below the gate electrode. 7. When the thickness of the gate electrode is dg and the distance between the offset region at the end of the source region or the drain region and the sub-gate electrode is dd, dg and dd are equal to dg. 7. The method according to claim 1, wherein the setting is made so as to satisfy a relationship of <dd / 2.
The thin film transistor according to any one of the above. 8. The thickness of the gate electrode is dg, the distance between the offset region at the end of the source region or the drain region and the sub-gate electrode is dd, the dielectric constant of the planarizing film is e1, When the dielectric constant of the first interlayer insulating film and the second interlayer insulating film (excluding the planarizing film) is e2, dg, dd, e1, and e2 are d
The thin film transistor according to any one of claims 1 to 6, wherein the relationship is set so as to satisfy a relationship of g x e1 <dd x e2 / 2. 9. A semiconductor layer is formed on a substrate with a base insulating film interposed therebetween, a source region, a drain region, an active region, and an offset region are provided in the semiconductor layer.
After forming a gate electrode via the interlayer insulating film, a second interlayer insulating film is formed to cover the gate electrode and the semiconductor layer, and a position corresponding to the offset region on the second interlayer insulating film is formed. A step of disposing a sub-gate electrode in the thin-film transistor, the method comprising the steps of: applying a flattening agent having a predetermined viscosity and heating / solidifying the gate electrode when forming the second interlayer insulating film; At least a step of gently filling a step generated by the method. 10. A semiconductor layer is formed on a substrate via a base insulating film, a source region, a drain region, an active region and an offset region are provided in the semiconductor layer, and a first interlayer insulating film is formed on the active region. After forming a gate electrode through the film, a second interlayer insulating film is deposited so as to cover the gate electrode and the semiconductor layer, and a sub-gate electrode is formed on the second interlayer insulating film at a position corresponding to the offset region. Forming a second interlayer insulating film, after depositing BPSG,
A method for manufacturing a thin film transistor, comprising at least a step of gently filling a step created by the gate electrode by thermal diffusion. 11. A semiconductor device comprising: (a) forming a semiconductor layer on a substrate via a base insulating film; (b) forming a source region, a drain region, and an active region in the semiconductor layer; Disposing an undoped offset region between at least one of an active region and the source region or between the active layer and the drain region; and (d) a first offset region on the active region. Forming a gate electrode via an interlayer insulating film; (e) depositing a second interlayer insulating film so as to cover the gate electrode and the semiconductor layer; and (f) forming the second interlayer insulating film. Applying a flattening agent having a predetermined viscosity thereon to form a flattening film that gently fills the step created by the gate electrode; and (g) a position corresponding to the offset region on the flattening film. Sub game Method of manufacturing a thin film transistor comprising the steps of disposing the electrode. 12. A semiconductor device comprising: (a) forming a semiconductor layer on a substrate via a base insulating film; (b) forming a source region, a drain region and an active region in the semiconductor layer; Disposing an undoped offset region between at least one of an active region and the source region or between the active layer and the drain region; and (d) a first offset region on the active region. Forming a gate electrode via an interlayer insulating film; (e) depositing a second interlayer insulating film so as to cover the gate electrode and the semiconductor layer; and (f) forming the second interlayer insulating film. A step of applying a flattening agent having a predetermined viscosity thereon to form a flattening film that gently fills a step created by the gate electrode; and (g) forming a flattening film and the second interlayer insulating film. Etch back some And (h) arranging a sub-gate electrode at a position corresponding to the offset region on the second interlayer insulating film. A method for manufacturing a thin film transistor. 13. A semiconductor device comprising: (a) forming a semiconductor layer on a substrate via a base insulating film; (b) forming a source region, a drain region, and an active region in the semiconductor layer; Disposing an undoped offset region between at least one of an active region and the source region or between the active layer and the drain region; and (d) a first offset region on the active region. Forming a gate electrode via an interlayer insulating film; and (e) covering the gate electrode and the semiconductor layer.
A step of applying a flattening agent having a predetermined viscosity to form a flattening film that gently fills a step created by the gate electrode; and (f) depositing a second interlayer insulating film on the flattening film. And (g) disposing a sub-gate electrode at a position corresponding to the offset region on the second interlayer insulating film. 14. The method according to claim 11, wherein the step of forming the gate electrode comprises removing the first interlayer insulating film other than the part below the gate electrode. A method for manufacturing a thin film transistor.